Achieving High Aspect Ratio TSVs


An Integrated Deep Silicon Etch/Directional PVD Process

BY THOMAS EISENHAMMER, et al. Oerlikon Balzers Ltd.

This 3 issue series takes a snapshot of where 3D packaging technologies are at both wafer and package levels, and also where they’re headed. Technology features will cover such topics as the TSV process from via etch and fill to interconnect, alternate methods of 3D stacking, material considerations for 3D stacking, 3D wafer aligning and bonding, and reliability testing of 3D packages.

Driving forces for 3D integration have been clearly identified and through-wafer via (TSV) technology continues to move closer to high volume production. However, many questions are still investigated, such as which aspect ratios (ARs) for vias will be required and what materials and techniques will be able to fill them.

Copper is the preferred interconnect metal for advanced CMOS devices due to low resistivity and desirable electro-migration characteristics. It is also widely used in wafer-level packaging (WLP) applications such as under-bump metal (UBM) and redistribution layer technology (RDL). Copper interconnects are produced by sputtering a thin seed layer onto a barrier metal film followed by electroplating to desired thickness. In via structures, it has been necessary to deposit these layers with advanced directional sputtering techniques to ensure sufficient bottom and sidewall coverage. The highest AR for features that could reliably be filled has been in the range 5:1 up to may be 10:1; limited by the ability of enhanced physical vapor deposition (PVD) techniques to deliver sufficient material to the lower sidewalls of the vias. However, many proposed interconnect structures require ARs of greater than 10:1; and better PVD methods are needed.

An integrated deep silicon etch (DSE) / advanced directional sputtering process was developed to provide enhanced metal bottom and sidewall coverage in features with vertical sidewalls and ARs up to 30:1. The DSE process produces a smooth via in a Si wafer with no overhang and minimal scalloping, making continuous coverage with the PVD metal films feasible. PVD data demonstrate continuous metal coverage up to 9% at the bottom of 30:1 features — sufficient for subsequent filling by electroplating. A novel process can extend the current limit of PVD + electroplated Cu metallization schemes for 3D packaging applications.

DSE Process

The vias were etched into the silicon substrate using a time division multiplexed (TDM) process, also known as the Bosch process, which consists of a series of alternating etch and deposition steps. SF6 is used to etch Si at a high rate and with a high selectivity to the mask material, but with an isotropic etch profile. In the deposition step, C4F8 is used to deposit an etch-resistant polymer on all exposed surfaces. Prior to the next etch step, the polymer is removed anisotropically from the bottom of the vias so that during the etch step the via sidewalls are protected from lateral etching. Thus, a vertical etch profile is approximated by a series of isotropic etches, producing features referred to as notches, or scallops, and contribute to the sidewall roughness within the via (Figure 1).

Figure 1. Variation of sidewall roughness with etch and deposition step duration.
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The magnitude of these scallops is determined by the amount of silicon removed during the etch step and is a function of both the silicon etch rate and the etch step duration. Therefore, to minimize edge roughness, either the silicon etch rate or the step duration can be reduced. If the step time is reduced too much, then the individual steps tend to “smear” together and the advantages of the TDM process are lost, typically manifested as a loss in etch rate. The effect of etch and deposition step duration on edge roughness is shown in Figure 1. Note that these features were etched for the same total time: the fact that the features maintain the same depth illustrates that little etch rate reduction was incurred.

To obtain short step times, system design and operation must be optimized to allow rapid and reproducible response from critical components (gas flow and pressure controllers, RF match controller), their settings changing from step to step. To maintain accurate gas flow control, a fast gas switching method is used, whereby the gas flow is kept constant but the gas is either fed to the process module or “dumped” to exhaust. For accurate pressure control via a throttle valve, a proprietary algorithm is used: the valve is initially positioned based on the throttle valve position averaged over previous steps of a like kind (i.e. etch or deposition step). The algorithm then switches to conventional pressure control based on pressure feedback. Since plasma impedance also changes between deposition and etch steps, rapid response of RF matching is required. This is ensured by using matching networks with fixed capacitors, but varying the RF frequency over a small range reducing the matching time to a few 10s of ms. This way, step times of 0.5 – 1.0 seconds can reproducibly be used, resulting in a good balance between etch rate and sidewall roughness. Figure 2 shows such a relationship for small (2.5 µm) features. For larger features, a similar relationship holds with etch rates in the range 8-10 µm/min.

Figure 2. Variation of silicon etch rate with etch step duration for small via diameter of 2.5 μm.
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Advanced Directional Sputtering (ADS)

A conventional approach to metal sputter deposition in silicon vias uses a large distance between target and substrate (TSD), typically about 1.5 times the substrate diameter. This allows the sputtered material to deposit perpendicularly to the substrate surface, successfully filling high AR structures. An undesired consequence is a reduced deposition rate which can be overcome by a multi-chamber tool configuration. Further advantages of this sputter chamber design are low risk of substrate damage and low particle generation.

RF bias on the substrate is an essential part of ADS for achieving optimum step coverage by enhancing the deposition direction perpendicular to the substrate. Material deposition at the upper corners of vias is also reduced by RF-bias-induced sputter etching. It redistributes material deposited in the via to increase sidewall deposition, and increases film adhesion and reduces tensile film stress, which is advantageous for thick Cu layers. The thermal impact of the RF bias on the substrate can be reduced by electrostatic clamping and backgas cooling.

Figure 3 shows SEM cross-sections of a trench with AR 8:1, sputtered with Ti as adhesion and barrier metal and Cu as seed layer for plating. Clearly visible is the step coverage for this 8:1 AR trench with 15% bottom coverage, compared to the field thickness for Ti and 10% for Cu. Thus, ADS is an appropriate solution for current and near future TSV applications such as flash memory, DRAM, and image sensors.

Figure 3. SEM cross sections of Ti and Cu films deposited with ADS in a trench with AR 8:1 analyzed for the locations upper sidewall (Up), middle sidewall (M), lower sidewall (L) and bottom (B).
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Highly Ionized Sputter Process

A sputtering process was introduced that allows for high ionization levels of the sputtered target material1, called high power pulsed magnetron sputtering (HPPMS). A short (< 0.2ms) electrical current pulse with high currents of several hundred up to >1000A is used to produce a dense plasma for sputtering the target material. The current densities are up to 2 orders of magnitude higher than in conventional sputtering. Under these conditions the sputtered target material is ionized immediately, obtaining high ionization level. For sputtering of Ti, an ionization level > 90% has been found near the target surface2, and > 60% metal ionization has been reported in the afterglow of HPPMS plasmas.3

This technology has been studied for hard coating application.4 However, little or no research has been presented for applications in semiconductor technology. A new HPPMS technology called “highly ionized sputtering” HIS has been developed and was implemented. RF-bias on the substrate is used for the acceleration of metal ions to reach the substrate perpendicularly to the substrate surface.

In contrast to the long throw sputtering technology or to conventional ionized PVD, the TSD for HIS can be quite small; actually a TSD as in conventional sputtering in the range of 30-80 mm was used. Furthermore, in conventional ionized sputtering the gas pressure usually is quite high, in the range of 2-5Pa. For HPPMS efficient ionization is also obtained at pressures <1Pa. Due to the small TSD and low gas pressure, the energy of the target ions deposited on the substrate is high causing a dense film structure. Another advantage of a small TSD is the high material usage compared to long throw sputtering, or conventional ionized PVD.


The Ti process provides a bottom coverage of up to 20% in trenches with AR 10:1 at a deposition rate of 26 Å/s. There is practically no inboard/outboard effect visible for trenches of these high aspect ratios near the wafer edge. Figure 4 shows SEM cross sections of a Ta layer on the bottom and lower sidewalls of a DSE trench with an AR of 30:1. A substantial amount of material is deposited in the bottom of the trench, even in the most critical areas at the edges of the bottom close to the trench wall and in the shadow of the DSE scallops.

Figure 4. Ta layer deposited with HIS on the bottom and sidewall scallops of a trench with AR of 30:1.
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These processes developed for Ti, Ta and Cu show that current limits of PVD + electroplated Cu metallization schemes for 3D packaging applications can be extended. AP


1. Plasma Physics Reports, Vol. 21, No. 5, 1995, pp. 400-409; US patent 06296742.

2. J. Bohlmark et al., J. Vac. Sci. Technol. A 23 (1) Jan/Feb 2005.

3. Poucques et al., Plasma Sources Technol. 15 (2006) 661-669.

4. A.P. Ehiasarian et al., Thin Solid Films 457 (2004) 270-277.

THOMAS EISENHAMMER, head of R&D business unit systems; JÜRGEN WEICHART, team leader advanced product development, MOHAMED ELGHAZZILI, senior process engineer; CHRISTIAN LINDER, process engineering manager PVD wafer; SIMONE VON ALLMEN, process engineer, ANDREAS ERHART; product marketing manager Asia; WOLFGANG RIETZLER; product manager Clusterline; GLYN J. REYNOLDS, principal scientist; DAVID J. JOHNSON, senior r&d manager; CHRIS JOHNSON, applications engineer; and MIKE DEVRE, senior process engineer may be contacted at Oerlikon Balzers Limited, FL-9496 Balzers, Liechtenstein; E-mail:;;;;;;;;;;