Issue



Package-on-package (PoP) with Through-mold Vias


01/01/2008







Package on Package (PoP) stacking has become the preferred method for 3D integration of baseband ICs or ASICs with high-performance memory in mobile multimedia applications. Market trends require migration to flip chip interconnects for higher pin count and electrical performance demanded in next-generation multi-core processors. Also, higher data transfer rates and wider bus memory architectures are driving increased pin-count in PoP memory stacking interfaces. Future applications are demanding a PoP base package with increased interconnect density, reduced pitch, reduced package size and thickness, improved warpage control, reduced tooling cost, and capability to handle various interconnect configurations including flip chip, stacked die, and passive component integration. To address these challenges, a PoP base package using a standard FBGA package structure with through-mold vias (TMV) has been developed.

The package is based on a standard FBGA package with wire bond, flip chip or stacked die interconnect. After molding, a blind via is created through the mold compound, exposing PoP bond pads on the package substrate’s top metal layer. The vias are partially filled with a conductive material before final processing, resulting in a a fully molded FBGA package with a conductive, blind via PoP interface.

This structure was demonstrated for a high-density PoP application using a 14 × 14-mm molded PoP base package. The bottom BGA array contains 620 balls at 0.4-mm pitch. The top PoP BGA array contains 200 PoP bond pads in a 2 row, 0.5-mm pitch perimeter array. The base package contains 1 flip chip die and a network of passive components which are attached to the package substrate between the edge of the flip chip die and the inner row of PoP interface lands.


Figure 1. Typical conductive via structure.
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Figure 1 shows a TMV in the base package prior to stacking the top package. The bump exhibits good wetting to the PoP interface lands, and bump height was controlled to within 3.5-µm standard deviation. Package flatness was controlled to less than 60 µm over a simulated reflow from RT to 260C°.

Package stacking was performed using an automated IC placement machine equipped with a flux or solder paste dipping module. After placement, the BGA balls of the top package rest inside the vias of the bottom package and make contact with the bumps in the vias. During initial trials 100% stacking yield was observed.


Figure 2.PoP solder joints after stacking.
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Gap height between the top package and bottom package can be tailored by adjusting the bump height in the via. Gap height of 10-15 µm has been demonstrated (Figure 2).

The TMV PoP structure has several advantages for next-generation applications. Tall solder joints can be formed at fine pitch with minimal risk of shorting, allowing for pitch reduction for higher interconnect density between the top and bottom packages. Alternatively, additional components such as passives or stacked die can be integrated in the base package with a thicker mold cap while maintaining a fine pitch PoP stacking interface. Gap height between packages can be reduced to a minimum value and can be tailored by adjusting the volume of solder in the mold cap via. Base package flatness is significantly improved over bare die flip chip PoP or straddle-mount wire bond PoP, improving assembly yield. The improved flatness will allow for thinner substrates to be used in the base package, reducing total thickness. For wire bond packages, standard array molding technology can be used rather than pin gate molding, which must be tooled for each package body size. The TMV structure allows PoP lands to be moved closer to the edge of the die compared to bare die flip chip or pin-gate molded wire bond structures. This will enable higher die size to package body size ratio. TMV technology promises to extend the capabilities of PoP stacking. The success of the PoP meet the challenges associated with next generation package stacking.


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CHRISTOPHER SCANLAN, V.P. corporate research & development, may be contacted at Amkor, 1900 South Price Rd., Chandler AZ 85248; 480/821-2408; E-mail: cscan@amkor.com.