Issue



The Thermal CPB An Approach to Thermal and Power Management


01/01/2008







BY PAUL A. MAGILL, Ph.D., Nextreme Thermal Solutions

In electronics, heat and power issues are gating progress; especially in high-end, flip chip devices. System level cooling is limited by power requirements. A novel approach integrating thermal material into solder bumps allows for spot cooling at chip level, and enables a system solution to do its job efficiently.

At the semiconductor chip, package, and system level, higher densities, more features, higher speeds, and miniaturization all contribute to heat and high power densities emanating from electronics.

It is a misconception that system-level cooling can solve these problems because the power required to achieve system-level cooling is a fundamental limitation to achieving the desired results.

A novel approach to electronic thermal management focuses on providing appropriate cooling when and where it is needed. Rather than displace system-level cooling, it introduces a way to achieve uniformity at the chip and board levels, so that a system solution can do its job more efficiently. Additionally, whereas system-level solutions scale with the system, this solution scales at the chip level.

The thermal copper pillar bump (CPB) solution involves the integration of a thin-film thermoelectric material into solder bumps for flip chip packaging. This enables active thermal management - and power generation - right at the chip’s surface using an industry-accepted manufacturing approach to ensure seamless implementation. Unlike conventional solder bumps, which provide an electrical path and a mechanical structure, each thermal CPB acts as a solid-state heat pump on a micro-scale.

Thermal bumps can be integrated as part of the standard flip chip process (Figure 1) and will be combined with electrical bumps (for power, ground, and signal). This technology offers new thermal functionality to electronics that can be integrated into a circuit design in the same manner as transistors, resistors, and capacitors.


Figure 1. Thermal and electrical bumps integrated on a single substrate.
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This technology extends the use of conventional solder bumped interconnects to provide active, integrated cooling of a flip chip component. It enables power generating capabilities within CPBs for energy recycling applications. Prior to this, solder bumps could only provide mechanical, electrical, and passive thermal functionality.

The thermally active CPB can achieve a 60˚C temperature difference across the 60-µm tall CPB when electrical current is run through it. Additionally, maximum power pumping capabilities exceed 150 W/cm2, and when subjected to heat, it can generate up to 10 mW of power.

Thermal CPB Structure

Figure 2 shows an SEM cross-section of a TE leg. The TE element is structurally identical to a CPB with an extra layer, the TE layer, incorporated into the stack-up. The addition of this TE layer transforms a standard CPB into an active thermoelectric CPB. This element, when properly configured electrically and thermally, provides active thermoelectric heat transfer from one side of the bump to the other.


Figure 2. Cross sectional view of a thermal CPB.
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The direction of heat transfer is dictated by the doping type of the thermoelectric material (either an n-type or p-type semiconductor) and the direction of electrical current through the material. This type of thermoelectric heat transfer is known as the Peltier effect. Conversely, if heat is allowed to pass from one side of the thermoelectric material to the other, a current will be generated in the material in a phenomenon known as the Seebeck effect. The Seebeck effect is the reverse of the Peltier effect. In this mode, electrical power is generated from the flow of heat in the TE element. The structure shown in Figure 2 is capable of operating in both the Peltier and Seebeck modes.


Figure 3. Schematic showing traditional CPB next to a P-type and N-type pillar bump.
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Figure 3 compares the structure of a typical CPB to that of a thin-film thermal CPB. These structures are similar, with both having copper pillars and solder connections. The primary distinction between the two is the introduction of either a P- or N-type thermoelectric layer between two solder layers. The solders used with CPBs and thermal CPBs can be any one of a number of commonly used solders including, but not limited to, SnPb eutectic, SnAg or AuSn.


Figure 4. Close-up schematic showing flow of heat through a thermal CPB. Also shown are the multi-layer metal traces often used in complex integrated circuits.
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Figure 4 shows an expanded view of a thermal CPB. Heat flow through the thermal CPB may be modified by the design of the metal traces on the chip. These traces, which can be several µm thick, and can be stacked or interdigitated, provide highly conductive pathways for collecting heat from the underlying circuit; and funnel that heat to the thermal CPB. The metal traces for conducting electrical current into the thermal CPB may or may not be directly connected to the circuitry of the chip. In either case, an on-board temperature sensor and driver circuitry control thermal CPB in a closed-loop for optimal performance. Second, the heat pumped by the thermal CPB and the additional heat created by it in the process, is rejected into the substrate or board.

Since thermal performance of the thermal CPB can be improved by providing a path for the rejected heat, it is beneficial to provide high thermally conductive pathways on its backside using a highly conductive substrate like AlN or a metal (e.g., Cu, CuW, CuMo, etc.) with a dielectric. In this case, the high thermal conductance of the substrate will act as a natural pathway for the rejected heat. The substrate might also be a multilayer substrate like a PWB designed to provide a high density interconnect. In this case, thermal conductivity of the PWB may be relatively poor and adding thermal vias (e.g. metal plugs) can provide excellent pathways for the rejected heat.

Applications

Because thermal CPBs are similar in structure, and use comparable processing techniques for traditional CPBs, they can be integrated into current CPB based processes. Thermal CPBs can be used in a number of different ways to provide chip cooling.

General cooling. Thermal CPBs can be distributed across the chip surface to provide an evenly distributed cooling effect. In this case, thermal CPBs may be interspersed with standard CPBs used for signal, power, and ground. This allows thermal CPBs to be placed directly under the active circuitry of the chip for maximum effectiveness. The number and density of thermal CPBs are based on the heat load from the chip. Each P/N couple provides a specific heat pumping (Q) at a specific temperature differential (ΔT) at a given electrical current. Temperature sensors on the chip (“on board” sensors) can provide direct measurement of the thermal CPB performance and provide feedback to the TEC driver circuit.

Precision temperature control. Since thermal CPBs can either cool or heat the chip depending on the current direction, they can be used to provide precision control of temperature for chips that must operate within specific temperature ranges irrespective of ambient conditions. This is a common problem for many optoelectronic components.

Hotspot cooling. In microprocessors, graphics processors, and other high-end chips, hotspots can occur as power densities vary significantly across a chip, severely limiting device performance. Because of the small size of the thermal CPBs and the relatively high density at which they can be placed on the active surface of the chip, these structures are ideally suited for cooling hotspots. In such a case, the distribution of the thermal CPBs may not need to be even. Rather, the thermal CPBs would be concentrated in the area of the hotspot while areas of lower heat density would have fewer thermal CPBs per unit area. In this way, cooling from the thermal CPBs is applied only where needed, thereby reducing the added power necessary to drive the cooling and reducing the general thermal overhead on the system.

Conclusion

The small size and easy integration methodology of this new technology opens the door to improving chip speeds while maintaining or improving system level energy consumption and efficiency.


Paul A. Magill, Ph.D. V.P. of marketing and business development, may be contacted at Nextreme Thermal Solutions 3040 Cornwallis Road, P.O. Box 13981, Research Triangle Park, NC 27709-3981; 919/597-7318; E-mail:pmagill@nextremethermal.com