Albany Nanotech opens 65nm line
Albany Nanotech put another notch in its belt when it qualified its 65nm semiconductor fabrication line in September. It is the first university to qualify a line of tools that matches the current state-of-the-art in the semiconductor industry.
The line is operated under the auspices of the Center for Semiconductor Research (CSR), an industrial partnership that includes participation from IBM, Advanced Micro Devices (AMD), Sony, Toshiba, Tokyo Electron and Applied Materials. The CSR is a long-term program to develop future chip technology beginning with the 32nm node. It is intended to provide full vertical integration of the design, modeling, fabrication, testing and pilot prototyping of devices.
“The line came up really well,” said James Ryan, professor of nanoscience and vice president of technology at Albany Nanotech. “It worked pretty much on the first shot.”
Ryan and others involved in the effort say the new line is a necessity in order for Albany Nanotech to take advantage of resources like an extreme ultraviolet (EUV) alpha demo tool it took delivery of from ASML this past summer. Moreover, they say, having a full product line is critical for both developing the new processes required and for providing feedback to the tool vendors.
“We intend to totally practice the craft of device integration,” said William Rozich, IBM’s director of 300mm operations. “Toolmaker participation becomes critical.” In short, having a full line lets tool innovation become part of the design process itself.
Ryan and Rozich said the effort was a case study in making industrial teams work. “People disagree, sure,” said Ryan, “but the guy who gets listened to in the meeting is the guy in the room who is smartest on that topic.”
Rozich said the effort constituted a unique blend of cultures that was a first for IBM in another way. “It was the first time for us doing this type of thing where we are not running the show,” he said.
Nevertheless, hiccups did occur. Working “pretty much on the first shot” actually meant the second: The first, said Ryan, was a mis-process.
And the teams encountered challenges they didn’t anticipate - such as how to collaborate in an open environment while still protecting corporate assets. That may sound easy, but it’s not necessarily so when you have to balance fab viewing corridors and camera phones, or open academic networks and corporate VPNs. New protocols had to be developed.
And procurement provided an almost comic stumbling block. “Let’s just say they weren’t used to ordering the quantities (of chemicals) that we need,” said Ryan of procurement staff who were more accustomed to ordering for classroom experiments than they were for a semiconductor fab.
Going forward, the group says the line will be both integrated and modular, supporting both industrial 32nm process development as well as academic projects like one Ryan is pursuing under a Navy contract to develop a new resistor material.
“It’s a unique model,” said Alain Kaloyeros, Albany Nanotech vice president and chief administrative officer, citing the close industry-academic collaboration. “It’s important to have partners willing to take short term risk in order to be strategic.”
- David Forman
IBM unveils MEMS-based chip cooling approach
IBM researchers presented an innovative MEMS-based approach for improving the cooling of computer chips at the Power and Cooling Summit in October. Big Blue says the technique, called “high thermal conductivity interface technology,” allows a twofold improvement in heat removal over current methods and could pave the way to reduce industry’s reliance on complex and costly systems to cool chips.
The approach addresses the connection point between the hot chip and the various cooling components used today to draw the heat away, including heat sinks. Special particle-filled viscous pastes are typically applied to this interface to guarantee that chips can expand and contract owing to the thermal cycling. This paste is kept as thin as possible in order to transport heat from the chip to the cooling components efficiently. Yet, squeezing these pastes too thin between the cooling components and chip would damage or even crack the chip using conventional techniques.
Instead, the researchers used MEMS processing techniques to develop a chip cap with a network of tree-like branched channels on its surface. The pattern is designed such that when pressure is applied, the paste spreads much more evenly and the pressure remains uniform across the chip, allowing the right uniformity to be obtained with nearly two times less pressure, and a ten times better heat transport through the interface.
The technique is one of several being explored by scientists at the IBM Zurich Research Laboratory to address cooling. The researchers are also developing a novel and promising approach for water-cooling. Called direct jet impingement, it squirts water onto the back of the chip and sucks it off again in a closed system using an array of up to 50,000 tiny nozzles and a tree-like branched return architecture.
By using a closed system, there is no fear of coolant getting into the electronics. In addition, the team was able to enhance the cooling capabilities of the system by devising ways to apply it directly to the back of the chip, thereby avoiding the resistive thermal interfaces between the cooling system and the silicon.
IMEC demos feasibility of double patterning immersion litho for 32nm node
IMEC, the Leuven, Belgium, independent research center for micro and nanotech, showed in collaboration with ASML the potential of double patterning 193nm immersion lithography at 1.2NA for 32nm node Flash and logic.
The organizations said that the results prove that double patterning might be an intermediate solution before extreme ultraviolet (EUV) lithography and very high NA (beyond water) 193nm immersion lithography will be ready for production.
The results were obtained by splitting gate levels of 32nm half pitch Flash cells as well as logic cells in two complementary designs. The splitting was done automatically using software from EDA partners in IMEC’s lithography program. After splitting, both designs received optical proximity corrections (OPC) and a classical lithography approach “litho-etch-litho-etch” was performed. Exposures of both lithography steps have been carried out on an XT:1700i at ASML.
IMEC and ASML say the results show that the XT:1700i 193nm immersion tool, which has a maximum NA of 1.2, could be extended beyond the 45nm node.
Nantero announces routine use of nanotubes in production CMOS fabs
Nantero Inc., a Woburn, Mass., company using carbon nanotubes for the development of next-generation semiconductor devices, announced it has resolved the major obstacles that had been preventing carbon nanotubes from being used in mass production in semiconductor fabs.
Nanotubes are widely acknowledged to hold great promise for the future of semiconductors, but most experts had predicted it would take a decade or two before they would become a viable material. This was due to several historic obstacles that prevented their use, including a previous inability to position them reliably across entire silicon wafers and contamination previously mixed with the nanotubes that made the nanotube material incompatible with semiconductor fabs.
Nantero said it has developed a method for positioning carbon nanotubes reliably on a large scale by treating them as a fabric which can be deposited using methods such as spincoating, and then patterned using lithography and etching. The company said it has been issued patents on all the steps in the process, as well as on the article of the carbon nanotube fabric itself, U.S. Patent No. 6,706,402, “Nanotube Films and Articles,” by the U.S. Patent and Trademark Office.
The patent relates to the article of a carbon nanotube film comprised of a conductive fabric of carbon nanotubes deposited on a surface. Nantero has also developed a method for purifying carbon nanotubes to the standards required for use in a production semiconductor fab, which means consistently containing less than 25 parts per billion of any metal contamination.