Intel 65-nm process leaves no room for tiniest particles
BY HANK HOGAN
SANTA CLARA, Calif.—Intel Corp.'s (www.intel.com) recent breakthrough achievement of fully functional 70-Mbit static random access memory (SRAM) chips on a 65-nanometer (nm) manufacturing process makes the contamination control playing surface smaller and more critical than ever.
The technology gives Intel a foundation on which to deliver next-generation multi-core processors, and to design such features as virtualization and security into products of the future.
But while Intel hasn't revealed many details of its latest manufacturing technology, it has released enough information to highlight several contamination-control challenges. For example, the new process has a smaller feature size than any previous volume production technology, making it vulnerable to even smaller particles. Additionally, the 65-nm process incorporates another metal layer (with eight layers of metal interconnect stacked on top of each other), an enhanced version of Intel's strained silicon transistors, an improved low dielectric between metal interconnect layers, and different photolithographic techniques—all of which have an impact on contamination control within Intel's cleanrooms.
The technology's advances also have an effect on the manufacturing infrastructure, ranging from mask making to process tools and supplies. "As we keep going to advanced nodes, instead of maybe one material change on one layer, we're compounding a lot more," explains Patricia Gabella, president of Gabella Management Group (Austin, Texas), which consults on advanced photolithographic mask making as well as other cleanroom areas. "The industry has a lot more challenges at one time than it did in the past."
Dealing with mask defects
For its 65-nm process, Intel is making greater use of 193-nm phase shift masks. The masks exploit optical techniques to create a change in phase of the light that passes through the masks. As a result, adjacent structures interfere with each other and lead to finer photoresist features. Because they are used repeatedly, masks must be defect-free. So, part of the photomask manufacturing process involves repair. For a phase shift mask, such as what is required in the 65-nm process, achieving perfection becomes more challenging.
"They're simply more difficult to fix because you have to pay more attention to the phase," Gabella says of the phase shift mask. Problems can arise, Gabella notes, because the repair itself can cause a phase shift.
Then there's the contamination-control issue with the increased use of 193-nm photolithographic tools: The wavelength of the light source (193-nm) is shorter than that of the previous industry standard of 248 nm. A shorter wavelength allows smaller features to be imaged, but like phase shifting, doesn't come without cost.
"The 193-nm wavelength has a higher photon energy, which can trigger contamination growth on masks from process residues or airborne contamination in the fab environment," notes Craig West, director of applications at DuPont Photomasks (Austin, Texas; www.photomask.com). West notes, however, "The industry is working on a number of improvements, including significant reduction in mask process residuals as well as more careful environmental control."
Another contamination-control and infrastructure challenge in the 65-nm process is the use of an enhanced version of strained silicon—or, silicon that is under stress. With strained silicon, manufacturers can create transistors that transport charge more quickly, which translates into faster transistors and better circuit performance.
"At the 90-nm generation, strained silicon improved average performance by about 20 percent. This generation silicon is improving average transistor performance by about 30 percent," says Mark Bohr, Intel's director of process architecture and integration.
Through process innovations, Intel has produced p- and n-type transistors with strain in only one direction. For the n-type, the transistors are capped with an appropriate film. For the p-type, the technique involves the selective deposition of a silicon germanium layer in the active regions of the device.
Intel won't go into the details of exactly how it achieved mass production of the second generation of strained silicon, the first generation of which some companies are still struggling with. But one thing needed for strained silicon is "the presence of the germanium atom," says Bryan Lord, vice president of corporate development at the strained silicon intellectual property company AmberWave Systems Corp. (Salem, N.H.; www.amberwave.com). "That is what changes the lattice structure of the material in the first place."
New gas purity issues
According to Conrad Sorenson, program development manager at Praxair Inc.'s (Danbury, Conn.; www.praxair.com) electronics research and development group, the silicon germanium film is where the contamination control and infrastructure problems arise. With the incorporation of a film of silicon germanium into a standard CMOS process, those purity standards have to be even more stringent.
"Germanium is very sensitive to oxygen," says Sorenson, "because germanium oxide is not stable—it's volatile. So, if you have any present, it's going to create problems inside the film."
As a result, the allowable level of oxygen present in such gases as nitrogen may have to be lowered. Such tightened criteria have contamination-control implications for both gas suppliers and facilities. Suppliers must provide higher purity gas, and facilities need to ensure that the gas purity level isn't compromised.
Even in the face of these and other contamination-control issues, Intel has produced SRAM chips with more than a half-billion transistors on a 65-nm process in its 300-mm wafer fab in Hillsboro, Ore. While the early yield is unknown, Intel says it has a strategy to replicate the process at facilities in Arizona and Ireland. Predicts Bohr, "We'll be processing functioning microprocessor chips on this technology in 2005."