Limits loom for low-k semiconductor materials


New contaminatin control processes on the horizon?


AUSTIN, Texas-Citing consensus from an interconnection symposium, semiconductor research consortium Sematech ( says the industry believes that low-k materials-those with a low dielectric constant-are reaching a practical limit. The likelihood of hitting the wall has the industry scrambling for other solutions, and with them the real possibility of more stringent contamination control requirements in the manufacturing process.

Andreas Knorr, program manager for Sematech’s advanced interconnect materials group, who chaired last year’s symposium, recalls that while opinion was divided on how low low-k can go, no one doubted the looming limits. “Everybody sees that they are there, and the limits are not going to be the theoretical limits but other factors,” says Knorr.

The problem is that semiconductor device performance is fundamentally determined by resistance and capacitance. As features shrink,

resistance goes up for a variety of reasons. That increase can be countered by decreasing capacitance, which is related to the dielectric constant. So, the semiconductor industry has been pushing low-k down-from around 2.7 at the 65-nanometer (nm) process node to a projected 2.4 at the 45-nm node, and on to perhaps 2.2 or 2.0 at 32 nm.

The dielectric constant can’t go below 1.0, but industry experts aren’t even sure that it’s possible to economically hit the 2.4 constant for the 45-nm requirements. The low-k materials being touted for that node are difficult to work with, which will mean added complexity and cost.

One solution may be to use supercritical carbon dioxide, or SCCO2. Formed at temperatures above 31°C (88°F) and pressures above 1,100 pounds per square inch-or, about 75 atmospheres-SCCO2 is environmentally benign and has some unique properties.

“It doesn’t have any surface tension, so going into pores is pretty easy for it,” explains Rick Reidy, associate professor of materials science and engineering at the University of North Texas, Denton. “It’s like a gas in that way. On the other hand, it is highly dense, approaching that-depending on pressure-of a liquid.”

This combination allows SCCO2 to act as a clean agent, and it also can repair processing damage to low-k materials. But using SCCO2 requires moving high-pressure gas around, and recirculating it means removing the contaminants picked up by the gas during a clean. The tools can weigh a half ton or more, which may require beefing up cleanroom subflooring.

Tessera Technologies' Chip Stack technology is designed to offer greater flexibility for stacking various chip technologies into small, high-performance functional blocks. The process leverages standard wire-bonding and works with bonding pads measuring 30 ??m or more across.

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Another proposed solution is 3D manufacturing, which some believe could be the ultimate answer because this approach entirely sidesteps several interconnect problems.

Tessera Technologies, Inc. (San Jose, Calif.; licenses a relatively simple version of 3D technology in its Chip Stack packaging (See Fig. 1). Craig Mitchell, Tessera’s vice president of marketing, says the company’s processes leverage standard wire-bonding and work with bonding pads measuring 30 µm or more across. “All of the processes used in developing these packages are performed within a cleanroom environment typically on the order of class 1,000 to class 10,000.”

Industry experts envision 3D manufacturing one day moving from the packaging area into a wafer fab. That would mean shrinking the bonding pads down and imposing more stringent contamination control.

Sematech’s associate director for interconnects, Kenneth Monnig, predicts, “It’s going to be between the extremes of what you would do now for conventional bonding and wafer processing.” III