Modern materials present new contamination problems in semiconductor processes


By Hank Hogan

In the good old days-say, five years ago-shrinking semiconductor features meant contamination challenges due to eliminating smaller particles. However, as new materials are introduced at a rapid rate, that’s no longer the case. A look at lithography and back-end processing shows why this isn’t your father’s-or even your older brother’s-fabrication process and what that means for contamination control.

Larry Thompson, president of the consulting firm IPSSLP (Austin, TX), notes that the lithography critical dimension (CD) budget, like killer particles, tracks feature size. “Because that CD budget is shrinking, you have to have better and better control over the airborne contamination,” he says.

New materials, though, are now having an impact. Immersion lithography substitutes water for air between the last lens and the wafer, allowing finer imaging. However, contaminants in or under the resist can be struck by an intense laser, which could result in a bubble that scatters light and deposits volatiles nearby. Because of this, notes Thompson, companies are contemplating making the last lens a flat, replaceable element.

Now just being deployed, immersion lithography will someday play out. Extreme ultraviolet (EUV) lithography is a contender for the next imaging technology. EUV photons are about 13 nanometers wavelength, almost 15 times shorter than today’s state-of-the-art 193 nm. Producing those short wavelengths leads to a lot of particles, mainly in the tool itself.

An alternative involves imprinting, a technique in which a template with the desired features stamps out resist patterns. It allows very high resolution-if the mold is built correctly. Achieving that requires controlling contaminants, which is a significant challenge since the template is an exact reproduction and not a shrink as is the case currently. Contamination, “both airborne and in the material itself, [is] far more critical in imprint than in a 4X reduction,” says Thompson.

In back-end processing, new materials already can cause contamination. In an effort to boost circuit performance, manufacturers are turning to high-stress nitrides and oxides, along with low capacitance, or low-k, materials that are brittle and don’t adhere well.

Film stress is a problem, notes Chris Long, a senior engineer with IBM (Essex Junction, VT). “You take them through subsequent processing and at high-stress points...the film [starts] cracking and then popping off,” he says.

The problem occurs on wafers and tools. Exposed to varying humidity when the tool is opened for preventive maintenance, the film can form small airborne flakes. These can land on other tools, load ports, or elsewhere. Reducing airflow in a fab to save energy and money exacerbates the issue.

Ensuring that multiple tools spaced closely together aren’t opened at the same time can minimize the problem. Another solution might be to change tool cleaning procedures. Adding humidity control would also help, as would temporarily turning up area airflow.

Other new materials present their own contamination problems. Atomic layer deposition of a film, for example, offers great step coverage down microscopic trenches. However, it can also result in a nonuniform film on the back of a wafer, increasing potential backside contamination.

One solution is increased backside cleaning and inspection. A trend is for wafers to be divided into various cleanliness zones, including front and back.

Finally, Long notes the contamination impact will grow as feature sizes shrink below the current 65 nanometer state-of-the-art, requiring diligence in attacking such problems. “We may see issues if we don’t keep those [problems] on the radar screen and try to fix them ahead of time,” he says.