Surface preparation prior to deposition


Integrated circuit design is constantly being scaled down in pursuit of faster circuit operation and lower power consumption. Scaled dimensions in a circuit design generally require attendant changes in fabrication processing.

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Theoretically, incorporating materials of higher dielectric constant into the gate dielectric opens the door to further device scaling. Due to higher dielectric constant, many materials can exhibit the same capacitance as a thinner silicon dioxide layer, such that a lower equivalent oxide thickness can be achieved without tunnel-limited behavior.

It is often difficult to deposit electrode materials, such as polysilicon, amorphous silicon, and particularly doped silicon or silicon germanium alloys, over conventional silicon oxides as well as many of the high k materials currently under investigation. Many other types of materials and deposition techniques in integrated circuit fabrication face issues that depend upon the substrate surface upon which the material is to be deposited.

Intermediate layers are often deposited prior to deposition of the desired functional layer for a variety of remedial reasons, including otherwise poor adhesion, nucleation, electrical interface properties, diffusion, etc. Such intermediate layers add to the complexity and cost of fabrication, and can also occupy valuable space within high aspect ratio features. In some contexts, additional layers increase the overall dielectric thickness and reduce the effectiveness of the layer, contrary to the trend for scaling down integrated circuits.

Accordingly, a need exists for improving the speed, efficiency, quality and uniformity of depositing layers in semiconductor fabrication. The methods described here are for treating substrate surfaces in preparation for subsequent deposition. In particular, the methods are provided for preceding nucleation sensitive depositions (e.g., polysilicon or poly-SiGe) and adsorption-driven deposition (e.g., atomic layer deposition or ALD).

The present invention provides a method for preparing the dielectric surface for electrode deposition without significant deposition and preferably without significant modification of bulk properties of the dielectric. Prior to depositing, the preferred embodiments treat the surface with plasma products. The surface treatment provides surface moieties more readily susceptible to a subsequent deposition reaction, or more readily susceptible to further surface treatment prior to deposition. By changing the surface termination of the substrate with a low temperature radical treatment, subsequent deposition is facilitated without depositing a layer of any appreciable thickness and without significantly affecting the bulk properties of the underlying material.

Exemplary plasma product treatment includes provision of F, Cl, H or N radicals, particularly through a remote plasma module attached to a deposition chamber for in situ surface treatment prior to deposition.

The figure shows a schematic sectional view of an exemplary single-substrate reaction chamber. The single-pass horizontal flow design enables laminar flow of reactant gases, with low residence times, which in turn facilitates sequential processing while minimizing reactant interaction with each other and with chamber surfaces. Thus, among other advantages, such a laminar flow enables sequentially flowing reactants that might react with each other. The illustration shows a CVD reactor (A), including a quartz process or reaction chamber (B).

A plurality of radiant heat sources are supported outside the chamber to provide heat energy in the chamber without appreciable absorption by the quartz chamber walls. The illustrated radiant heat sources comprise an upper heating assembly of elongated tube-type radiant heating elements (C). A lower heating assembly comprises similar elongated tube-type radiant heating elements (D) below the reaction chamber, preferably oriented transverse to the upper heating elements. Desirably, a portion of the radiant heat is diffusely reflected into the chamber by rough specular reflector plates (not shown) above and below the upper and lower lamps, respectively. Additionally, a plurality of spot lamps (E) supply concentrated heat to the underside of the substrate support structure to counteract a heat sink effect created by cold support structures extending through the bottom of the reaction chamber.

A substrate, preferably comprising a silicon wafer (F), is shown supported within the reaction chamber upon a substrate support structure (G). The illustrated support structure includes a substrate holder (H), upon which the wafer rests, and a support spider (I) that is mounted to a shaft (J), which extends downward through a tube depending from the chamber lower wall. Preferably, the tube communicates with a source of purge or sweep gas that can flow during processing, inhibiting process gases from escaping to the lower section of the chamber.

A plurality of temperature sensors, which may take a variety of forms, are positioned in proximity to the wafer. In the illustration, the temperature sensors comprise thermocouples, including a first or central thermocouple (K), suspended below the wafer holder. The central thermocouple passes through the spider in proximity to the wafer holder. The reactor further includes a plurality of secondary or peripheral thermocouples, including a leading edge or front thermocouple (L), a trailing edge or rear thermocouple (M), and one or more side thermocouples (not shown). Each of the peripheral thermocouples is housed within a slip ring, which surrounds the substrate holder and the wafer. Each of the central and peripheral thermocouples is connected to a PID temperature controller, which sets the power of the various heating elements in response to the readings of the thermocouples.

The illustrated reaction chamber includes an inlet port (N) for the injection of reactant and carrier gases, and through which the wafer can be received. An outlet port (O) is on the opposite side of the chamber.

An inlet component (P) is fitted to the reaction chamber, adapted to surround the inlet port, and includes a horizontally elongated slot (Q) through which the wafer can be inserted. A generally vertical inlet (R) receives gases from remote sources and communicates such gases with the slot and the inlet port.

An outlet component (S) similarly mounts to the process chamber such that an exhaust opening (T) aligns with the outlet port and leads to exhaust conduits (U). The conduits, in turn, can communicate with suitable vacuum means (not shown) for drawing process gases through the chamber and through the reaction chamber and a downstream scrubber (not shown).

The preferred reactor also includes a source (V) of excited species, preferably positioned upstream from the chamber. The excited species source comprises a remote plasma generator, including a magnetron power generator and an applicator along a gas line (W). A source of precursor gases (X) is coupled to the gas line for introduction into the excited species generator. A source of carrier gas (Y) is also coupled to the gas line.

In other arrangements, the excited species can be generated within the process chamber. For example, in situ plasmas can be generated by applying radio frequency (RF) power to spaced electrodes within the process chamber. Furthermore, energy can be coupled to source gases by a number of means for either in situ or remote plasma generation. Preferably, however, a remote plasma source is employed for the processes described herein, affording greater control for surface modification with minimal bulk effects.

Patent number: 7,056,835

Date: June 6, 2006

Inventors: Christophe F. Pomarede (Phoenix, Ariz.); Jeff Roberts (Chandler, Ariz.); Eric J. Shero (Phoenix, Ariz.)