Inside ASET's Dream Chip
The International Symposium on Electronic Packaging was held in Osaka the week of April 10th with keynote speakers, Dr. Subramanian S. Iyer of IBM, Dr. Takeshi Uenoyama of Panasonic, and Dr. Urmi Ray of Qualcomm.
There were 180 papers and over 20 posters. In addition, the Japan ASET consortium, Taiwan and Korea held special sessions.
The ASET "Dream Chip" program recently ended in Japan. In the ASET special session, Sueoka and co-workers described their proposal for "High Precision Bonding for Fine Pitch Interconnection." Bonding fine pitch interconnect requires consideration of the factors which degrade the alignment accuracy such as thermal expansion of the machinery, and surface topologies of the chip an substrate.
They were able to bond 10??m pitch bumps. Using a flip chip bonder equipped with infrared alignment optics they found that they could observe alignment marks and adjust the chip position during the bonding process, even when the solder was molten. Most importantly they could eliminate the mis-alignment caused by joining non flat chips and due to thermal expansion of the tool head.
This dynamic alignment bonding scheme consists of 4 steps:
??? pre-align for the approach of the chip to the substrate
??? small gap align with IR light
??? correct alignment for offsets caused by impact of the chip touching the substrate
??? final align during the bonding while the solder is molten.
Renesas and IBM Japan described "3D Package Assembly Development with the use of Dicing Tape Having NCF Layer". Dicing and stacking are important technologies in 3DIC assembly. Bumps on the wafer backside make it difficult for general dicing tape to achieve both high quality dicing and pickup. For tight pitch, small bump bonding it is also difficult to inject underfill into the narrow gap between the dies.
General dicing tape cannot bury the bumps and thus fully fix the die. This causes chipping and cracking of the die during dicing. If you increase the tapes thickness to fully bury the bumps, die pickup becomes difficult.
ASET studied a new ICF tape from Nitto Denko. The tape has a NCF layer (non-conductive film) on the dicing tape. Since this NCF layer ends up staying in the gap as underfill, they call this Inner chip film or ICF (just what we need more acronyms!) Hot lamination of the tape to the wafer will bury the backside bump. Wafer and NCF layer are diced together. The die pick up becomes easy since the required separation is between the ICF and the dicing tape adhesive.
Hozawa and ASET co-workers at ASET described their "3D Integration Technology using Hybrid Wafer Bonding and its Electrical Characteristics". In this study ASET examined 3D integration with vias last. Vias last was examined because it needs no modification of the front end process.
The process flow consists of: TSV formation; bump/contact ad formation; substrate thinning and stacking. They also examined W2W bonding and thinning after bonding as process flows.
Hybrid bonding was chosen where Cu-Cu and polymer ??? polymer bonding (they used PBO) occur at the same interface. Hybrid bonding provides both strong metal bonding and reliable polymer underfilling simultaneously.
In the full process sequence a silicon interposer wafer and the first device wafer are bonded F2F with hybrid bonding. After backside thinning the first device wafer, TSV formation and backside bumping the second device wafer is bonded to the stack B2F. Lastly the silicon interposer is thinned, TSV formed and bumps attached.