Issue



Detection and elimination of a yield-critical non-visual residue defect


06/03/2013







Soonhaeng Lee, Wiseok Kang and Hobong Shin, Samsung Electronics, Gyeonggi-Do, Korea; Sungjin Cho, Jaeyoung You and Jeff Hawthorne, Qcept Technologies, Fremont, CA.


A post-wet clean residue that was causing a yield issue was found and eliminated.


Integrated circuit manufacturers rely heavily on optical inspection techniques to monitor and control manufacturing processes. Optical inspection has proven effective in detecting and classifying a wide range of physical defects on semiconductor wafers, such as pits, particles and scratches. In recent years, circuit features have continued to shrink while semiconductor manufacturers have been introducing many new materials, processes and structures for advanced technologies, such as high-k metal gates, low-k dielectrics and stressed silicon channels. The accelerating pace of change has introduced new types of yield-limiting defects, some of which are not detectable using optical inspection techniques. These defects are sometimes referred to as Non Visual Defects (NVDs), and include sub-monolayer residues, surface contamination and process-induced charging of dielectric films [1-4].


Samsung Electronics and Qcept Technologies previously presented a case study where a charge-based NVD was identified as a precursor to a physical "pitting" defect in the gate oxide process [5]. In this article we describe the detection and elimination of a post-wet clean residue on a logic device. The residue defect correlated to a known yield issue from end-of-line (EOL) electrical test. The failed die were clustered in a semicircular arc across the top of the wafer. The defect was believed to occur at the front end of line (FEOL) gate module, but no matching defect pattern was detected by the existing optical inspection tools. The residue defect was ultimately determined to be an NVD as detected by a unique, non-optical inspection technique.





FIGURE 1. Images (a) and (b) are sample EOL failure maps that show a common pattern of failed (pink) die across the top of the wafer. Image (c) is a brightfield optical inspection defect map at After Clean Inspect (ACI). Optical inspection provided no indication of the defect causing the yield loss.
FIGURE 1. Images (a) and (b) are sample EOL failure maps that show a common pattern of failed (pink) die across the top of the wafer. Image (c) is a brightfield optical inspection defect map at After Clean Inspect (ACI). Optical inspection provided no indication of the defect causing the yield loss.

The problem was initially noticed when a leading-edge-node logic device was experiencing increased yield loss at EOL electrical test. A large number of die on random wafers from random lots were failing for low grounded voltage of the collector (Vcc). The failures occurred in an arc pattern across the top of the wafer (FIGURE 1), and the failure mode suggested that the defect was happening somewhere in the gate and spacer module. A review of the existing brightfield optical wafer inspection data from the gate and spacer module did not identify a physical defect pattern that matched the yield-loss signature. In an effort to detect and diagnose the problem, inspection was initiated at several process steps within the gate and spacer module using a unique, non-optical inspection technology that is sensitive to a wide range of NVDs, including sub-monolayer contamination and process induced charge.


The inspection system used was the ChemetriQ system from Qcept Technologies. ChemetriQ is a scanning probe system that produces a full wafer image showing changes in the work function of the wafer. The resulting differential data can be numerically integrated and thresholded to detect regions of the wafer with relatively high or low work function. Changes in work function can result from a variety of surface conditions, including changes in surface chemistry, such as residues or contamination. This technique is sensitive to low-level, sub-monolayer contamination that does not scatter light and cannot be detected using traditional optical means.


ChemetriQ inspection was initiated at several process steps in the gate and spacer module, including post gate photo, post gate etch / clean, post spacer deposition, and post spacer etch / ash / clean. These types of partition studies are facilitated by the fact that the ChemetriQ system can scan wafers at many different process steps without modifying the scan recipe, so no time is spent optimizing recipes for each process step. NVD inspection data detected strong spots of increased work function (+WF) at the top portion of the wafer after the spacer etch, ash, and clean steps. The NVDs detected at the spacer process were thresholded into Defect Maps as shown in FIGURE 2. The number and spatial location of the NVDs correlated with failed die at EOL and closely matched the top of wafer yield-loss pattern.





FIGURE 2. The image on the left is a ChemetriQ image showing a residue pattern across the top of the wafer after spacer deposition, etch, ash and clean (red arrows). Areas of increased work function (+WF) appear bright in the image. The image on the right is a defect map created by thresholding the integrated image. The pattern of defects across the top of the wafer closely matched the pattern of EOL yield loss.
FIGURE 2. The image on the left is a ChemetriQ image showing a residue pattern across the top of the wafer after spacer deposition, etch, ash and clean (red arrows). Areas of increased work function (+WF) appear bright in the image. The image on the right is a defect map created by thresholding the integrated image. The pattern of defects across the top of the wafer closely matched the pattern of EOL yield loss.

The partition study provided strong evidence that the defect occurred at spacer etch and clean. The batch wet clean process was targeted as the most likely source of the NVD defect. During the clean process, the wafers were extracted from the batch tool notch-edge up, so the rinse water flowed from the notch (bottom) to top of the wafer as shown in FIGURE 3. It was suspected that this process might result in less effective rinsing on the top of the wafer.





FIGURE 3. Diagram of the batch tool used to clean wafers after spacer etch. The wafers were extracted from the bath with the notch up so the rinse water flowed from the bottom (notch side) of the wafer to the top.
FIGURE 3. Diagram of the batch tool used to clean wafers after spacer etch. The wafers were extracted from the bath with the notch up so the rinse water flowed from the bottom (notch side) of the wafer to the top.

An experiment was designed to determine if the defect could be caused by the flow of liquid as the wafers were extracted from the batch wet clean tool. Wafers were loaded in the tool with the notch at 90 degrees. The ChemetriQ images after clean showed that the +WF NVD pattern was rotated by 90 degrees. EOL electrical tests showed that the pattern of failed die was also rotated by 90 degrees (FIGURE 4). These results provided convincing evidence that the batch clean tool rinse was leaving a residue on the wafer surface that was causing the yield loss.





FIGURE 4. Sample results from an experiment with wafers rotated 90 degrees in the batch clean tool. Rotating the wafers also rotated the NVD pattern detected by the ChemetriQ inspection system and the pattern of yield loss at EOL test.
FIGURE 4. Sample results from an experiment with wafers rotated 90 degrees in the batch clean tool. Rotating the wafers also rotated the NVD pattern detected by the ChemetriQ inspection system and the pattern of yield loss at EOL test.

Different options were evaluated to eliminate the NVD from the batch wet clean process, including modifying the existing process and switching to a single-wafer clean process. One promising option was to use a new linear, single-wafer clean process for a more robust cleaning process and to eliminate the NVDs. ChemetriQ inspection results on wafers processed with the new linear, single-wafer clean process showed a cleaner and more uniform surface. EOL data also exhibited a significant increase in yield and elimination of the characteristic yield-loss pattern as shown in FIGURE 5.





FIGURE 5. Sample inspection and test results for a wafer cleaned with a linear single-wafer clean process. The pattern of positive work function defects was eliminated from the ChemetriQ inspection image and defect map, and EOL yield was increased significantly.
FIGURE 5. Sample inspection and test results for a wafer cleaned with a linear single-wafer clean process. The pattern of positive work function defects was eliminated from the ChemetriQ inspection image and defect map, and EOL yield was increased significantly.

As a result of this work, a linear, single-wafer clean approach was implemented after spacer etch, and the ChemetriQ tool was used to monitor production wafers to insure that the problem did not recur. In addition, Samsung engineers performed parametric tests and device modeling, which confirmed that a negative ionic contaminant was consistent with both the shift in electrical parameters for failed devices and the increase in work function detected by the ChemetriQ system.


Summary


In this paper we have presented the detection and elimination of a yield-critical residue at the FEOL gate and spacer module. The contamination responsible for the yield loss is an example of an NVD, which could not be detected using optical inspection. In this case the residue was detected using a scanning probe technique that detects changes in surface work function, which can be induced by chemical contamination or charging of dielectric films. Surface work function inspection results were used to identify and modify the clean process responsible for the defect. As a result, the defect was eliminated and yield was increased. The inspection system was subsequently used to monitor the process to insure that the defect did not recur.


References


1. J. Park, et al; SEMATECH Surface Preparation and Cleans Conference; Impact of Charge at Gate Oxide Patterning on Yield for an Advanced Technology Node, (2012).


2. J. Hallady, et al; SEMATECH Surface Preparation and Cleans Conference; Elimination of ESD Defects Using DICO2, (2008).


3. K. H??ppner, et al; Advanced Semiconductor Manufacturing Conference; Novel In-Line Inspection Method for Non-Visual Defects and Charging, (2009)


4. J. Hawthorne, et al; MICRO; Inspection Wafers Using a Potential Difference Imaging Sensor Method, (2005).


5. J. Park, et al; Solid State Technology; Impact of Charge During Gate Oxide Patterning on Yield, (July 2012).


SOONHAENG LEE is senior engineer of defect analysis group at Samsung Electronics Co., LTD, Yongin, Gyeonggi-Do, Korea. WISEOK KANG is senior engineer of defect analysis group and HOBONG SHIN is principal engineer of yield enhancement team at Samsung. SUNGJIN CHO is senior application manager at Qcept Technologies, 47354 Fremont Blvd, Fremont, CA. Tel: 510-933-1131, email: jason.cho@qceptech.com. JAEYOUNG YOU is senior application engineer at Qcept Technologies Korea, Hwasung, Gyeonggi-Do, Korea. JEFF HAWTHORNE is vice president of applications engineering at Qcept Technologies.



Solid State Technology | Volume 56 | Issue 4 | June 2013