New materials and processes for advanced interconnects
Although on-chip interconnects have not been scaling at the same speed as other parts of the chip, new capabilities enabled by graphene and CNTs, among other materials, could soon change that.
By Pete Singer
Transistor speed used to be the limiting factor for chip performance, but increasingly on-chip or Back End of Line (BEOL) interconnects have become a limiting factor. While transistors and other aspects of ICs have been continually made smaller, inter- connect scaling essentially stopped at the 20nm node. In part, this decision was made to save costs (i.e., reuse masks and avoid more complex lithog- raphy steps). There was also concern about imple- menting too many major changes at the same time. “When you have ten layers of metal and let’s say six layers of those are close to minimum pitch, it gets very expensive once you start doing double patterning,” said Dr. Deepak Chandra Sekar, general co-chair of the upcoming 2014 IITC/AMC joint conference. “With the interconnect layers, people want to save litho costs. That’s one reason they are not scaling as much as they used to.”
The major reason is that it’s difficult to make interconnects much smaller without introducing significant increases in resistivity. “If you scale down and your resistivity goes up exponentially, it can be a problem,” Sekar said. “Copper resistivity shoots up when you scale it down because of surface scattering, grain boundary scattering and interface roughness.” It’s well known that the electrical resistance (R) of the wires, or lines, increases as they are made thinner. It also arises because capacitive coupling (C) can occur among adjacent lines spaced very closely together. Speedor frequency is directly related to the inverse of the RC time constant (fc = 1/2πRC).
[caption id="attachment_59992" align="alignnone" width="507"] FIGURE 1. Work at IBM and Applied Materials showed a 10x improvement in electromigration lifetimes with multi-layer SiN and selective cobalt cap layers. 1000x improvement in electromigration lifetimes with multi- layer SiN cap, cobalt cap and wrap-around cobalt liners.[/caption]
Two upcoming conferences are worthy of special note: IITC/AMC and IRPS. The 17th annual Inter- national Interconnect Technology Conference (IITC) will be held May 21 – 23, 2014 in conjunction with the 31st Advanced Metallization Conference (AMC) at the Doubletree Hotel in San Jose, California (http://www.ieee.org/conference/ iitc). It will be preceded by a day-long workshop on “Manufacturing of Interconnect Technologies: schemes are shown to provide a 1000x improvement in electromigration lifetimes. The paper is titled “Advanced Metal and Dielectric Barrier Cap Films for Cu Low k Interconnects.”
Graphene and CNTs
Further out, it appears is if graphene hold tremendous promise as a possible replacement for copper. In work reported earlier this year by Georgia Institute of Technology, it was shown that electrical resistance in nanoribbons of epitaxial graphene changes in discrete steps following quantum mechanical principles (FIGURE 2). The research shows that the graphene nanoribbons act more like optical waveguides or quantum dots, allowing electrons to flow smoothly along the edges of the material. In ordinary conductors such as copper, resistance increases in proportion to the length as electrons.
[caption id="attachment_59993" align="alignnone" width="600"] FIGURE 2. Conceptual drawing of an electronic circuit comprised
of interconnected graphene nanoribbons (black atoms) that are epitaxially grown on steps etched in silicon carbide (yellow atoms). Electrons (blue) travel ballistically along the ribbon and then from one ribbon to the next via the metal contacts. Electron flow is modulated by electrostatic gates. (Courtesy of John Hankinson, Georgia Tech).[/caption]
Where are we now and where do we go from here?” on Tuesday, May 20. The International Reliability Physics Symposium (IRPS) will be held June 1-5 at the Hilton Waikoloa Village, Waikoloa, Hawaii (http://www.irps.org).
Reliability is important because it’s another challenge to scaling of interconnects. Both time- dependent-dielectric-breakdown (TDDB) and electromigration lifetimes for interconnects drop rapidly when scaled.
At both IITC/AMC and IRPS, a variety of papers will be presented that look at new materials that could enable continued scaling of conventional interconnects, while also addressing reliability challenges. These range from tweaks to existing processes to radically new strategies that could provide a viable alternative to copper/low-k.
At IITC/AMC, for example, IBM and Applied Materials will present a multi-layer SiN cap process is developed that shows higher breakdown and lower leakage compared to conventional SiCNH caps (FIGURE 1). Selective cobalt caps in combination with the multi-layer SiN cap are shown to provide a 10x improvement in electromigration lifetimes. Wrap-around cobalt liners in combination with the cap layer encounter more and more impurities while moving through the conductor.
The ballistic transport properties, similar to those observed in cylindrical carbon nanotubes, exceed theoretical conductance predictions for graphene by a factor of 10. The properties were measured in graphene nanoribbons approximately 40nm wide that had been grown on the edges of three-dimensional structures etched into silicon carbide wafers. “This work shows that we can control graphene electrons in very different ways because the properties are really exceptional,” said Walt de Heer, a Regent’s professor in the School of Physics at the Georgia Institute of Technology. “This could result in a new class of coherent electronic devices based on room temperature ballistic transport in graphene. Such devices would be very different from what we make today in silicon.”
Sekar also highlighted a number of papers that will be presented this year that focus on new materials that could lead to reduced resistivity and enable further interconnect scaling. “There is a lot of excitement about carbon and carbon- copper composites eventually replacing copper,” he said. “At IITC this year, we have a couple of papers, one on graphene showing lower resistivity than copper, and then one on carbon nanotubes showing good resistivity as well. They are
still a bit far out in the sense that there’s a lot more process integration work that needs to be done because these are proof of concept demos, but they show that there might be more beyond copper.”
In a paper from AIST, titled “Sub 10nm wide intercalated multi-layer graphene interconnects with low resistivity,” work will be presented that demonstrates 8nm wide 6.4nm thick graphene intercon- nects with a resistivity of 3.2uohm-cm (FIGURE 3), which is significantly better than copper with similar dimensions. This milestone for graphene inter- connect research is expected to motivate the process integration research that is required to take the technology to the next level.
[caption id="attachment_59998" align="alignnone" width="357"] FIGURE 3. Work 8nm wide graphene interconnects.[/caption]
Carbon nanotubes (CNTs) have been explored as a material for vertical inter- connects for many years since they can handle higher current densities than copper and offer ballistic transport. A paper from imec titled “Electron Mean Free Path for CNT in Vertical Intercon- nects Approaches Copper,” work will be presented that demonstrates a 5x improvement in electron mean free path for CNTs compared to previous work (FIGURE 4). The CNT mean free path of 24-74nm approaches copper. Contact resistance is improved significantly compared to previous work as well.
[caption id="attachment_59994" align="alignnone" width="230"] FIGURE 4. Carbon Nanotube (CNT) vias in integrated structures.[/caption]
Of course, an alternative to making everything smaller by scaling is to go 3D. That will be addressed by a variety of papers, including one from CEA-Leti focused on 3D monolithic integration. While most of today’s through-silicon vias (TSVs) are in the 5μm range, monolithic 3D technologies offer TSVs in the 50nm range, which allows dense connectivity between different layers in a 3D-IC. In the Leti paper, such dense connectivity is shown to provide 55% area reduction and 47% energy-delay product improvement for a 14nm FPGA design (FIGURE 5). Transistor technologies that allow monolithic 3D integration are experimentally demonstrated. “When you make the TSVs smaller and smaller, you can reduce the length of on-chip wires as well by taking what’s on a single now and stacking them into two layers,” Sekar said. “That might save a lot of power and area. There’s been a lot of talk about monolithic 3D, but these are some of the first few experimental demonstrations showing that it’s possible.”
[caption id="attachment_59995" align="alignnone" width="242"] FIGURE 5. Monolithic 3D-ICs produced by Leti.[/caption]
Through Silicon Vias (TSVs), an important component of 3D chip stacking technology, typically have a “keep-out zone” around them, where transistors are not placed. This is due to co-efficient of thermal expansion mismatch between the copper TSVs and silicon, which introduces tensile stresses in the silicon and changes transistor performance. These keep-out zones are typically >7μm, which adds constraints for design and leads to die size penalties.
Perhaps the ultimate ways of sending signals is not with electrons but with photons. Optical interconnects are already in use in telecommunications, and have been implemented at the backplane level on computer systems. Someday, we could see chip-to-chip level optical communication, and perhaps even on-chip.
In work from GLOBALFOUNDRIES, a CMP stop layer is specially designed such that it introduces compressive stresses on the silicon and compensates for the tensile stresses introduced due to copper TSVs (FIGURE 6). The result is a near-zero keep-out zone for TSV technology, that is validated with simulations as well as experiments.
[caption id="attachment_59996" align="alignnone" width="517"] FIGURE 6. Copper shrinkage results in tensile stress in the silicon while CMP stop layer shrinkage results in compressive stress in the silicon.[/caption]
At IITC, the first talk after the plenary talk is title “Nanophotonic and Interconnects - Status and Future Directions,” and will be delivered by one of the original pioneers in the field, David A.B. Miller, who runs the Ginzton Laboratory at Stanford University.
“Optical interconnects at progressively shorter distances and higher communications densities demand novel optics and very low operating energies. Optoelectronics with femtojoule or lower energies and compact custom and self-designing optics may enable the lower energy per operation and higher bandwidth density required for continued scaling of information processing, with significant potential impact for systems,” Miller says in his summary.
[caption id="attachment_59997" align="alignnone" width="625"] FIGURE 7. At the VLSI Symposium, Micron Technology will describe the first monolithic silicon-photonics-on-bulk-CMOS process flow to connect distant distributed memories.[/caption]
The upcoming Symposia on VLSI Technology & Circuits (http://www. vlsisymposium.org/), scheduled for Honolulu from June 9-12 (Technology) and June 10-13 (Circuits). Of particular note is a highlighted paper from researchers at Micron Technology describing the first monolithic silicon- photonics-on-bulk-CMOS process flow to connect distant distributed memories (FIGURE 7). Features include deep- trench isolation, polysilicon waveguides, grating couplers, filters, modulators, and detectors. Fully functional on-chip CMOS enables transmit
eceive operation while minimizing interconnect parasitics. With the addition of an external 1280-nm light source, a fully functional optical link (5 Gb/s with 2.8 pJ/b), capable of WDM (wavelength division multiplexing), has been demonstrated. In addition to the polysilicon resonant detector used in the link, a monolithically integrated SiGe-based photodetector using selective epitaxial growth was also developed.