Issue



In-line high-K/metal gate monitoring using picosecond ultrasonics


2014-05-16 09:53:19

Only a direct measurement of SRAM structures can represent true variations of metal gate height due to CMP process and is strongly affected by the design and layout of pattern, including pattern density, dummy design, and spacing.

By CHUN WEI HSU, United Microelectronics Corp., Tainan City, Taiwan; JOHNNY DAI,Rudolph Technologies, Inc., Budd Lake, New Jersey, USA

The pursuit of Moore’s law has dictated the scaling of semiconductor devices and has led to successful shrink of device form structures while delivering significant transistor performance improve- ments. In order to keep pace with the need for improved performance, new materials and new process integration schemes have been developed. High-K/ metal gate technology, introduced by Intel to replace the conventional oxide gate dielectric and polysilicon gate, has truly revolutionized transistor technology more than any other change over the last 40 years. First introduced at the 45nm node, this complex process has now been adopted for advanced nodes as the primary approach to address gate leakage and the reduction in gate capacitance due to poly Si gate electrode depletion issues [1].

FIGURE 1. (a) Schematic representation of the PULSE set up and (b) position sensitive detection (PSD) method. FIGURE 1. (a) Schematic representation of the PULSE set up and (b) position sensitive detection (PSD) method.

Two main integration schemes have been adopted by device manufacturers. The gate first approach (also known as Metal-Inserted Poly Si-MIPS) is similar to the oxynitride/poly process flow and is the preferred method for applications that require lower power that do not need the aggressive scaling of gate thickness [2,3]. The gate last approach (also known as Replacement Metal-Gate or RMG) takes advantage of strain enhancement techniques, such as e-SiGe, and a poly Si removal step and significantly improves hole mobility, making RMG an attractive option for high performance applications. The replacement metal gate approach includes two chemical mechanical polishing (CMP) steps. One is the poly opening polish (POP) process before dummy poly removal and the second is the aluminum CMP (AlCMP) process after work function metal deposition. Known concerns with this AlCMP process are Al dishing/erosion, gate height uniformity control and introduction of various types of defects that affect the performance and yield of the final device [4]. Control of gate height and uniformity is critical to transistor performance and precisely controlling this height is the primary challenge for the replacement metal gate AlCMP process. Non-uniform gate height can cause gate resistance variation, which results in parametric issues for the device. Thinner gate heights can result in over etched contacts [5]. The dimensional tolerance of the AlCMP process is much more challenging (10 times tighter) than the conventional CMP process because the metal gate height is only several hundred Angstroms [6]. Hence, in-line gate height monitoring is necessary for RMG to control gate resistance and avoid over etched contacts.

In this article we evaluate the capability of picosecond ultrasonic sonar measurements for in-line monitoring of high-/metal gate structures and demonstrate the benefits of this technology for measuring various structures, including SRAM, pad array, and line array key, with excellent correlation to cross sectional trans- mission electron microscopy (TEM). We have shown that only a direct measurement of SRAM structures can represent true variations of the metal gate height due to CMP process and is strongly
affected by the design and layout of
pattern, including pattern density,
 dummy design, and spacing. The small
spot, non-contact, and non-destructive
nature of this technology allows for
in-line measurements directly on these
structures with excellent repeatability
at a very high throughput.

Picosecond ultrasonic measurements


The Picosecond ultrasonic technology (PULSE) is a unique way of measuring opaque film thickness using an ultra-short pulsed laser. Because the technique is non-contact and non-destructive, it can be used directly on product wafers. In addition to thickness measurements, it can measure parameters such as roughness, density, phase and modulus to provide additional information about the reflected acoustic wave reaches the wafer surface, it is detected by a probe laser pulse, which was diverted from the pump pulse by a beam splitter and routed through a servo- controlled delay circuit to introduce a known variable delay process.

FIGURE 1a shows the optics layout of this technology. The system uses a pump-probe measurement technique. A 0.1ps pump laser pulse focused into a 5_7_m2 spot on the wafer surface induces a sharp acoustic wave that travels away from the surface through the film at the speed of sound. At each interface between layers a portion of the acoustic energy is reflected back toward the surface while the rest is transmitted. When the reflected acoustic wave reaches the wafer surface, it is detected by a probe laser pulse, which was diverted from the pump pulse by a beam splitter and routed through a servo-controlled delay circuit to introduce a known variable delay.

 FIGURE 2. TEM cross-section of product wafers generated for characterization using picosecond ultrasonic measurements.
FIGURE 2. TEM cross-section of product wafers generated for characterization using picosecond ultrasonic measurements.

There are two different methods of
 detecting the arrival of the reflected acoustic
 wave at the surface. The first method is to
 detect the change of optical reflectivity caused
by the strain of acoustic wave. The second method is to detect the deflection of the reflected probe beam that is caused by the deformation of surface due to the acoustic wave. The second method requires a position sensitive detector (PSD) as shown in FIGURE 1b.

FIGURE 3. Schematic representations of measurement sites (a) SRAM, (b) Pad array (c) Line array key. FIGURE 3. Schematic representations of measurement sites (a) SRAM, (b) Pad array (c) Line array key.

The PSD method shows better sensitivity and signal-to-noise for measuring thick copper and line array structures. Data reported in this article takes advantage of both measurement methods. The servo-delay controls the time difference between pump and probe, allowing accurate measurement of the round trip travel time of the acoustic wave within the film. Multiplying the one-way travel time (half of the roundtrip time) by the speed of sound in the material yields the layer thickness (equation 1). The thicknesses of component layers of a multi-layer film stack can be calculated similarly from the analysis of multiple return echoes from a single measurement.

(1) d=(v)(t)/2

where d is the film thickness in Å, v is the speed of sound in the material in Å/ps and t is the transit time in ps. Thickness is calculated from first principles and does not require calibration standards or reference wafers. Calibration of the system relies primarily on the positional accuracy of the delay stage. This is calibrated using optical encoders and corresponds to 1-1.5Å of the film thickness. This level of intrinsic matching allows for easy system-to-system matching across wafer fabs.

FIGURE 4. Raw data showing change in deflection versus time. The measurements are from DOE skew wafers of varying thickness from the SRAM structure. The large zero peak is the pump laser pulse and the next peak to the left is the first returning echo. The time elapsed to the first echo is seen to increase for the three wafers, corresponding to known increases in thickness. FIGURE 4. Raw data showing change in deflection versus time. The measurements are from DOE skew wafers of varying thickness from the SRAM structure. The large zero peak is the pump laser pulse and the next peak to the left is the first returning echo. The time elapsed to the first echo is seen to increase for the three wafers, corresponding to known increases in thickness.

Experimental

Product wafers including a nominal stack of PVD Al film/ CVD Al seed layer/ PVD Ti wetting layer/ N or P MOSFET work function metals/ TaN etch stop layer/ CVD oxide film/ Si-substrate were prepared (FIGURE 2) to systematically study the effects of CMP processes on the stack, specifically, characterization of metal gate height loss and Al metal dishing followed by defect analysis. The AlCMP process was carried out on a rotary type polisher with three polishing platens. Multiple sets of wafers (different products) with varying thickness skew were generated to test the capability of the picosecond ultra- sonic technique to measure a wide variety of structures: SRAM, pad array, and line array key (commonly measured by CD metrology tools). The arrays are shown schematically in FIGURE 3. The SRAM structure, although challenging with only 40% metal density, was selected to provide information on true process variation. Pad arrays (75% metal density) and line array keys (50% metal density) were also chosen to provide a comparison with the SRAM structure and to help determine the extent of pattern dependent variations in CMP rates. Structures for both N well and P well stacks of varying array widths were investigated.

FIGURE 5. Correlation of PULSE vs TEM measurements of (a) SRAM (b) Pad array and (c) Line array. FIGURE 5. Correlation of PULSE vs TEM measurements of (a) SRAM (b) Pad array and (c) Line array.

FIGURE 6. Resistivity measurements vs picosecond ultrasonic gate height measurements showing excellent correlation on both (a) NMOS and (b) PMOS devices. FIGURE 6. Resistivity measurements vs picosecond ultrasonic gate height measurements showing excellent correlation on both (a) NMOS and (b) PMOS devices.

Results and discussion

FIGURE 4 shows the raw timing
data of a PULSE measurement from
a center die on three thickness skew
wafers. The time elapsed between
the pump pulse and the returning
echoes, 7.3ps, 8.0ps, and 8.3ps, can
be used to calculate the thickness of
the layers (Al gate+work function).
 Longer times indicate thicker
films. Unlike other spectroscopic 
metrology technologies, which 
require sophisticated modeling and
 calibration, picosecond ultra sonic
technology provides a simple, direct measurement of thickness.

The accuracy of PULSE measurements for a wide thickness range of all three different structures was verified by comparison
to measurements made on the cross sectional TEM images. FIGURE 5 (a), (b) and (c) show the correlation between picosecond ultrasonic measurements and TEM on SRAM, pad array and line array keys, respectively. Correlation with TEM is excellent for all three structures (R2> 0.9).

PULSE measurements were also compared to resistivity (Rs) measurements to verify accuracy. FIGURE 6 shows Rs measurement for both NMOS and PMOS structures. Rs and PULSE measurements of gate height were conducted at Metal 3, and the AlCMP process step, respectively. The correlation between PULSE and Rs for both structures is ~ 0.90. The high correlation made it possible to predict Rs performance of the device at AlCMP.

In-line Monitoring Strategy: SRAM vs. Pad Array and Line Array Keys Pad arrays, nominally grids of pads with NMOS structure, or line array keys of varying metal density, are typically used for metrology thickness measurements but provide only an indirect indication of gate height. This study was specifically designed to evaluate picosecond ultrasonic technology’s capability to measure SRAM structures as a direct monitor of gate height, and, if successful, to adopt this strategy for in-line monitoring.

Direct measurement of gate heights in SRAM is complicated by the multilayer structure of the NMOS and PMOS devices, which have different work function metals and cross single trench isolation areas that introduce gate height variations. Given the complexity of the stack, concerns also exist regarding the accuracy and reliability of the measurement for in-line use. Measurements on pad and line array keys can only serve as an indirect measurement due to well-known pattern dependent variations in polishing rates. CMP rates are known to be affected by variations in design and layout of the pattern, differences in surrounding areas between grid pads and SRAM, pattern density differences, and effects of a dummy design, all of which can impact thickness measurement on the pads and arrays but does not represent the behavior on the SRAM structure.

Direct picosecond ultra- sonic measurements of gate height within the SRAM are feasible and show excellent correlation with TEM and resistivity measurements. Moreover, since the measurements are fast (<2 seconds), PULSE technology allows for sampling of more structures and die on the wafer to better characterize uniformity across wafer. The wafers show very similar profiles and the measurements can help process engineers better understand sources of within wafer variation. These measurements provide useful information for process optimization especially during development.

FIGURE 7. Correlation between SRAM gate height vs. PULSE for various structures. FIGURE 7. Correlation between SRAM gate height vs. PULSE for various structures.

FIGURE 7 shows the correlation between the SRAM gate heights as measured by TEM and PULSE thickness measurements for the various structures. PULSE measurements made directly on SRAM structures show excellent correlation (R2 = 0.94) with SRAM gate height. Additionally, high resolution scans were performed across the SRAM structures to characterize dishing/erosion profiles. FIGURE 8 charts the measurements on center, mid and edge die showing the thickness profiles and variations. In general, the wafers showed identical profiles on the three die. Thickness variation was ~20Å within the structure. FIGURE 9 provides details full wafer maps for both NMOS and PMOS devices. The data collected on these structures was used to better understand the within wafer profiles and guide process optimization.

FIGURE 8. High resolution line scan profiles from center, mid and edge die on an SRAM structure. FIGURE 8. High resolution line scan profiles from center, mid and edge die on an SRAM structure.

FIGURE 9. Full wafer maps of both NMOS and PMOS devices. FIGURE 9. Full wafer maps of both NMOS and PMOS devices.

 

Finally, measurement repeatability and stability were evaluated. TABLE 1 summarizes the results of dynamic (wafer load/unload) repeatability testing performed on SRAM structures across nine sites on a test wafer. The standard deviation is < 0.5% at each site and < 0.2% for the wafer average. FIGURE 10 shows results of measurement stability over a 10-day period when measuring daily production monitor wafers.

TABLE 1 TABLE 1

FIGURE 10. Long term stability monitored on daily QC wafers. FIGURE 10. Long term stability monitored on daily QC wafers.

Conclusion

PULSE technology is uniquely qualified
to provide the information needed
for tight process control for the High-K/
metal gate applications. Its small spot,
 non-contact, non-destructive nature
permits direct, in-line measurements
on product wafers. The measurements
provide accurate information to the process area on true thickness variations
that can be correlated with device 
performance. Excellent correlation
between PULSE, TEM and resistivity 
methods has validated the accuracy of the
technique. Direct PULSE measurements
on SRAM structures provide a means
of monitoring gate height that is clearly
superior to indirect measurements
using pad and line arrays, which are negatively affected by pattern dependent variations. In addition, the picosecond ultrasonic measurement system has demonstrated the repeatability and long term stability required for in-line metrology. Its capability has been proven for both pre-and post-CMP processes. Characterization of work function barrier layer measurement provides an additional benefit for the use of picosecond ultrasonic technology for HKMG process monitoring.

References

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2. Misra. V, Lucovsky, G., & Parsons G, “Issues in High-k Gate Stack Interfaces”, MRS Bull., 27 (3), 212–216 (2001).

3. Hoffman T. Y. “Integrating high-k /metal gates: gate-first or gate-last?”, Solid State Technology Review, (2010).

4. Hsien, Y.H., Hsu, H.K., Tsai, T.C., Lin, W., Huang, R.P., Chen C.H, Yang, C.L., Wu, J.Y., “Process development of high-k metal gate aluminum CMP at 28 nm technology node”, Microelectronic Engineering,92(4),19–23(2012).

5. Steigerwald, J. M., “Chemical mechanical polish: The enabling technology”, IEDM, 1-4 (2008).

6. Xu, K., Chen, Y., Iravani H., Wang Y., Swedek, B., Yu, M., Wang, Y., Tu, W., Xia, S., Karuppiah, L., “High k metal gate CMP challenges and solutions”, 218th ECS meeting, ECS (2010).