Highlights from the IMAPS Device Packaging Conference
By Dr. Phil Garrou – Contributing Editor
The annual IMAPS Device Packaging Conference in Ft. McDowell, AZ is always a source for the latest packaging information.
Ron Huemoeller, Sr VP at Amkor indicated that they are seeing customer programs using 2.5D silicon interposers to create mixed node modules, i.e. only the circuits that require it are moving to 14nm while the rest of the circuits are remaining on a separate chip using a legacy 28nm process. Reportedly this results in a lower cost solution.
Speaking of lower cost, Tezzaron / Novati CTO Bob Patti addressed the interposer cost issue head on during a panel session when he commented that silicon interposers at Novati today will cost you 25 cents per sq. mm but they see a path to eventually get the cost down to 2 cents per sq mm.
During Qualcomm’s Steve Bezuk keynote talk on mobile packaging he noted that 7B smartphones are expected to be shipped between 2013 and 2017. With handset thickness quickly approaching 6mm and the battery and screen not shrinking, the package and board must absorb all the z direction miniaturization. Thinner substrates have been achieved so far by using thinner cores . To avoid warpage suppliers have used lower and lower CTE core materials. Since that has now run out of steam they will now be looking for low CTE materials with higher modulus to maintain stiffness.
Bzuk’s comment on 2.5/3D that “…we are not yet sure what the substrate material should be (Si, laminate or glass) or where it will be coming from…” is a sober reminder that mobile will likely not be the initial driver for TSV based technologies.
Bryan Black, Sr Fellow at AMD brought some good news for the 3D community when he stated “Die stacking is catching on in FPGAs, Power Devices, and MEMs but there is nothing in mainstream computing CPUs, GPUs, and APUs …HBM Stacked DRAM will change this!” He predicts that we will see 3X the bandwidth/watt using stacked memory.
As we have mentioned in previous blogs Black predicts the SiP of tomorrow will be separately optimized / manufactured functions stacked on an interposer. While the busses needed to connect these functions will be complex, Black is convinced that this is doable . Black indicates that AMD and partner Hynix are currently looking for partners to develop such products.
Brandon Prior of Prismark reported a major move to 0.4mm pitch by 2018 (28% of all CSP/WLP) but notes that challenges remain for assembly yield and PCB routing for 0.35mm and below. Prismark predicts that performance DDR will adopt flip chip at all of the major memory suppliers with 5B units being shipped by 2018.