Challenges of EUVL HVM
By Vivek Bakshi, EUV Litho, Inc.
Most of the papers at this year’s EUVL Conference during SPIE’s 2014 Advanced Lithography program focused on topics relating to EUVL’s entrance into high volume manufacturing (HVM).
In their paper, GLOBALFOUNDRIES compared EUVL and ArF immersion scanners for 20/14nm metal lines and found equal yields for both lithog- raphy techniques. They did note an additional issue of EUV mask backside contamination, which I believe can be addressed. For 10/7nm metal lines, they believe they need to address issues of overlay, mask defects, integration and line width roughness (LWR) through focus, in order to bring EUVL into production.
Imec presented a preliminary cost of ownership (COO) study that concluded that at the 7 nm node, 75 wafers per hour (WPH) throughput will be needed for EUVL to show better COO than ArF immersion (ArFi) multiple patterning (MP). This throughput corresponds to 100 W of source power at the intermediate focus.
HVM-related metrics such as yield and availability (mean time to failure [MTTF], mean time to repair [MTTR], etc.) are now the focus. It was evident from the talk by TSMC, which reported ~10 W of power instead of the expected 30 W for their planned insertion of EUVL into the 10 nm node. A laser misalignment caused a source breakdown and a two-week unexpected downtime for the tool. Although some saw this as a setback, a brand new tool’s first installation in the field can be expected to have glitches and downtime. TSMC reconfirmed their commitment to bring EUVL into HVM at the 10nm node.
Mark Philips of Intel, in his talk, outlined the 1-D grating and cuts approach of Yan Semiconductors Borodovsky. EUVL is the preferred choice for cuts as EUVL offers advantages in terms of number of masks and edge placement error (EPE). Intel still plans to insert EUVL at the 7nm node in 2017, but needs a mature COO for EUVL. It will be either mix and match with ArFi MP or EUVL alone, depending upon the cost drivers.
As the mix and match approach faces the issue of overlay, he presented a detailed model, developed with Mike Hanna of ASML, that identifies the root cause of machine to machine overlay values and will help minimize it. Current machine to machine overlay (EUVL and ArFi) is 5 nm but needs to be 3.5 nmat10nmnodesand3.0nmat7nmnode.My perception is that with the amount of effort going into it, those goals can be achieved.
Hynix, in their paper on EUVL development efforts, made a comment that self-aligned quadruple patterning (SAQP) has 5x more steps than EUVL and that many multiple patterning steps take away any benefit that one can expect from it, and hence are not beneficial.
ASML currently has three NXE 3300B, HVM level scanners being installed in the field, including one at TSMC. They reported 30 W power (down from 50 W reported in the lab last year) with 100 W planned for this year and 250 W for next year. We know that TSMC had only 10 W at the time of conference. With ASML acquiring Cymer, I expected a change in how data is presented, with more realistic roadmaps. I understand that to predict the readiness of source is very hard, as there are many new technologies that may do well in the lab with a dozen PhDs fine-tuning them, but aren’t necessarily ready for the field where they have to perform 24 x 7 while being operated by technicians.
My personal opinion is that if we can get 50 W with decent availability in the field this year for 3300 B, it will be a great achievement. 100 W will follow over the coming years and I cannot predict yet when 250 W sources will be ready. With the data that I currently have seen, I will stick with my predictions.