How finFETs ended the service contract of silicide process

2016-03-25 10:55:10

A look into how the silicide process has evolved over the years, trying to cope with the progress in scaling technology and why it could no longer be of service to finFET devices.

BY ARABINDA DAS, TechInsights. Ottawa, Canada

Samsung and TSMC introduced their finFET devices in 2015 and joined Intel as the semiconductor industry’s three major manufacturers possessing the most advanced technology. Intel’s 14nm finFET 5Y70 processor was commercialized in 2014 and within six months Samsung mass produced their 14nm finFET Exynos 7 7420 SoC. Later that same year, TSMC started supplying their 16nm finFET based devices to Apple. Today Samsung and TSMC both supply their finFET based processors to Apple, which are being used for the iPhone6’s A9 processor.

Since the release of the iPhone6 several blogs and articles have been written about the cost of fabrication, the perfor- mance of tri-gates, the type of work-function materials used by the manufacturers, the dominant supplier for Apple and speculation about the future of finFET devices. TechInsights has performed detailed structural analyses of these three devices and has also tried to understand some of these questions. While comparing these structural reports on finFET devices, one small detail stands out is that a major pillar of semiconductor processing is missing. The silicide process is not being used. Intel stopped using the silicide process in their 22nm finFET “Ivy Bridge” Processor. Samsung and TSMC at 20nm used the existing planar structure and employed NiSi on top of their source and drain regions. But as soon as these two device makers adopted finFET structure in 14 and 16nm nodes they abandoned the thirty year old silicide process. It is interesting to look into how the silicide process has evolved over the years, trying to cope with the progress in scaling technology and finally also why it could not anymore be of service to finFET devices.

The silicide process has been an integral part of semicon- ductor manufacturing since the early 1980s. The first patents were filed by Motorola, Fairchild and IBM. This process is used as an interface between semiconductor material and metals to reduce the contact resistance between tungsten contacts and the source-drain regions or the gate electrode. This parasitic resistance should be minimized to enable higher drive currents in transistors. Silicides have metal-like properties and are made by reacting Si to refractory or near-noble metals. A large number of metals in the periodic table can form silicides. The most common silicides in the semiconductor industry are titanium silicide, tungsten silicide, cobalt silicide, nickel silicide and nickel-platinum silicide. Platinium was used to stabilize the NiSi phase at a specific temperature.

These compositions can exist in various phases and have unique phase diagrams. One particular integration process of silicides, known as self-aligned silicides (also termed ‘salicide’), has played a significant role in bipolar devices, passives and in CMOS devices. In this scheme, no additional mask is needed; the silicide is grown on exposed silicon or polysilicon surfaces and not at all on neighboring dielectric surfaces.

The main steps of growing the silicide are depositing a refractory metal or a near-noble metal on the exposed Si and then annealing in a non-oxidizing atmosphere at a suitable temperature to react the metal with Si. The duration of the thermal cycle should be long enough to convert the majority of the metal to a silicide composition. Several stages of annealing may be completed to stabilize the phase. Thereafter the unreacted metal is removed by wet-etching. For a detailed understanding of silicide process please refer to the book “Silicide technology for integrated circuits” by L.J. Chen or to the lecture notes from Professor Sarsawat from Stanford University [1].

The earliest image of the silicide process in TechInsights’ database is from Intel’s 166 Mhz Pentium microprocessor A80502166 based on a 0.35 μm CMOS process. The die markings of this device suggest that it was made in 1992-93. FIGURE 1 shows a TEM cross-section of a gate employing titanium silicide. The transistors in this device have 0.40 μm thick titanium silicide on top of the gates and silicided diffusions formed using a salicide process.

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The industry realized very quickly that TiSi2 was not easily scalable. It has two phases C49-TiSi2 and C54-TiSi2. The first is formed at temperatures between 350 to 700o C and has a resistivity of 60-80 μΩcm; while the other is formed around 750 ̊ C and has a resistivity lower than C49-TiSi2 (~20 μΩcm). As devices scaled down it became necessary to reduce the thermal budget which had the consequence of forming C49-TiSi2 instead of C54-TiSi2, which resulted in higher contact resistance. Since this was counter-productive, it was time to switch to a new silicide. Intel’s Pentium III “Tualatin” used Co-silicide in a 0.13 μm CMOS process (FIGURE 2).

The next major milestone for silicide processes came at the 90nm node when Intel introduced the concept of raised source and drain for the PMOS transistor in their “Prescott” processor. The raised source and drain regions were formed by etching out portions of the Si substrate at the source and drain regions and then depositing epitaxial layers of Si1-xGex, where x is between 0 and 1. The etching out used both dry and wet chemistry. This concept was an innovative use of the growth rate variability on the bottom surface and on the side walls of the cavity due to the different crystal plane orientations of the silicon substrate. SiGe has a lattice constant that is slightly larger than that of silicon so this epitaxial film induces a large uniaxial compressive strain in the PMOS channel region, resulting in significant hole mobility improvement. But SiGe surfaces were not very suitable for Co-Silicide. Most silicides have much lower free energy than germanides so when the silicide is formed on a Si-Ge alloy the Ge is expelled. This expelled Ge undergoes agglom- eration and increases the contact resistance thus negating the effect of the enhanced mobility. The use of Ni instead of Co was especially beneficial for salici- dation of both Si and SiGe source drain regions because Ni provides a more uniform contact resistance. Moreover, NiSi has the same resistivity as CoSi2 but has smaller Si consumption. FIGURE 3 shows Intel’s 90nm “Prescott” transistor along with NiSi on top of SiGe regions.

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NiSi was the mainstream process for two process nodes (90nm and 65nm) and was employed on top of polysilicon gate as well as on top of the source-drain regions. Around the year 2000, there were even discussions about a fully silicided (FuSi) gate. Then in 2008 Intel introduced the high-k dielectric and metal gate-last (HKMG) process at the 45nm node in their “Penryn” processor. This device did not require any more silicide on top of the gate but only at the source-drain regions. FIGURE 4 shows a TEM cross-section of Intel’s 45nm “Penryn” processor. In these devices, silicide is formed only on top of source and drain regions. The silicide is self-aligned to the sidewall spacer. The surface of the SiGe source-drain regions that is in contact with the silicide has enriched Si concentration to facilitate the silicide process. The nickel silicide depth from the silicon surface is about 65nm.

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Finally, in 2012 Intel commercialized the first finFET device at 22nm in their “Ivy Bridge” (Intel core i5-3550) processor, in this device the silicide process was abandoned. To understand why the silicide process was not employed, it is important to grasp the differences between a tri-gate device and a planar device. Tri-gate brought in several advantages. For example, the effective gate width is proportional to the fin height and can be increased without increasing the device footprint. Additionally, because the gate wraps around the fin, there is better control of the channel. Another benefit is that the walls of the fin offer a different crystallographic plane than the top of the fin. Here, in this integration schemethe PMOS transistors benefit from higher mobility along the fin sidewalls.

The tri-gate integration scheme also brought in several process challenges. Epitaxial SiGe for PMOS and epitaxial Si islands for NMOS must be grown in a recess in a narrow Si fin rather than in the Si substrate. One constraint is due to double patterning, which requires that all the fins be of the same width and pitch; so if a larger gate width is required then multiple fins have to be employed. That means that the gate width is dependent on integer units of fins. This concept of integer units of fins is well illustrated in FIGURE 5, where the I/O transistor of TSMC finFET is shown having several fins connected in parallel.

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Multiple fins connected in parallel imply that the contact to the source-drain regions must have exactly the same contact resistance on multiple fins and this was indeed difficult to guarantee with the silicide process due to the vagaries of the diffusion process. In the Ni silicide process, it is believed that Ni atoms are the dominant diffusing species in Ni monosilicide formation; this property can lead to excessive silicidation on narrow lines. Ni-silicide is sensitive to temperature and often at low temperature a NiSi2 is formed. This phase is usually seen on strained PMOS structures and can create an increase of contact resistance. Non uniform distribution of silicide process was the biggest show-stopper for this old process.

In addition to the silicide process there was also the problem of dopants in the source and drain regions. The thermal process causes undesirable dopant diffusion and leads to the loss of the junction abruptness. Also, thermal processes create thermal budget issues in the integration’s process flow. There could be also other reasons for avoiding the silicide process in finFET devices, like leakage and stress because it is well known that the silicide process has an impact on device properties. Luckily, the technology of in-situ doping was already mature and used for DRAM devices as these volatile memories do not require a silicide process due to leakage concerns. Intel in its 22 nm process flow, most likely used in-situ doping of epitaxial regions along with trench contacts to eliminate the silicide process. This does not mean that other doping techniques like implants and thin film doping were not employed; they were probably used during different parts of the process flow. Intel did mention at IEDM 2014 that thin film doping method was used for 14nm finFET devices.

The introduction of trench contact, which ensure equal and low contact resistance to multiple fins was the ultimate reason not to use the silicide process in FinFETs. The integration flow is described in FIGURE 6. First, multiple parallel fins are formed. Each fin is separated from its neighbors by the STI-oxide. On these fins a sacrificial poly-silicon gate structure is made that runs perpendicular to the fins. On portions of the fin not covered by the gate, cavities are etched by using a line mask or a self-aligned process. Recesses in the fins are made by selectively etching the silicon. In-situ doped epitaxial layers are then grown to form source-drain regions. These epitaxial layers extend beyond the fin width and may even merge to form a continuous layer. The epitaxial layers do not extend above the surface of the fin. Subsequently, the poly-silicon gate is removed and the high-k-metal-gate (HKMG) formed in its place. A dielectric layer is deposited on top of the gates and the fins. The dielectric layer is patterned to form trenches running parallel to the gate. The integration scheme further includes etching a trench in the epitaxial layers and then filling the trench with tungsten to form trench contacts.

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FIGURE 7 shows the cross-sectional schematic diagram of how the trench contacts are embedded or well anchored in the epitaxial layers.

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Cross-sectional images parallel to the fins of the three 1x node finFETs from Intel, Samsung and TSMC are collected in FIGURES 8a, 8b and 8c, respectively. The cross-section is made along one of the fins. The important point to note is that the trench contact at the surface of the source and drain regions is surrounded on three sides. It is more pronounced in the case of Samsung’s device. The tungsten metal lines that run parallel to the gate, form the contacts for source-drain regions and are well anchored in the epitaxial layers. This increases the surface area of the contact and reduces the contact resistance.

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FIGURE 9 shows the cross-section of the 16nm finFETs from TSMC in the direction perpendicular to the fins. In this direction the epitaxial regions could be designed to merge or extend beyond the fin width and thus increase the contact region with the metal contact. This increased contact region reduces the contact resistance.

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The silicide process has a long history in the semicon- ductor industry; it has evolved through many phases from tungsten silicide to titanium silicide to cobalt-silicide to nickel silicide. But it could not be used for finFET devices. As for these devices, multiple fins may be used to form a single transistor, which implies that the contacts to all these fins have the exact same contact resistance. This is difficult to control in a process that is purely based on diffusion like the silicide process. So after 30 or more years of service it is time that the silicide process takes retirement and leaves the future to trench contacts and in-situ doping; however, there is always a possibility its use may be prolonged especially if the silicidation can be localized only inside the trench contact and not over the entire surface of the source-drain regions. Trench contacts will most likely be used in the next 10nm node but sub 10nm node, if new concepts like nanowire or new materials are introduced, the semiconductor industry is likely to innovate some other designs.

ARABINDA DAS is a Senior Process Analyst in the Technical Services division of TechInsights, Ottawa, Canada,