How low can we go?
By Ed Korczynski
In the advanced CMOS technology programs ongoing in the Belgium city of Leuven, imec works to extend the building-blocks of integrated circuits (IC). On the day before the opening of SEMICON West 2017, the invitation-only imec Technology Forum provided an update on the emerging opportunities in semiconductor technology and smart electronics systems. An Steegen, Executive VP Semiconductor Technology & Systems, provided the update on how small we can scale CMOS devices over the next 5-10 years. Taller finFETs will likely be used along with nano-wire FETs (NW-FET) by industry, and researchers see ways to cost-effectively combine both in future optimized System-on-Chips (SoC).
“Existing finFET technology can scale to the 5nm-node,” explained An Steegen at ITF 2017 in Antwerp, Belgium. “However, at the 3nm-node it looks like the nano-wire is comparable in performance to the finFET, but it has an additional advantage in that the nanowire is a better electro-statically controlled device so it enables gate-length scaling more than the finFET. So the contacted gate pitch (CGP) of a nano-wire can scale further than a finFET, because below ~40 nm CGP a finFET loses electro-static control which a nano-wire does not.”
While it is given that a nanowire has better electro-static control compared to a finFET, the basic trade-off is that of reduced drive current. The Figure shows that IMEC sees the possibility of System-Technology Co-Optimization (STCO) of future system-on-chip (SoC) designs using hybrid semiconductor technologies. imec’s basic process flow for NW-FETs starts with forming fins and so could be relatively easily integrated with finFETs for co-integrated hybrid CMOS.
System-Technology Co-Optimization (STCO) for future System-on-Chip (SoC) designs could integrate finFETs with Nano-Wire FETs (NW-FET) and Magnetic Random Access Memory (MRAM) for optimized performance. (Source: imec)
“Today, this SoC is processed in one technology which means it’s sub-optimal for certain blocks on the SoC,” explained Steegen. “So imagine a future where you can choose the preferred technology for each block. I would choose finFETs for those blocks that need drive current, while I would choose nano-wire-FETs for those blocks that need more density and lower power. I would for example choose a magnetic RAM to replace my cache memory. I can optimize each sub-block for a preferred technology. Now I can do more, like sprinkle in low-energy devices like tunnel-FETs or spin-devices or 2D-materials as low-energy switches.”
Super-vias and Rutherails
Design-Technology Co-Optimization (DTCO) is imec’s term for new interconnect technologies to allow for simpler or more-compact designs. IDTCO process-scaling boosters are needed to stay with the pace of aggressive design rule targets. “We’re working on super-vias that connect more than one metal to the other and can jump a number of levels, and buried rails to support finFETs in standard-cell libraries,” explained Steegen during ITF2017.
Super-vias could be cobalt plugs that connect more than two metal levels within on-chip multi-level interconnects. The cobalt plugs would be nominally 20nm diameter and 105nm deep, and connected to a dual-damscene upper metal line. Low-k dielectric of k=2.55 uses thin silicon carbon nitride (SiCN) for definition between the damascene levels.
Ruthenium rails (Rutherails) would be buried in a front-end dielectric layer to provide electrical contacts below finFETs for 42nm CGP and 21nm MP needed for imec 3nm-Node (I3N) devices. Ruthenium rails 30nm deep and 10nm wide do not need complex barrier layers and should provide sufficient current flow for either finFETs or NW-FETs.
imec is also working on materials R&D to extend the performance of 3D-NAND. Steegen said,
“At imec we are working on improving the performance of that Flash device by introducing high-mobility channels, also by engineering the dielectric trapping layer with a barrier that can help improve the erase window and also the retention.”