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Solid State Technology
3D Integration: The Challenges Ahead
The potential benefits of 3D integration -- where chips are thinned, stacked and electrically connected with through-silicon vias (TSVs) ??? are by now well known for stacking memory and for communication chips.
The rule of three for CMP
Michael A. Fury, Techcet Group, LLC, Del Mar, CA
3D activity at SEMICON West
At the TechXspot session on "Bridging the Gap," Steve Bezuk of Qualcomm shared his views on mobile device packaging.
Real-time CMP monitoring tracks LPCs
With continued device geometry and new process steps comes increasing use and variety of CMP steps???e.g. through-silicon vias (TSV), ceria used for shallow-trench isolation, very thin interlayer dielectrics, colloidal silica for copper steps, copper barrier steps.
450mm report: Standards, AMHS, platforms getting ready
In its closed-door session during SEMICON West, the International SEMATECH Manufacturing Initiative (ISMI) presented an update on the steps it is taking this year to provide the needed infrastructure, and momentum, to enable an eventual transition to the 450mm wafer size???from readiness of silicon, processes, and equipment, to factory integration issues, test wafer generation, and equipment testing methodologies.
Interfacial properties of Cu-Cu direct bonds for TSV integration
With varying process conditions, the quantitative analysis of the interfacial adhesion energy of Cu-Cu thermo-compression bonds was performed. Bioh Kim, et al, EV Group, Inc., Tempe, AZ USA; Eun-Jung Jang, et al, Andong National University, Andong, Korea
Process equipment readiness for through-silicon via technologies
Unit processes, integration schemes, and equipment are in place to enable development and pilot production of TSV technologies and all parts of the value chain do exist today at 300mm to enable integration technology qualification, end-product samples, and limited pilot production. Sesh Ramaswami, Applied Materials, Santa Clara, CA USA
Convergence of 3D integrated packaging and 3D TSV ICs
As the need to integrate MEMS devices and advanced memory for sensor applications expands, work is underway to develop modules merging both mechanical and electrical devices into single, highly compact modules. Navjot Chhabra, Freescale Semiconductor, Austin, Texas, USA
System In Package
Achieving cost and performance goals using 3D semiconductor packaging
It has been proven that SoC and 3D multiple die packaging can significantly improve performance and the function-to-area ratio, however, one must look at the tradeoffs. Vern Solberg, STC-Madison, Madison, WI USA
Overlay error components in double-patterning lithography
Wafer selection at the beginning of a process could help minimize the effects of shape changes during the wafer processing that may affect overlay error. Venkat R. Nagaswami, et al, KLA-Tencor Corp., Milpitas, CA