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Solid State Technology
Heard at The ConFab 2010
Increasingly, advanced semiconductor manufacturing research is a collaborative effort.
Innovative financing options a must for the industry
James Quinn, Replisaurus Technologies, Kista, Sweden
IMEC tips work in Ge CMP, epitaxy
European R&D consortium IMEC recently offered more details of its work in Ge-on-Si and other novel materials, in efforts to improve two processes: optimizing chemical mechanical planarization (CMP), and improving epitaxial growth using hydrogen and "inert species."
EUV players hit 100W output with LPP source
The Extreme Ultraviolet Lithography System Development Association (EUVA) says it has surpassed 100W output at intermediate focus for an EUV light source, addressing a big hurdle facing EUV lithography as a production-viable candidate for next-generation semiconductor manufacturing.
Toshiba's 25nm trial ups ante for NAND scaling, next-gen litho
Toshiba is prepping a ??15B (US $157M) investment in a <25nm NAND flash test line, eyeing mass production in 2012, a move that not only tightens the NAND flash scaling wars, but also could narrow the insertion point for a next-generation lithography set.
EU group takes stride toward optical interconnects
An EU-funded project has come one step closer to its goal of building silicon photonics circuits, with the creation of a fully CMOS-compatible laser source coupled to a silicon waveguide.
HP: Memristors now a reality
New insights into memristors could offer an offramp to the increasingly challenging navigations of Moore's Law scaling, and some very interesting applications in biomed research.
FEI eyes 3D structures with integrated SEM/FIB platform
FEI Co. has introduced its Helios NanoLabx50 DualBeam Series (450(S) and 650) that integrates the company's extreme high-resolution scanning electron microscope (XHR SEM) with a new, high-performance focused ion beam (FIB).
Novellus tips WN film for 3X memory Cu interconnects
Novellus says it has devised a new process technology for tungsten vias for copper interconnect applications in 3X node and below memory devices.
Accelerating high-k dielectric solutions for next-gen DRAM capacitors
High-productivity development techniques have been applied to surface preparation and deposition, however, broadly applied, this approach has the potential to significantly improve overall efficiency and effectiveness of industry R&D efforts. John Doering, ATMI, Tempe, AZ USA, Weimin Li, ATMI, Danbury, CT USA
Analyzing noise in modern MOSFETs
Relaxation energies associated with defects in high-k/metal gate devices indicate oxygen vacancies in the interfacial SiO2 layer. D. Veksler, et al, SEMATECH.
Heterogeneous microtechnology – an area for smart designers
Heterogeneous microsystems are smarter than their macroscopic counterparts, more powerful and energy-efficient. Jan Provoost, Chris Van Hoof, Imec.
The second wave of 3D packaging technology: PoP
PoP, together with WSP and QFN, have been the industry???s most successful packages during the last decade, and their success will extend into this decade. Mario A. Bolanos, Texas Instruments Inc.
Combinatorial tooling for development of cost-effective and efficient ALD
The authors describe the construction and characterization of an ALD process development chamber. Prashant Phatak, et al, Intermolecular Inc.
Improving 22nm design space with source/design optimization
Source/mask optimization techniques show promise for extending the resolution capability of the single-exposure approach. Jim Blatchford, et al, Texas Instruments, Inc.; Thuc Dam, et al, Luminescent Technologies.
The effect of grounding on electrostatic damage
A new SEMI standard addresses ways to improve the electrostatic protection of new generations of extremely electrostatic sensitive devices. Gavin Rider, Microtome.
Air gaps for interconnects: ready to go?
The scalability of Cu/air gap interconnects to future technology nodes appears to be possible with air gaps, without performance or reliability losses. Gerald Beyer, et al, IMEC, Leuven.