Table of Contents

Solid State Technology

Year 2008
Issue 4



It’s springtime for creative engineers

It’s springtime for engineers in electronics, computing, and chip architecture.

World News


Worldwide semiconductor capacity and output both slowed significantly in 4Q07, but for the first time in a year and a half factory utilization rates crept up above the benchmark 90% level.

Technology News.html

Technology News

Beyond Cmos

Imprint litho forms arrays for new fault-tolerant nanoscale circuits

Extending Moore’s Law to 22nm and beyond for logic circuits calls for new concepts in manufacturing processes and device architectures.

Q Amp A

Hermans leads accelerated MEMS development at IMEC

There’s much more going on at the Belgian research center IMEC than the relentless pursuit of Moore’s Law and semiconductor process technology scaling.

Contamination Control

Using existing production tools for low-cost thin wafer handling

In 2003, NXP CAEN opened a new pilot line dedicated to innovative solutions in system-in-a-package (SIP) on 150mm wafers.


Featured Product

The Tachyon 2.5 computational lithography platform and the Tachyon DPT, an advanced double patterning technology (DPT) solution, have been introduced.


Product News

System improvements to the model 9200 PanelPrinter system include handling as many as 60 reticles on its automated reticle library subsystem, with automatic loading of up to 6 masks/layer.

Industry Forum

Riding the wave of CMP

CMP is rapidly becoming one of the most important and widespread fab processes enabling the continuation of device shrinks.


Patterning Technology

OPC model separability speeds computational lithography

In low k1 lithography, process integration and qualification are of little value without OPC-corrected masks.

Cover Article

Full-wafer post-via wet clean nonvisual defect inspection

The optimization of wet clean and surface preparation processes is an industry challenge, due in part to the lack of adequate inspection techniques to detect nonvisual defects (NVD).

Modeling Simulation

Using scanner systematic signatures to enhance OPC modeling

At previous technology nodes, scanner systematic signatures–including illuminator pupil-fill and polarization, lens aberration, lens apodization, and flare–could be ignored without significantly impacting optical proximity compensation (OPC) accuracy.


Compensation for local proximity effects

Short range proximity effects in maskmaking processes require compensation over and above that presently applied to account for other effects such as electron backscattering.


On-the-fly threshold voltage measurement for BTI characterization

Advances in traditional CMOS scaling techniques are reaching their limits, bringing up the need for new materials and novel device designs.

Flexible Elecronics

Coating and deposition for flexible organic electronics

Developers of flexible, printed, and organic electronics (FPOE) products face significant challenges in scaling to true volume production.