It’s springtime for creative engineers
It’s springtime for engineers in electronics, computing, and chip architecture.
Worldwide semiconductor capacity and output both slowed significantly in 4Q07, but for the first time in a year and a half factory utilization rates crept up above the benchmark 90% level.
Imprint litho forms arrays for new fault-tolerant nanoscale circuits
Extending Moore’s Law to 22nm and beyond for logic circuits calls for new concepts in manufacturing processes and device architectures.
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Hermans leads accelerated MEMS development at IMEC
There’s much more going on at the Belgian research center IMEC than the relentless pursuit of Moore’s Law and semiconductor process technology scaling.
Using existing production tools for low-cost thin wafer handling
In 2003, NXP CAEN opened a new pilot line dedicated to innovative solutions in system-in-a-package (SIP) on 150mm wafers.
The Tachyon 2.5 computational lithography platform and the Tachyon DPT, an advanced double patterning technology (DPT) solution, have been introduced.
System improvements to the model 9200 PanelPrinter system include handling as many as 60 reticles on its automated reticle library subsystem, with automatic loading of up to 6 masks/layer.
Riding the wave of CMP
CMP is rapidly becoming one of the most important and widespread fab processes enabling the continuation of device shrinks.