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Solid State Technology
Welcome to ElectroIQ!
Peter Singer, Editor-in-Chief
3D IC technology drives public investment in 300mm
Given the many open challenges, it is important that material and equipment providers join forces with research organizations to work on 3D technology solution.Dietrich Tonniers, SUSS MicrTec
Commercializing a WLCSP passivation layer solution
Russell Stapleton, senior staff scientist at Lord Corp., gave SST a summary of his Aug. 26 presentation at the Arizona chapter of IMAPS (International Microelectronics and Packaging Society) concerning the company's first-generation passivation layer solution for wafer-level chipscale packaging (WLCSP), expected to be commercialized in 1Q10.
Pushing c-Si efficiency to 20% with narrower interconnect
Photovoltaic cells are getting steadily more efficient, and even the small area taken up by interconnect is shrinking to get moreelectrons flowing.
Researchers at IBM and the California Institute of Technology say they have a possible solution to key problems looming for post-22nm node semiconductor manufacturing: a combination of lithographic patterning and self-assembly that arranges DNA structures on surfaces compatible with current manufacturing equipment.
FEI's Tecnai Osiris S/TEM goes for speed in analytics
FEI Co. recently released its Tecnai Osiris scanning/transmission electron microscope (S/TEM).
Optimization of edge die yield through defectivity reduction
As the economics of semiconductor production dictate new efficiencies for supporting market needs, the wafer edge region is emerging as a key focus area in process optimization and control. Kalyan Jami, Srini Vedula and Gerry Blumenstock, KLA-Tencor Corp; Jack Chen, Keechan Kim, Yunsang Kim, and Yung Kim, Lam Research Corp.
Copper interconnect advances to meet Moore's Law milestones
3D interconnects allow continued 2D scaling through extension of extension of existing process technologies without the need to invest in more expensive lithography solutions. Ajay Bhatnagar, Mehul Naik, Sesh Ramaswami, Matthew Spuller, Michael Armacost, Russ Perry, Jim Van Gogh, Jen Shu, and Gray Miner, Applied Materials.
Building blocks for wafer-level 3D integration
Candidate building blocks for different 3D integration schemes have been demonstrated to be compatible with back-end-line CMOS processes and with aggressive wafer grinding and thinning. Mariam Sadaka, Soitec USA Inc.: Lea Di Cioccio, CEA-DRT-LETI.
Understanding tester interfaces
Hands-on insight into four classes of signal integrity problems - Impedance mismatches, crosstalk, transmission line loses, and inadequate power distribution - with the test cell and DUT interface. Nick Langston, Liberty Research.