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Solid State Technology
SEMI: Wafer shipments, sales slide in ‘08
Worldwide silicon wafer area shipments and revenues fell in 2008 for the first time since 2001 as everything fell apart in the final months of the year, according to date from SEMI’s Silicon Manufacturers Group (SMG).
A reliability engineer’s dream comes along
In a former life within the semiconductor standards and reliability engineering community, I advocated for the adoption of well-known reliability and maintainability engineering practices that have been used for decades in the aerospace and defense sectors.
SVTC, Entrepix expand CMP work to 300mm
SVTC Technologies (née Cypress Semiconductor’s Silicon Valley Technology Center, spun out to VC/private equity owners in March 2007) and CMP outsourcing firm Entrepix are expanding their existing partnership to 300mm wafer processing.
Holistic efficiency optimization: how to help in a downturn
The industry is in another cyclical downturn. No one knows the depth or length of this cycle, but one thing is certain — manufacturing efficiency will be important.
How Green is Your Valley?
The global explosion in IT, combined with rapidly escalating energy costs, has chipmakers asking how much does it really cost to run today’s computers/servers, and what can be done to provide more energy-efficient solutions?
Ion implant: a new enabler for 32nm and 22nm devices
Over the years, suppliers of ion implant tools have competed mostly on productivity and cost of ownership differentiation.
Combinatorial PVD and ALD workflows for cost-effective R&D
Special workflows using combinatorial technology applied to physical vapor deposition (PVD), atomic layer deposition (ALD) and wet processes can be utilized for applications including development of alternative non-volatile memory and metal gate high-k dielectrics for high-performance logic.
Meeting current and future wafering challenges
Currently, the multi—wire slurry sawing (MWSS) technique is the leading technology for high precision machining of large cross—sectional area wafers for both the semiconductor and photovoltaic industries.
3D integration with TSV: temporary bonding and debonding
Making reliable through-die interconnects for 3D wafer stacking usually requires a reduction in wafer thickness and therefore improved wafer handling.
Burn-in Test Socket Challenges
This article provides a broad review of the issues affecting socket usage: lead-free challenges, finer pitch adjustments, cost control, standardization, practical customer concerns, and improvements needed for 3D packages and other innovations on the horizon.
Kelvin measurement using spring probes for packaged IC testing
Test engineers often look to leverage a Kelvin-measurement configuration when testing high-power devices, particularly QFN packages — even as the finer-pitch terminal in latest-generation packages makes it difficult to accomplish.