|Table of Contents|
Solid State Technology
Leaving a legacy
When former US Vice President Al Gore testified on climate change before US House and Senate committees this spring, he called on the US to take the lead in reducing the greenhouse gases responsible for global warming.
Merging mask design and manufacturing to drive cycle-time improvement
Semiconductor industry observers who think the drive for lower manufacturing costs and cycle time is a recent phenomenon would do well to acquaint themselves with the history of the data handoff between design and manufacturing.
Advanced Process Control
Implementing a strategy for effective fab data management
IC manufacturing is performed with hundreds of sequential steps, each of which could experience problems leading to yield loss.
Improving wafer yields with integrated all-surface inspection
Although backside defects have historically received much less attention than frontside defects, semiconductor manufacturers now realize that backside defectivity can contribute significantly to yield loss.
A double-line/double-patterning process to extend immersion beyond 45nm
Since the fall of 2003 when immersion lithography produced its first images and began appearing on roadmaps, the technology has made rapid progress towards maturity.
Using Strain Engineering
Using strain engineering to improve NVM retention time
Conventional CMOS logic device scaling beyond the 90nm node requires local strain engineering to increase electron and hole mobilities and enhance transistor performance [1-4].
Silicon and WLP enable commercial-grade MEMS resonators
In today’s consumer electronics world, where integrated circuits provide the majority of system functionality, vibrating mechanical devices in the form of quartz crystals are still used as clock sources in most applications.