Table of Contents

Solid State Technology

Year 2007
Issue 1



Value creation while maximizing return on capital

The semiconductor industry represents one of the miracles of the capitalist system, requiring steel-nerved risk-takers.

World News

SIA tweaks down chip sales forecast

The Semiconductor Industry Association (SIA) has slightly tweaked its outlook for chip sales for the next several years, with growth through 2008 slightly less than what was projected in June.

Tech News

Integrating photonics: Hitachi, Oki put LEDs on silicon

Hitachi Ltd.’s central research laboratory reports making a light-emitting diode (LED) from ultrathin silicon thin film with conventional CMOS technology, a step toward potentially putting high-speed optical connections on conventional low-cost silicon devices, without the issues of integrating compound semiconductor materials with standard silicon.


Cost, production, and logistics implications of C4NP solder bumping

The newest generation of bumping technology, called Controlled Collapse Chip Connection: New Process (C4NP), works with lead-free solder alloys.

Asia Pacific

A healthy appetite for chips drives Korea’s rapid growth

South Korea’s global leadership in semiconductor manufacturing is on the rise.

Product News

CVD processing platform

The Producer GT offers 150 wafers/hour throughput, thanks to a FX robot allowing simultaneous transfer of four wafers and a three-“Twin Chamber” configuration.

Industry Forum

Assessing the need for FC abatement standards

Without a script, the semiconductor industry nonetheless appears well along the way toward a voluntary goal of the World Semiconductor Council (WSC) to limit atmospheric emissions of gaseous fluorinated compounds (FCs).



Native oxide removal for NiSi formation using remote plasma preclean

In situ NF3/NH3 remote plasma preclean enables NiSi integration in SOC devices. This new preclean technology allows reliable, production-worthy integration of NiSi for CMOS technology without plasma damage or queue-time control problems.

Next Generation Processe

Driving yield learning with advanced scan-based fault isolation

As the number of transistors and metal layers increase, traditional fault isolation techniques are less successful at isolating causes of failures.

Automation Robotics

Improving fab productivity with new standards for equipment data acquisition

Deploying the set of new SEMI standards encompassing equipment data acquisition (EDA) enables the customization of requests by engineers and other fab personnel for equipment data.


Developing a consensus-based plan for the next wafer size transition

As part of the plan for a next wafer size transition, International Sematech Manufacturing Initiative (ISMI) is developing a strategy for steering design evolution in 300mm-as a precursor to scaling up to 450mm-including the timing and risks associated with design changes needed for next wafer size manufacturing insertion.

Fab Management

Boosting production output by outsourcing CMP

Outsourcing the chemical mechanical planarization (CMP) process module has been successfully implemented to boost production output from an existing wafer fab.