Table of Contents

Solid State Technology

Year 2003
Issue 6


Data Bank

Data Bank

Global semiconductor sales reached $12.1 billion in March 2003, a 2.6 percent increase from the $11.8 billion in revenue reported in February 2003.

Industry Voices

Development Packaging Solutions: Flip Chip and Beyond

In times of reduced research and development (R&D) budgets and a slump in venture financing, time- and cost-efficient execution of the new product development often is a matter of survival. Yet, few developments follow a straightforward path, and this can be particularly true for products requiring advanced packaging.

New Products

New Products


In the News

Packaging Trends

Mapping and Traceability Minimize Recall Costs

Manufacturing industry's pressing need for open systems standards for traceability is motivating new developments in standards for test assembly and packaging.


Alphabet Soup

There are some things that this industry really needs, such as a solid dictionary to sort out the various elements of alphabet soup and to standardize the language of the field engineer.


Flip Chip Pbgas.html

Flip Chip PBGAs

Flip chip packaging has seen explosive growth in recent years, with more and more high-performance devices being designed in flip chip technology. Additionally, flip-chip-in-package (FCIP) is increasingly seen as a solution for higher I/O devices.

The Back End Process

Underfill Techniques: Automated Dispensing and Jetting

Devices that use underfill have proliferated both in package type and volume. The need for underfilling a wide variety of packages for reliability is well established.

Hygroscopic Swelling Of

Hygroscopic Swelling of Encapsulated Microcircuits

The hygroscopic swelling of five commercially available mold compounds is analyzed and the coefficient of hygroscopic swelling is determined for each mold compound using moiré interferometry. The results indicate that the deformation caused by hygroscopic swelling can be as significant as the deformation caused by a thermal expansion of 90°C.

Board Level Reliability

Board-level Reliability Design

A chip scale package (CSP) is defined as any IC package with an area less than 1.5x in die area, a package width less than 1.2x in die width, or any fine-pitch (0.5 mm or less) area-array package.