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Solid State Technology
Intellectual Property (IP) Management in Electronic Design
Typically, when we hear the phrase intellectual property, we immediately think about theft and protection.
Trends that Presaged These Uncertain Times
Any writer of current trends wants to be up-to-date. Normally I could write this piece and expect that by the time it was published, it still had some relevancy.
In The News
IMEC Research Energetically Stacks Up
LEUVEN, Belgium–IMEC remains on the forefront of research in many areas including nanotechnology, RF MEMS packaging, flip chip, substrates, organic electronics, CMOS-based research, solar cells, and 3D stacked integrated circuits.
It takes a while for changes in technology to affect the standard business measurements of success, and many decisive steps are taken before the rewards are apparent.
Notes from SEMICON Europa and IMAPS International
What SEMICON Europa 2008 lacked in size, it made up for in content. Exhibitor numbers were down, due in part to the absence of the PV portion, which will be merged with next June’s Intersolar show in Munich.
The Back End Process
Improved Flip Chip Probing
Clean the wafer not the probe card
Collective Hybrid Bondin
Collective Hybrid Bonding for 3D IC Stacks
The 3D stacked IC (3D-IC) approach calls for a combination of standard single damascene techniques, extreme wafer thinning, and direct Cu-Cu thermo-compression bonding.
Reducing Costs For Tsv M
Reducing Costs for TSV Manufacturing
Through silicon vias (TSVs) are a key component in 3D integration technology. TSV’s improve electrical performance, reduce power consumption, shrink device sizes, and potentially lower costs.
Design Considerations Fo
Design Considerations for Package on Package Underfill
Package-on-package (PoP) is a recognized technology that is becoming more commonplace in mobile electronics with the increased demand for features like cameras, Bluetooth, FM radio, WLAN and mobile TVs.