Table of Contents

Solid State Technology

Year 2008
Issue 10


Editorial Board

Embedded Passives in Device Packaging: What is Limiting Widespread Adoption?

The expectation that embedded passives technology would be required to meet size, performance, and cost requirements of devices has been a driver of considerable R&D activity in laboratories of many material suppliers.

New Products

Wafer Bonder for CMOS Image Sensors

In response to market needs For 300mm process equipment capabilities to demonstrate 3D processes, SUSS MicroTec has introduced The XBC300.

Packaging Trends

fcPiP: The Marriage of Flip Chip and Wire Bond

Cellular handsets and mobile handheld products are defining a new application space that goes beyond the realm of traditional flip chip and 3D packaging.

In The News

EMC3D Consortium Achieves Cost Goal for TSV

SANTA CLARA, CA — Two years ago, the EMC3D Consortium, an open consortia of equipment and materials manufacturers, established itself and set out to develop a process flow and cost model for 3D integration.


A Celebration of Packaging

A packaging engineer living in this Information Age has an obligation to keep on top of everything that’s happening.

Advanced Packaging Road

From End to End

In semiconductor manufacturing, there’s a lot of talk about ends. First, there’s the front-end and the back-end.


The Back End Process

Adhesion Enhancement for Improved MSL

With the development of environmentally friendly ICs at reduced thickness, the manufacturing of thermally reliable products becomes more demanding.

Mastering Material Sets.

Mastering Material Sets

Simple Testing to Evaluate Ball Attach Fluxes.

Laminated Housing Techno

Laminated Housing Technology

Traditional socket manufacturing methods are limited in the ability to meet contact methods of the test socket market, especially those related to semiconductor packages.

The Great Debate Copper

The Great Debate: Copper vs. Gold Ball Bonding

The increased price of gold is making gold ball bonding, a mainstay process in package assembly, cost prohibitive.

How 3d Is Stacking

How 3D is Stacking Up

While moving towards tomorrow’s high-performance 3D packages with through-silicon vias (TSV) has captured most of the attention in the industry, stacked packages and similar established approaches have many 3D advantages and are making substantial, if quieter, technical and market progress.