Lithography

LITHOGRAPHY ARTICLES



Ultratech and Qoniac jointly develop 3D lithography APC solution

01/28/2016  Ultratech, Inc. and Qoniac GmbH announced that the companies are jointly developing a 3D lithography advanced process control (APC) solution for advanced 3D CMOS manufacturing.

Memristor Variants and Models from Knowm

01/22/2016  Knowm Inc., a start-up pioneering next-generation advanced computing architectures and technology, recently announced the availability of two new variations of memristors targeting different neuromorphic applications.

AMD Net Loss Widens in 2015 on Lower Revenue

01/20/2016  Advanced Micro Devices on Tuesday reported a net loss of $660 million on revenue of $3.99 billion for 2015, compared with a net loss of $403 million on revenue of $5.51 billion in 2014.

ASML Has Record Revenue for 2015; Will Raise Dividend, Buy Back More Stock

01/20/2016  ASML Holding today reported net income of about $1.5 billion on revenue of $6.855 billion for 2015. That compared with 2014’s net income of $1.3 billion on revenue of $6.385 billion.

Engineers invent a bubble-pen to write with nanoparticles

01/14/2016  Researchers at the Cockrell School of Engineering at The University of Texas at Austin have developed a device and technique, called bubble-pen lithography, that can gently and effectively handle nanoparticles.

Semiconductor capital spending to decline 4.7% in 2016, according to Gartner

01/12/2016  Worldwide semiconductor capital spending is projected to decline 4.7 percent in 2016, to $59.4 billion, according to Gartner, Inc.

Stanford researchers advance area selective ALD to develop more energy efficient electronics

01/12/2016  Stanford University researchers sponsored by Semiconductor Research Corporation (SRC) have developed a new area selective atomic layer deposition (ALD) process that promises to accelerate the manufacturing of higher performing, more energy efficient semiconductors.

Semiconductor capital spending market in the US to reach over $31B by 2019

01/11/2016  Technavio's market research analysts estimate the semiconductor capital spending market in the US, to grow at a CAGR of around 9% between 2015 and 2019.

Collaboration is the centerpiece to push the limits of lithography

01/11/2016  The continuation of Moore’s Law requires a combination of both physical and functional scaling, where our main challenge in lithography is to continue pushing the physical scaling limits in a controlled and cost-effective way.

A wild ride in 2015 - and two steps forward in 2016

01/07/2016  “In like a lion, out like a lamb” is just half the story for 2015. While initial expectations forecasted a double-digit growth year, the world economy faded and dragged our industry down to nearly flat 2015/2014 results.

EUV, multiple patterning, integrated circuits among topics for SPIE Advanced Lithography 2016

01/06/2016  EUV lithography is on the threshold of becoming a mainstream patterning technology for sub-10nm chips, featured speaker Anthony Yen of Taiwan Semiconductor Manufacturing Co. (TSMC) will tell fellow attendees at SPIE Advanced Lithography 2016.

Micron announces resignation of President Mark Adams

01/04/2016  Micron Technology, Inc. today announced that President Mark Adams will resign for personal health reasons.

Startup Works on Ultralow-k Materials for Chips, Displays

12/21/2015  The very last presentation at the 12th annual 3D Advanced Semiconductor Integration and Packaging conference was given by Hash Pakbaz, president and chief executive officer of SBA Materials, a developer of nanoporous and mesoporous materials for semiconductor manufacturing and other applications.

3D ASIP Conference Hears from EDA, IC Gear Companies

12/18/2015  John Ferguson of Mentor Graphics provided the electronic design automation perspective on packaging technology at the 12th annual 3D ASIP conference in Redwood City, Calif.

SEMI applauds congressional action to make R&D tax credit permanent; extend solar tax credit

12/18/2015  SEMI has been working to make the popular tax incentive a permanent part of the tax code since the R&D credit was first established in 1981.

North American semiconductor equipment industry posts November 2015 book-to-bill ratio of 0.96

12/18/2015  North America-based manufacturers of semiconductor equipment posted $1.24 billion in orders worldwide in November 2015 (three-month average basis) and a book-to-bill ratio of 0.96.

Packaging Conference Addresses Challenges, Opportunities in New Technologies

12/18/2015  On the second day of the 12th annual 3D ASIP conference, the heavy hitters came out to talk. Attendees heard presentations from executives of Amkor Technology, the Defense Advanced Research Projects Agency (DARPA), Northrop Grumman, Taiwan Semiconductor Manufacturing, Teledyne Scientific & Imaging, and Xilinx, among other companies.

Conference Features "The Year of Stacked Memory" in 2015

12/17/2015  The theme of this year's 3D Architectures for Semiconductor Integration and Packading (3D ASIP) conference is "The Year of Stacked Memory," noting how memory die stacked in one package are becoming more commonplace in 2015.

2016 bounce to modest gains

12/14/2015  After deflated 2015, 3D leads the way.

TSMC applies for 12-inch wafer fab and design service center in China

12/11/2015  TSMC this week submitted an application to the Investment Commission of Taiwan's Ministry of Economic Affairs for an investment project to build a wholly-owned 12-inch wafer manufacturing facility and a design service center in Nanjing, China.




TWITTER


WEBCASTS



Advanced Packaging: A Changing Landscape Rife with Opportunities

May 10, 2016 at 1 PM ET / Sponsored by Brewer Science

Die stacking enables better chip performance in a small form factor, meeting the needs of smartphones, tablets, and other advanced devices. Through-silicon vias are moving into volume packaging production, but problems with reliability, cost, and scaling remain. The supply chain also must adjust to this “mid” step between front- and back-end chip production. This webcast will explore the wafer thinning, bonding, TSV formation and other critical process steps necessary to enable 3D integration.

Sponsored By:
Trends in MEMS

May 11, 2016 at 12 PM ET / Sponsored by Boston Semi Equipment

MEMS have quite different process and material requirements compared to mainstream microprocessor and memory types of devices. This webcast will explore the latest trends in MEMS devices – including sensor fusion, biosensors, energy harvesting – new manufacturing challenges and potential equipment and materials solutions to those challenges.

Sponsored By:
Fan-Out Wafer Level Packaging

May 2016 (Date and time TBD) / Sponsored by Zeta Instruments

Wafer level packaging (WLP) using fan-out technology is an attractive platform for achieving low-cost low-profile package solutions for smart-phones and tablets, which require cost-effective, high-density interconnects in small form-factor packaging. Assembled directly on a silicon wafer, the approach is unconstrained by die size, providing the design flexibility to accommodate an unlimited number of interconnects between the package and the application board for maximum connection density, finer line/spacing, improved electrical and thermal performance and small package dimensions to meet the relentless form factor requirements and performance demands of the mobile market. In this webcast, industry experts will explain the FOWLP process, discuss recent advances and forecast future trends.

Sponsored By:
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TECHNOLOGY PAPERS



Protecting Electronics with Parylene

This whitepaper provides a comprehensive overview of parylene conformal coating, advantages of parylene, and applications for parylene to protect electronic devices. As technology continues to advance, devices will encounter rugged environments and it is vital that they are properly protected. Parylene conformal coating is one way that manufacturers are giving their devices a higher level of protection, along with increasing the overall quality of their products. Parylene conformal coating applications for Electronics include: · I/O & PCI Modules · Power Converters and Supplies · Backplanes · Other Embedded Computing applications · Other specialty electronics and assemblies April 26, 2016
Sponsored by Diamond-MT

NMT: A Novel Technology for In-Line Ultra-Thin Film Measurements

XwinSys identified the semiconductors recent market trends and developed a novel XRF technology, named NMT: Noise-reduced Multilayer Thin-film measurement. This innovative approach can be used for in-line inspection and metrology features, to accurately and precisely analyze single and multi-layered elements in ultra-thin films. NMT novel technology can be utilized for in-line applications ranging from localized ultra-thin film stacks to the inspection of 3D localized features to the analysis of defects involving geometries, voids and material elements. February 23, 2016
Sponsored by XwinSys Technology Development Ltd.

Adhesives for Electronic Applications

Master Bond custom formulates epoxy adhesives, sealants, coatings, potting and encapsulation compounds to meet the rigorous needs of the electronic industry. We are a leading manufacturer of conformal coatings, glob tops, flip chip underfills, and die attach for printed circuit boards, semiconductors, microelectronics, and more. Browse our catalog to find out more.January 05, 2016
Sponsored by Master Bond, Inc.,

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EVENTS



SID Display Week 2016
San Francisco, CA
http://www.displayweek.org
May 22, 2016 - May 27, 2016
Design Automation Conference
Austin, TX
https://dac.com
June 05, 2016 - June 09, 2016
The ConFab
Las Vegas, NV
http://theconfab.com
June 12, 2016 - July 15, 2016
SEMICON West 2016
San Francisco, CA
http://www.semiconwest.org
July 12, 2016 - July 14, 2016

VIDEOS