Materials and Equipment

MATERIALS AND EQUIPMENT ARTICLES



Imec presents back-side illuminated CMOS image sensor with UV-optimized antireflective coating

11/04/2014  At this week’s VISION 2014 exhibition, imec presents a backside-illuminated (BSI) CMOS image sensor chip featuring a new anti-reflective coating (ARC) optimized for UV light.

Experts at the Table: Focus on Semiconductor Materials

11/03/2014  The cutting edge in semiconductor manufacturing has meant not only big changes in IC design and process technology, but also in semiconductor materials. Experts weigh in from Linde Electronics; Kate Wilson of Edwards Vacuum; David Thompson of Applied Materials; and Ed Shober of Air Products and Chemicals.

Air-gaps in Copper Interconnects for Logic

10/31/2014  Intel’s “14nm-node” process uses air-gaps in dielectrics; direction disclosed four years ago.

MegaChips to acquire SiTime for $200M

10/29/2014  SiTime Corporation, a MEMS and analog semiconductor company, today announced that it has signed a definitive agreement under which MegaChips Corporation, a top 25 fabless semiconductor company based in Japan, will acquire SiTime for $200 million in cash.

Element Six introduces new thermal grade of CVD diamond

10/15/2014  Element Six this week announced the development of a new thermal grade of diamond grown by chemical vapor deposition (CVD), DIAFILM TM130.

IRLYNX and CEA-Leti to streamline new CMOS-based infrared sensing modules

10/15/2014  IRLYNX and CEA-Leti today announced they have launched a technology-development partnership for a new CMOS-based infrared technology that will allow a new type of smart and connected detectors in buildings and cities.

Texas Instruments announces 22B copper wire bond technology units shipped

10/14/2014  Texas Instruments today announced it has shipped more than 22 billion units of copper wire bonding technology from its internal assembly sites and is now in production for major high reliability applications including automotive and industrial.

Deeper Dive -- Mentor Graphics Looks to the Future

10/14/2014  There has been a great deal of handwringing and naysaying about the industry’s progress to the 14/16-nanometer process node, along with wailing and gnashing of teeth about the slow progress of extreme-ultraviolet lithography, which was supposed to ease the production of 14nm or 16nm chips. Joseph Sawicki, vice president and general manager of Mentor’s Design-to-Silicon Division, is having none of it.

Threshold voltage tuning for 10nm and beyond CMOS integration

10/13/2014  A novel metal gate integration scheme to achieve precise threshold voltage (VT) control for multiple VTs is described.

ARM and TSMC unveil roadmap for 64-bit ARM-based processors on 10FinFET process technology

10/02/2014  ARM and TSMC today announced a new multi-year agreement that will deliver ARMv8-A processor IP optimized for TSMC 10FinFET process technology.

Boston Semi Equipment creates industry's largest independent ATE organization

10/01/2014  Boston Semi Equipment LLC (BSE) today announced it has combined all of its automated test equipment (ATE) businesses under the Boston Semi Equipment brand name.

SPIE Photomask Technology Wrap-up

09/23/2014  Extreme-ultraviolet lithography was a leading topic at the SPIE Photomask Technology conference and exhibition, held September 16-17-18 in Monterey, Calif., yet it wasn’t the only topic discussed and examined. Mask patterning, materials and process, metrology, and simulation, optical proximity correction (OPC), and mask data preparation were extensively covered in conference sessions and poster presentations.

SPIE panel tackles mask complexity issues

09/19/2014  Photomasks that take two-and-a-half days to write. Mask data preparation that enters into Big Data territory. And what happens when extreme-ultraviolet lithography really, truly arrives?

Rudolph introduces new acoustic metrology and defect inspection technology

09/18/2014  Rudolph Technologies has introduced its new SONUS Technology for measuring thick films and film stacks used in copper pillar bumps and for detecting defects, such as voids, in through silicon vias (TSVs).

Oxford Instruments launches 3rd annual Indian nanotechnology seminars in Kolkata and Delhi

09/18/2014  Oxford Instruments is hosting its third series of annual seminars for the nanotechnology industry in India in November.

ASML on EUV: Available at 10nm

09/17/2014  Extreme-ultraviolet lithography systems will be available to pattern critical layers of semiconductors at the 10-nanometer process node, and EUV will completely take over from 193nm immersion lithography equipment at 7nm, according to Martin van den Brink, president and chief technology officer of ASML Holding.

Design and Manufacturing Technology Development in Future IC Foundries

09/16/2014  Virtual Roundtable provides perspective on the need for greater integration within the “fabless-foundry” ecosystem.

Monolithic 3D breakthrough at IEEE S3S 2014

09/15/2014  In the upcoming 2014 IEEE S3S conference (October 6-9), MonolithIC 3D will unveil a breakthrough flow that is game-changing for 3D IC. For the first time ever monolithic 3D (“M3DI”) could be built using the existing fab and the existing transistor flow.

Process Watch: Sampling matters

09/15/2014  Determining an optimum sampling strategy comes down to weighing the cost of process control against the benefit of capturing the defect or other excursion in a timely manner.

Foundry, EDA partnership eases move to advanced process nodes

09/15/2014  A leading semiconductor foundry and an EDA vendor with design-for-yield (DFY) solutions have enjoyed a long-term partnership. Recently, they worked together to leverage DFY technologies for process technology development and design flow enhancement.




HEADLINES

FINANCIALS



TECHNOLOGY PAPERS



ASIC Design Made Cost Effective with Low Cost Tools and Masks

For smaller projects or companies with modest design budgets, ASIC design is becoming a viable option due to low cost design tools and easy access to flexible, mature IC processes. This is especially compelling for developing mixed-signal ASICs for cost-sensitive sensor applications for the Internet of things (IoT). This paper discusses how costs and risks can be reduced using multi-project wafer services, coupled with affordable design tools for developing mixed-signal ASICs. April 13, 2015
Sponsored by Mentor Graphics

High-Performance Analog and RF Circuit Simulation

The research group led by Professor Peter Kinget at the Columbia University Integrated Systems Laboratory (CISL) focuses on cutting edge analog and RF circuit design using digital nanoscale CMOS processes. Key challenges in the design of these circuits include block-level characterization and full-circuit verification. This paper highlights these verification challenges by discussing the results of a 2.2 GHz PLL LC-VCO, a 12-bit pipeline ADC, and an ultra-wideband transceiver.March 13, 2015
Sponsored by Mentor Graphics

How to Use Imaging Colorimeters for FPD Automated Visual Inspection

The use of imaging colorimeter systems and analytical software to assess display brightness and color uniformity, contrast, and to identify defects in FPDs is well established. A fundamental difference between imaging colorimetry and traditional machine vision is imaging colorimetry's accuracy in matching human visual perception for light and color uniformity. This white paper describes how imaging colorimetry can be used in a fully-automated testing system to identify and quantify defects in high-speed, high-volume production environments.February 27, 2015
Sponsored by Radiant Vision Systems

More Technology Papers

WEBCASTS



3D Integration: The Most Effective Path for Future IC Scaling

Thursday, April 23, 2015 at 12:00 p.m. EST

It is well recognized that dimensional scaling has reached its diminishing return phase. The industry is now looking at monolithic 3D to be the future technology driver. Yet, until recently, the path to monolithic 3D has required the development of new transistor types and processes. This Webcast will present game-changing monolithic 3D process flows which use the existing transistor of existing manufacturing line and existing process flows. Now the most effective path for future IC scaling is indeed monolithic 3D, which offers the lowest development and manufacturing cost for future ICs.

Sponsored By:
Trends in Materials: The Smartphone Driver

Thursday, April 30, 2015 at 1:00 p.m. EST

To understand 3-D FinFET doping and high mobility channel material, this talk will first review the current doping and Fin/channel mobility enhancement techniques used for 22nm FinFET production by Intel for both high performance logic and SOC devices and the changes they made for their 2nd generation 14nm FinFET.

Sponsored By:
MEMS

May 2015 (Date and time TBD)

MEMS have quite different process and material requirements compared to mainstream microprocessor and memory types of devices. This webcast will explore the latest trends in MEMS devices – including sensor fusion, biosensors, energy harvesting – new manufacturing challenges and potential equipment and materials solutions to those challenges.

Sponsored By:
More Webcasts

VIDEOS



EVENTS



SEMICON Southeast Asia 2015
Penang, Malaysia
http://www.semiconsea.org
April 22, 2015 - April 24, 2015
ASMC 2015
Saratoga Springs, NY
http://www.semi.org/en/asmc2015
May 03, 2015 - May 06, 2015
The ConFab
Las Vegas, Nevada
http://www.theconfab.com
May 19, 2015 - May 22, 2015
65th Annual ECTC
San Diego, CA
http://www.ectc.net
May 26, 2015 - May 29, 2015
SID Display Week 2015
San Jose, California
http://www.displayweek.org
May 31, 2015 - June 05, 2015