Metrology

METROLOGY ARTICLES



Altera CEO John Daane to receive Robert N. Noyce Award

10/08/2014  The Semiconductor Industry Association announced that John P. Daane, President, CEO, and Chairman of the Board of Altera, has been named the 2014 recipient of SIA's highest honor, the Robert N. Noyce Award.

Boston Semi Equipment creates industry's largest independent ATE organization

10/01/2014  Boston Semi Equipment LLC (BSE) today announced it has combined all of its automated test equipment (ATE) businesses under the Boston Semi Equipment brand name.

Kurita, SEMATECH partner on wafer surface contamination and cleaning technology in semiconductor processing

09/30/2014  SEMATECH, the global consortium of chipmakers, announced today that Kurita Water Industries Limited has partnered with SEMATECH to develop innovative technologies for low defectivity ultrapure water (UPW) applications used in semiconductor manufacturing.

SPIE Photomask Technology Wrap-up

09/23/2014  Extreme-ultraviolet lithography was a leading topic at the SPIE Photomask Technology conference and exhibition, held September 16-17-18 in Monterey, Calif., yet it wasn’t the only topic discussed and examined. Mask patterning, materials and process, metrology, and simulation, optical proximity correction (OPC), and mask data preparation were extensively covered in conference sessions and poster presentations.

SPIE panel tackles mask complexity issues

09/19/2014  Photomasks that take two-and-a-half days to write. Mask data preparation that enters into Big Data territory. And what happens when extreme-ultraviolet lithography really, truly arrives?

Rudolph introduces new acoustic metrology and defect inspection technology

09/18/2014  Rudolph Technologies has introduced its new SONUS Technology for measuring thick films and film stacks used in copper pillar bumps and for detecting defects, such as voids, in through silicon vias (TSVs).

ASML on EUV: Available at 10nm

09/17/2014  Extreme-ultraviolet lithography systems will be available to pattern critical layers of semiconductors at the 10-nanometer process node, and EUV will completely take over from 193nm immersion lithography equipment at 7nm, according to Martin van den Brink, president and chief technology officer of ASML Holding.

Design and Manufacturing Technology Development in Future IC Foundries

09/16/2014  Virtual Roundtable provides perspective on the need for greater integration within the “fabless-foundry” ecosystem.

Monolithic 3D breakthrough at IEEE S3S 2014

09/15/2014  In the upcoming 2014 IEEE S3S conference (October 6-9), MonolithIC 3D will unveil a breakthrough flow that is game-changing for 3D IC. For the first time ever monolithic 3D (“M3DI”) could be built using the existing fab and the existing transistor flow.

Process Watch: Sampling matters

09/15/2014  Determining an optimum sampling strategy comes down to weighing the cost of process control against the benefit of capturing the defect or other excursion in a timely manner.

Foundry, EDA partnership eases move to advanced process nodes

09/15/2014  A leading semiconductor foundry and an EDA vendor with design-for-yield (DFY) solutions have enjoyed a long-term partnership. Recently, they worked together to leverage DFY technologies for process technology development and design flow enhancement.

SEMI advocates for the industry in Washington

09/10/2014  With changes coming in Washington, SEMI has important work ahead supporting the innovators and job creators of this country.

Research Alert: September 9, 2014

09/09/2014  GLOBALFOUNDRIES and SRC announce new scholarship for undergraduate engineering students; Layered graphene sandwich for next generation electronics; Doped graphene nanoribbons with potential

SEMI wins request for etch equipment export control review

09/09/2014  Major milestone in longstanding push to remove etch equipment from U.S. export control list.

Gas applications in lithography

09/08/2014  Lithography is a key enabling process with very demanding requirements. Shrinking feature sizes will raise the bar even further.

The Week in Review: September 5, 2014

09/05/2014  New non-volatile memory technology; President and CEO of FSA announced; Samsung to use ProPlus 14nm finFET SPICE modeling platform; MEMS gyroscope from Analog Devices; SEMICON Taiwan held this week

GLOBALFOUNDRIES adds Louis Lupin as Chief Legal Officer

09/04/2014  GLOBALFOUNDRIES, a provider of advanced semiconductor manufacturing technology, announced today that Louis “Lou” Lupin has joined the company as senior vice president and chief legal officer.

Research Alert: September 3, 2014

09/03/2014  A new, tunable device for spintronics; Copper shines as flexible conductor; Competition for graphene

Intel Announces “New Interconnect” for 14nm

09/02/2014  Intel has just announced that “Embedded Multi-die Interconnect Bridge (EMIB”) packaging technology will be available to 14nm foundry customers.

The Week in Review: August 29, 2014

08/29/2014  Intel releases new packaging technologies; Fairchild Semiconductor to close two facilities; KLA-Tencor introduces new metrology tools; UMC joins Fujitsu's new foundry company; Thinnest-possible semiconductor; SEMI announces keynotes for Vietnam Semiconductor Strategy Summit




HEADLINES

FINANCIALS



TECHNOLOGY PAPERS



ASIC Design Made Cost Effective with Low Cost Tools and Masks

For smaller projects or companies with modest design budgets, ASIC design is becoming a viable option due to low cost design tools and easy access to flexible, mature IC processes. This is especially compelling for developing mixed-signal ASICs for cost-sensitive sensor applications for the Internet of things (IoT). This paper discusses how costs and risks can be reduced using multi-project wafer services, coupled with affordable design tools for developing mixed-signal ASICs. April 13, 2015
Sponsored by Mentor Graphics

High-Performance Analog and RF Circuit Simulation

The research group led by Professor Peter Kinget at the Columbia University Integrated Systems Laboratory (CISL) focuses on cutting edge analog and RF circuit design using digital nanoscale CMOS processes. Key challenges in the design of these circuits include block-level characterization and full-circuit verification. This paper highlights these verification challenges by discussing the results of a 2.2 GHz PLL LC-VCO, a 12-bit pipeline ADC, and an ultra-wideband transceiver.March 13, 2015
Sponsored by Mentor Graphics

How to Use Imaging Colorimeters for FPD Automated Visual Inspection

The use of imaging colorimeter systems and analytical software to assess display brightness and color uniformity, contrast, and to identify defects in FPDs is well established. A fundamental difference between imaging colorimetry and traditional machine vision is imaging colorimetry's accuracy in matching human visual perception for light and color uniformity. This white paper describes how imaging colorimetry can be used in a fully-automated testing system to identify and quantify defects in high-speed, high-volume production environments.February 27, 2015
Sponsored by Radiant Vision Systems

More Technology Papers

WEBCASTS



Trends in Materials: The Smartphone Driver

Thursday, April 30, 2015 at 1:00 p.m. EST

To understand 3-D FinFET doping and high mobility channel material, this talk will first review the current doping and Fin/channel mobility enhancement techniques used for 22nm FinFET production by Intel for both high performance logic and SOC devices and the changes they made for their 2nd generation 14nm FinFET.

Sponsored By:
MEMS

May 2015 (Date and time TBD)

MEMS have quite different process and material requirements compared to mainstream microprocessor and memory types of devices. This webcast will explore the latest trends in MEMS devices – including sensor fusion, biosensors, energy harvesting – new manufacturing challenges and potential equipment and materials solutions to those challenges.

Sponsored By:
Interconnects

June 2015 (Date and time TBD)

This webcast will examine the state-of-the-art in conductors and dielectrics, -- including contacts and Metal1 through global level -- pre-metal dielectrics, associated planarization, necessary etch, strip and cleans, embedded passives, global and intermediate TSVs for 3D, as well as reliability, system, and performance issues.

Sponsored By:
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VIDEOS



EVENTS



ASMC 2015
Saratoga Springs, NY
http://www.semi.org/en/asmc2015
May 03, 2015 - May 06, 2015
The ConFab
Las Vegas, Nevada
http://www.theconfab.com
May 19, 2015 - May 22, 2015
65th Annual ECTC
San Diego, CA
http://www.ectc.net
May 26, 2015 - May 29, 2015
SID Display Week 2015
San Jose, California
http://www.displayweek.org
May 31, 2015 - June 05, 2015
Design Automation Conference (DAC)
San Francisco, CA
https://dac.com
June 07, 2015 - June 11, 2015