Silicon wafer revenues decline in 2012
February 12, 2013
Worldwide silicon wafer revenues declined by 12 percent in 2012 compared to 2011, according to the SEMI Silicon Manufacturers Group (SMG) in its year-end analysis of the silicon wafer industry.
imec advances CMOS beyond silicon to Ge, III-V
December 14, 2011
Marc Heyns, fellow at research consortium imec, discusses the group's work on chip fab materials beyond silicon, namely, Ge and III-V, presented in "Advancing CMOS beyond the silicon roadmap with germanium and III-V devices" at IEDM.
September 2014 (date and time TBD)
Continued scaling and more complex device structures, including FinFETs and 3D stacking, are creating new challenges in metrology and inspection. Smaller defects must be detected and analyzed on an increasingly diverse set of materials. Chip makers are looking for better wafer edge inspection techniques, higher resolution metrology tools, 450mm-capability and new compositional analysis solutions.
Sept. 2014 (Date and time TBD)
Back-end packaging is increasingly important to semiconductor device form factor, thermal and power performance, and costs. Compounded by the demand for lead-free processing and the soaring cost of gold, the industry is developing new approaches to packaging, including redistribution layers (RDL), through silicon vias (TSV), copper pillars, wafer-level packaging (WLP) and copper wire bonding. Experts will discuss these and other approaches in this webcast.
Oct. 2014 (Date and time TBD)
This webcast will examine the state-of-the-art in conductors and dielectrics, -- including contacts and Metal1 through global level -- pre-metal dielectrics, associated planarization, necessary etch, strip and cleans, embedded passives, global and intermediate TSVs for 3D, as well as reliability, system, and performance issues.