Edwards Brings the Future of Sub-Fab Technology to SEMICON Europa 2014

Edwards Limited will offer presentations on emerging sub-fab technologies at SEMICON Europa, taking place 7-9 October 2014, in Grenoble, France.

Edwards’ Mike Czerniak, Product Marketing Manager for Exhaust Gas Management, will present a paper titled, “450mm Innovations and Synergies for Smaller Diameters,” that will review the implications of new processes for exhaust gas treatment and the options for managing these challenges.

Steve Cottle, Senior Product Manager for Edwards’ Integrated Systems, will present at the Tech Arena on “Integrated Sub-fab Equipment Solutions – the Key to Manufacturing Peace of Mind.” Cottle will describe how integrated sub-fab exhaust management solutions enhance process operation and reduce total cost-of-ownership in high-volume manufacturing.

“Cost-effective, high-volume manufacturing of 450mm wafers, and 10- to 7-nm devices, will introduce new materials and processes, creating new challenges for our customers. Over the many years that we have participated in the semiconductor industry, we have acquired a solid understanding of manufacturing processes and the sub-fab best practices required to support them. We leverage that knowledge every day as we work to develop innovative solutions to address the next round of challenges. These papers and presentations will provide insight to some of the newest solutions that our R&D engineers have been working on,” states Ralph Loske, Edwards’ European Sales Director.

KLA-Tencor Evolves Inspection and Review Portfolio for 3D Future

By Ed Korczynski, Contributing Editor 

This week at SEMICON West, KLA-Tencor Corporation announced updates to four systems—the 2920 Series, Puma 9850, Surfscan SP5 and eDR-7110—intended for defect inspection and review of 16/14nm node and below IC devices in both development and production.

KLAT_July2014_InspectReviewUpdates_Fig1[1]

The 2920 Series broadband plasma patterned wafer, Puma 9850 laser scanning patterned wafer, and Surfscan SP5 unpatterned wafer defect inspection systems deliver enhanced sensitivity and significant throughput gains. By enabling discovery and monitoring of yield-critical defects, these inspectors support chipmakers’ integration of complex structures, novel materials and new processes at leading-edge design nodes. Each of the inspection systems seamlessly connects with the eDR-7110 electron-beam review system, which uses improved automatic defect classification (ADC), providing chipmakers with accurate information to improve manufacturing yield of the most advanced commercial ICs.

Process control of advanced IC manufacturing can only occur with pragmatic use of metrology and inspection, since ‘you can’t build it if you can’t see it.’ In an exclusive interview with The Show Daily, Brian Trafas, KLA-Tencor’s chief marketing officer discussed how industry attitudes toward inspection have changed for the better in recent years, but lingering misunderstandings remain. “Even in the area of adding cycle time, some people have a pretty archaic view that this can increase cycle time,” said Trafas. “But if you don’t monitor you can put an enormous number of lots at risk.”

Multiples of all four systems have been installed at foundry, logic, and memory manufacturers worldwide, where they are being used for development and production at advanced technology nodes. All four systems are expected to be shipping to customers in volume in the second half of this year.

KLAT_July2014_InspectReviewUpdates_Fig2

However, due to industry consolidation, there are perhaps only five organizations remaining that are pushing IC manufacturing down to sub-22nm node technology. Each organization is understandably concerned about information leaking to competitors, and so each organization insists upon extreme confidentiality when evaluating strategic manufacturing technology such as that involved in defect inspection and review. KLA-Tencor has customer-specific modifications to it’s tools, and each customer will build its own database of defect signatures using its own proprietary test structures.

“There are general things that are the same, like if it’s a poly layer it’s best to use a certain wavelength,” elaborated Trafas, “but beyond that the device differences lead each customer to optimize inspection in different ways.”

Broadband Inspection of Patterned Wafers

Broadband inspection of patterned silicon wafers is needed both in R&D and in volume production of advanced ICs. Different wavelengths reflect differently from different thin-film materials, and the ability to capture broadband information thereby proves more valuable as the industry integrates more materials into advanced device structures. For example, advanced on-chip copper interconnects may use cobalt and ruthenium barrier layers.

“Our competitor, Applied Materials, has a single-wavelength laser…but depending upon the material you may get better resolution with a different wavelength,” explained Trafas. “We are the only company providing a broadband source from a plasma, and that’s unique intellectual property from KLA-Tencor that we’re also using on our metrology tools.”

KLA-Tencor began investing in this broadband plasma source technology around 10 years ago, the first-generation was released four years ago with the 2835 tool, and the second-generation was released two years ago with the 2900 tool.

KLAT_July2014_InspectReviewUpdates_Fig3

Using a third-generation broadband plasma illumination source, the 2920 platform delivers twice the light of its predecessor, enabling the use of a new deep ultra violet (DUV) wavelength band and the industry’s smallest optical inspection pixel. Along with new advanced algorithms, these optical modes boost sensitivity to subtle protrusions, tiny bridges and other pattern defects on complex IC device architectures, such as FinFETs. The 2920 tool’s Accu-ray and Flex Aperture technologies combine to provide the best optical settings for capture of critical defect types, significantly reducing the time required to discover and solve process and design issues. The company claims that instead of the days formerly required to establish a new R&D inspection recipe for a new material in a novel device, the new algorithms and recipes allow for setup in just a few hours.

“We’ve pushed the sensitivity of the tool in die-to-die comparison mode to see thousands of signals, but some are spurious so the algorithms are needed to extract new defect types,” elaborated Trafas. “The tool can resolve 10nm defects. This is an optical-based tool, so some people say that even if you’re in the DUV range you can’t resolve 10nm. They’re somewhat correct, but all we’re trying to do is resolve the differences between dice. In some cases we use a contrast mode, where we suppress data from one layer and enhance data from another layer  based on the different frequencies. The result is the best overall sensitivity and the best overall capture rate.”

Laser Inspection of Patterned Wafers

Compared to broadband plasma inspection, laser-based inspection doesn’t see as many defects but is very fast and so can be used for production checks. For example, an integrated patterning process may be controlled by laser-based inspection after each unit-process step—photoresist development, etch, clean—monitoring the same device feature to see how it evolves. With multiple platform enhancements, the Puma 9850 laser scanning patterned wafer defect inspection system provides improved sensitivity across a range of production throughputs to support a diverse array of FinFET and advanced memory inspection applications.

Higher speed modes, operating at up to twice the throughput of the Puma 9650, allow for cost-effective excursion monitoring in the film and chemical-mechanical planarization (CMP) process modules. “As a customer gets into routine production, the Puma can be used to track performance of a particular process step to catch excursions,” explained Trafas. “So heavy use of the 2920 in the beginning of production ramp, heavy use of the Puma in the end of mature manufacturing, and a mix of the two in the middle.”

The Puma 9850’s higher sensitivity operating modes allow for efficient defect capture on after-develop inspection (ADI), photo-cell monitor (PCM), and front-end-of-line line-space etch layers. “The new system has better defect capture, and sometimes at up to 7x better throughput,” claimed Trafas. “With additional capabilities the price of the tool is going up, but we’re off-setting some of that with increased throughput so the overall cost-of-ownership should be the same or possible better.”

Unpatterned wafer inspection

Silicon ICs need pristine silicon or silicon-on-insulator (SOI) starting wafers, and defects in the wafer surface tend to propagate into dis-functional defects in final fabricated devices. The Surfscan line of unpatterned wafer inspectors has now been upgraded with an improved light source and more of those better algorithms. “The SP5 is a critical platform, I can’t emphasize this enough,” emphasized Trafas. “Customers wanted a tool with greater sensitivity to be able to monitor defects in advanced wafer production, such as epi-growth. We have actually had this in the market space at leading companies doing some of that contamination monitoring.”

The Surfscan SP5 unpatterned wafer inspector incorporates enhanced DUV optical technologies that produce sub-20nm defect sensitivity at production throughput, enabling detection of tiny substrate or blanket film defects that can inhibit successful integration of multi-stack IC devices. With throughput up to three times faster than the previous-generation Surfscan SP3, the Surfscan SP5 maintains high productivity while qualifying and monitoring the increased number of process steps associated with multi-patterning and other leading-edge fabrication techniques.

The greater sensitivity of the SP5 compared to the SP3 allows for more defect counts to be captured, but unless those counts are properly accounted for as defect categorizations the process engineers don’t know which actions to take to recover yield. Thus, “mere counting doesn’t count.”

E-beam Defect Review

When all else fails in categorization of a yield loss due to a defect, a wafer is sent to an electron-beam (e-beam) tool for review. The eDR-7110 e-beam review system includes a new SEM Automatic Defect Classification (S-ADC) engine that can produce an accurate representation of the defect population during production, and can also be used during development to reduce the time required for defect discovery.

Moreover, S-ADC results can automatically trigger additional in-line tests, such as compositional analysis or imaging with alternative modes, while the wafer is still on the eDR-7110. Automatic triggering of additional tests is a unique capability of this tool, which enhances the quality of the defect information provided to engineers for process decisions.

“We want to automatically classify that defect,” reminded Trafas. “We made a lot of improvements in the classification algorithms, improved the optics, and improved data-transfer links to eliminate so-called ‘SEM Non-Visuals.’ In some cases we may use the image from an inspector.”

All of these tools combine to create a ‘virtuous circle’ of defect learning. An inspection tool feeds information to an eDR tool, which feeds information to S-ADC for attribute-based classification, which feeds information to manual classification, which ultimately leads to a Pareto chart of defects. Pragmatic evolution of these inspection and review systems enables leading IC fabs to extend manufacturing to sub-22nm nodes.

How to Drive and Motivate Modern-Day Innovation

By Shannon Davis, Web Editor, Solid State Technology

Technology innovation isn’t slowing down. But its steady acceleration isn’t happening spontaneously, and Tuesday’s Silicon Innovation Forum keynote from Professor of Innovation Dr. Bob Metcalfe outline how he believes to effectively drive the complex cycle that is modern-day innovation.

“Change in itself is not improvement – the crux of the matter is in innovation management,” said Dr. Metcalfe. “Ideas are a dime a dozen, and most are bad ideas.”

When it comes to innovating, Dr. Metcalfe has a lengthy resume to prove he knows what he’s talking about: Internet pioneer, inventor of Ethernet, co-founder of 3Com Corporation, publisher-CEO of IDG/Info-World – his credentials are seemingly endless. So, when he began to explain the ecology he believed needed to develop the most effective innovation system, his audience sat up and took notes.

Dr. Metcalfe explained that, in his experience, the most effective, successful innovation ecology is comprised of seven key players: funding agencies, research professors, graduating students, scaling entrepreneurs, venture capitalists, strategic investors, and early adopters. In discussing funding agencies, he also addressed the sometimes-sticky role of research universities in driving innovation.

“Are research universities up to it? Are they up to doing our research for us?” he mused. “They’re not well-managed; they’re heavily governed – we need to keep universities competing with each other and that will improve their management.”

“Universities don’t like it when I say that,” he joked.

Research universities are also up against a new kind of challenge, he pointed out – the growing popularity of online campuses. Dr. Metcalfe said that the affect of this on universities’ abilities to effectively carry out research has yet to be seen, but it certainly something that manufacturers ought to consider when discussing partnerships with research universities in the future.

Dr. Metcalfe also suggested that giving IP to researching professors or students, the true inventors, might provide added incentive for increased participation in research programs at institutions.

So, where will the next great innovation be? Dr. Metcalfe said he, albeit biasedly, supports more innovation in networking, but encouraged the audience to seriously consider pursuing entirely new and crucial forms of innovation, such as making solar energy affordable.

“The world’s most important problems will not be solved by yet another website,” said Dr. Metcalfe. “We need to address how to get this new generation to think about innovating things that matter.”

Dr. Bob Metcalfe at Tuesday's Silicon Innovation Forum keynote at SEMICON West 2014. (Photo provided by SEMI)

Dr. Bob Metcalfe at Tuesday’s Silicon Innovation Forum keynote at SEMICON West 2014. (Photo provided by SEMI)

Vacuum Technologies Needed for 3D Device Processing

By Ed Korczynski, Contributing Editor

Future ICs will use more 3D device structures such as finFETs and gate-all-around (GAA) transistors, and so vacuum deposition processes are needed that can produce conformal films on the tops, bottoms, and side-walls of features. New materials are needed as the commercial IC fabrication industry pushes the limits of device miniaturization, while industry consolidation drives the remaining players to use proprietary materials.

Even lithography needs more vacuum processing when double-, triple-, and quadruple-patterning schemes need sidewall spacer and sacrificial hard-mask depositions. Materials deposited in these process steps may not remain on the final chip, but they are nonetheless essential in sub-22nm node process flows.

All of this leads to a need for an unprecedented number of new chemical precursors for vacuum depositions to be simultaneously ramped into high-volume manufacturing (HVM) in fabs worldwide. “If you’re trying to deposit a metal nitride, for example, four different fabs may use four different precursors sets,” explained Kate Wilson, global applications director, Edwards Vacuum Ltd. in an exclusive interview with the Show Daily.

“With conformal processes, such as those used for finFETs, there are a broad range of processes needed,” continued Wilson. “The solutions are diverging. For example, even if you’re depositing silicon the number of precursors in use has probably tripled in the last three years. We’re getting gas lists from end-users with practically every metal precursor possible, and if we ask which ones will be used we’re told that all of them may be in use.”

Each molecular precursor has unique properties in terms of thermal stability, tendency to polymerize, reactivity with oxygen, toxicity to humans, and tendency to coat different material surfaces. So each molecular precursor calls for different solutions in vacuum processing and effluent abatement. However, the same precursor may be managed slightly differently by different fabs in HVM.

Special Vacuum Challenges with ALD

Atomic Layer Deposition (ALD) can be considered as a special sub-set of chemical vapor deposition (CVD), where the chemical precursors are alternately pulsed into the vacuum chamber. The first ALD gas pulse coats device features with a single layer of molecules, then the second precursor pulse reacts with the molecules to leave behind a single layer of atoms.

ALD precursors are somewhat magical molecules in terms of their properties. They must completely coat the desired wafer surfaces, yet neither decompose nor polymerize before reaching the wafer. They must remain completely stable until reaching the wafer surface, and then completely react to leave behind just the atoms of choice. One common property of the precursors molecules that include the atoms of choice:  to ensure near perfect atomic coverage across 300mm diameter wafers they tend to stick to most other surfaces too.

ALD processing is a broad topic, with known variations for oxides, nitrides, metals, and rare-earth elements. There are also variations between thermally-activated and plasma-enhanced processes, but ALD generally occurs in two different tools types:  tube furnaces for batch processing, and single-wafer chambers. Tube furnace have large internal volumes, and the alternating pulses of precursors occur on a time-scale of minutes such that only one of the two precursors flows through the tool at any given time.

However, single-wafer ALD tools have small internal volumes and precursor pulses occurring on a time-scale of mere seconds, such that the best process results derive from continuous flows of both precursors through the tool. Gas control manifolds are setup using high-speed valves to divert flows to either the vacuum chamber or directly to the exhaust stream. For such processes, half the precursors are shunted past the deposition chamber directly to the exhaust, and the vacuum pump and abatement system must handle not just process effluent but high flows of unreacted precursors that tend to stick to any surface.

“You have to consider dilution levels and side-reactions,” cautioned Wilson. “Working with the OEM and the end-users as they fine-tune these processes is key to success.”

For some ALD process there are conflicting challenges in configuring a vacuum solution, such as one using a MOCVD precursors and a chloride precursor. For the MOCVD molecule the general approach would be to lower temperatures to prevent decomposition, while for the chloride molecule it would be best to use high temperatures to prevent condensation. Some molecules polymerize more at higher temperatures, while condensing more at lower temperatures, so a strategic trade-off must be made.

“Chlorine-based precursors, for example, are quite challenging to abate without creating toxic by-products,” explained Wilson. “Most of the things we abate become a powder, so we have to deal with that powder to ensure that we don’t clog the system.”

When ALD and conformal CVD processes are used to form 3D structures in future sub-22nm node ICs, there will be different thicknesses for the final films and different precursors used in leading HVM lines. Consequently, any standardization in vacuum technology seems impossible, and a lot of customization using proven sub-systems will be essential for each end-user.

Vacuum and abatement customization

Different fabs rely upon different overall vacuum strategies. In some cases there may be a trade-off between capital costs and labor costs. In some situations the solution may require abatement of just perfluorocarbons (PFCs), or may also require the abatement of toxics. From fine-tuning of internal temperatures, to modification of purge cycles, vacuum system suppliers must work closely with OEMs and end-users to ensure that everything has been configured to work reliability in the final system. Edward Vacuum starts by creating a basic reference standard hardware-package that’s flexible enough to work in general, and then tailors it to fit each individual situation.

“The OEM involvement is becoming more key,” confided Wilson. “The differentiation of the process is more critical, and we’re very involved with the OEM in providing a complete solution. We can’t test everything fully at the OEM, but we establish performance benchmarks that carry on to the end-user.”

Since low cost-of-ownership is always desired, coordination with the OEM allows vacuum technologists to keep hardware and dilutants gas costs constrained by not over-designing the system.

If the end-user works on an R&D line or with a tool that has to process multiple IC types, precursors in use may change from lot to lot or from day to day. ALD/CVD vacuum tools and abatement technologies must then be flexible enough to safely and reliably deal with a wide variety of precursors. With new materials in use, not just deposition tools but tools for etch and strip likewise need to be flexible enough to properly handle a wider variety of effluents than ever before.

A Temperature Management System (TMS) on the foreline trap can be setup to take feed-forward information from the OEM tool, allowing for automated adjustment to different pre-set modes appropriate for different precursors.

“We try not to use traps whenever possible, because it introduces another potential failure point and inevitable maintenance, but occasionally it’s unavoidable,” elaborated Wilson.

Specifications from end-users for reliability and uptime only become more challenging in leading IC fabs. Consequently, Edwards Vacuum claims to have doubled the process flow capability of its vacuum systems, while increasing the mean time between service (MTBS) from six weeks to six months. It takes vacuum systems suppliers and OEMs and end-users working together to optimize the safe and reliable use of ALD and CVD processes needed to form the 3D IC devices of the near future.

Fig 1.: Pulsed precursors in a vacuum system.

Fig. 1: Pulsed precursors in a vacuum system.

Fig. 2: Minimizing deposition in the tool.

Fig. 2: Minimizing deposition in the tool.

Development of Silicon Photonics Devices Discussed in Forum

By Jeff Dorsch

Six speakers discussed developments in designing and manufacturing silicon photonics devices in a TechXPOT North session on Wednesday morning.

Attendees heard from representatives of IBM, Oracle, Compass-EOS, Luxtera, CEA-Leti, and Aurrion.

IBM’s Jean Trewhella said her company has been working on optical interconnect for a long time, and “we’re moving the technology into our Burlington fab.” In developing a “flexible platform” for silicon photonics, IBM is shooting for bringing the cost down to 2.5 cents per gigabit per second, she noted.

IBM designed built-in self-test into its silicon photonics devices, so it could do wafer-level test on the chips, Trewhella said. Fabrication was slotted at Burlington, Vt.’s 200-millimeter wafer fabrication facility in the interest of containing costs. Dimensions on the chip fell into the range of 90 nanometers down to 65nm, according to Trewhella. “There is no additional cost benefit from scaling photonic components,” she said.

Working with IBM in silicon photonics is Aurrion, a startup based in Santa Barbara, Calif. Eric Hall, the company’s vice president of business development, said Aurrion is integrating III-V semiconductors atop silicon waveguides to develop large wavelength-division multiplexing arrays. Indium phosphide and silicon chips are being employed in its products, along with indium-gallium-arsenide absorbers in its photodiodes.

“Integrating on silicon allows photonics to leverage the cost/volume/yield of established fabrication and packaging infrastructure,” Hall said. He added, “Aurrion is hiring!”

The session also heard from Jack Cunningham of Oracle, Shuki Benjamin of Compass-EOS, Peter De Dobbelaere of Luxtera, and Hughes Metras of CEA-Leti.

A 50Gbps Silicon Photonics transmit module (left) sends laser light from the silicon chip at the center of the green board, which then travels through optical fiber to the receiver module (right), where a second silicon chip detects the data on the laser and coverts it back into an electrical signal. Source: Intel.

A 50Gbps Silicon Photonics transmit module (left) sends laser light from the silicon chip at the center of the green board, which then travels through optical fiber to the receiver module (right), where a second silicon chip detects the data on the laser and coverts it back into an electrical signal. Source: Intel.

The Connected Experience: A Manufacturer’s Dream?

By Shannon Davis, Web Editor, Solid State Technology

Imagine being able to not only track and address equipment degradation in real time, but also analyze patterns in your factories’ equipment and address potential issues before they even present a problem.

It may sound too good to be true, but Microsoft’s Sanjay Ravi explained in Wednesday morning’s keynote that this innovation is becoming available now to manufacturers.

In his keynote “The Art of Possible: How Manufacturers are Leveraging Digital Technologies to Drive Business in a Connected World,” Mr. Ravi gave his audience a glimpse of the brave, new world that leveraging mobility, social, cloud and big data offers them, specifically siting product offerings and developments from Microsoft.

“The key priority is taking advantage of the connected business networks and enabling connected customer experience,” Mr. Ravi shared. Building a data culture across one’s organization can drive the right business processes and models, he explained.

He used examples from Samsung and AMD, who both utilized Cloud-based data analytics programs to reduce costs, manage energy and increase data warehouse performances by jaw-dropping percentages. AMD, for example, used Microsoft BI solutions to improve operational agility and was reportedly able to reduce resource support work needed by 90 percent. Samsung, he reported, analyzed 10 times more data to make more efficient decisions about energy management, using trend statistics and histograms – decreasing their costs by 75 percent.

“Given the explosion of the Internet of Things, all of our equipment can be connected,” said Mr. Ravi. “This means gathering big data from embedded devices and transforming big data into business information and insight.”

The implications are mind-boggling: manufacturers could anticipate production disruptions remotely and take corrective action anytime, anywhere.

And if that wasn’t enough to capture his audience’s imagination, Mr. Ravi also shared the Smart Elevator project Microsoft has in development. When used in an office setting, the Smart Elevators have the ability to learn office workers behaviors and analyze their Cloud-based work schedules to know 1) if they need to get on the elevator as they approach it and 2) where they will need to go once they get on the elevator. The result is a completely button-less elevator, an elevator that anticipates your schedule and is there right when you need it.

Whether it’s leveraging big data or Smart Elevators, the connected workplace isn’t science fiction: it’s possible and its potential is undeniable.

Sanjay Ravi during Wednesday morning's keynote at SEMICON West 2014

Sanjay Ravi during Wednesday morning’s keynote at SEMICON West 2014

Trends in Next-Generation MEMS Discussed in TechXPOT Forum

By Jeff Dorsch

The microelectromechanical system (MEMS) device market is forecast to increase at a compound annual growth rate of 13 percent over the next five years, reaching $24 billion in 2019, according to Jean-Christophe Eloy, president and CEO of Yole Développement.

Microphones still account for half of the MEMS market, and STMicroelectronics remains the top supplier of mobile MEMS for smartphones and tablet computers, he told a TechXPOT session on Tuesday morning. While five suppliers dominate the mobile MEMS market, there are more than 50 companies competing for market share in automotive MEMS, Eloy noted.

Among other topics, Eloy said the “critical issue” in MEMS is “how to increase the chance of new devices to enter the market.”

Jack Young of Qualcomm Ventures discussed digital health applications for MEMS. His investment fund has put money into Fitbit and InvenSense, among other companies. Wearable gadgets have the potential to become fashion accessories, he said, noting that Fitbit has consulted with designer Tory Burch.

With MEMS-based wearable electronics, “your body is tweeting, your body is posting on Facebook all the time,” Young commented.

Tomas Bauer, senior vice president of sales and business development for Silex Microsystems, said the MEMS market is ready to move beyond automobiles and smartphones, and his company, a pure-play MEMS foundry, has a number of process technologies, such as Sil-Via and Met-Via, to fabricate new types of MEMS devices. Silex has also developed a through-glass via technology for some applications.

The End of Scaling?

By Jeff Dorsch

Are we reaching the end of scaling?

Yes and no.

Let me explain.

The semiconductor industry has been able to “scale” the dimension features of chips steadily downward for decades. The good old, reliable planar bulk CMOS silicon process is on its way out, however, and scaling will have to go on without it. There seem to be no easy answers on how scaling will continue, with so many possibilities and variables to be considered.

Scaling might be an easier (not an easy) proposition if extreme-ultraviolet lithography systems were good to go for volume production of chips now, according to Brian Trafas, KLA-Tencor’s chief marketing officer. “EUV continued to be late to the marketplace,” he says. “It was going be for 14/16-nanometer, then 10-nanometer, now 7-nanometer.”

As EUV struggles forward, the industry is dealing with 193nm immersion lithography, which involves “more process steps, more cycle time,” Trafas says. “The focus on defectivity is really important. Everything needs to be defect-free.”

Dealing with all those defects is KLA-Tencor’s bread and butter, of course. “It’s good for us,” Trafas acknowledges.

Semiconductor Equipment and Materials International recognizes the general industry anxiety (or concern, at the minimum) about the future of scaling, and the topic is the subject of a Semiconductor Technology Symposium session on Wednesday, July 9. “Getting to 5nm Devices: Evolutionary Scaling to Disruptive Scaling and Beyond” will run from 9 a.m. to 12 noon in Moscone North. Attendees will hear from executives of GlobalFoundries, imec, Intel, Intermolecular, Sematech, and Soitec, along with professors at Stanford University and SUNY’s College of Nanoscale Engineering and Science. An Steegen, imec’s senior vice president of process technology, said at SEMI’s show-opening press conference on Monday that there are two different scaling roadmaps to consider – device scaling and system scaling. With the immersion lithography in use throughout the semiconductor industry, manufacturers are “battling complexity,” she said. Three-dimensional devices with FinFETs, 3D stacking in packaging, and emerging memory types could be answers to the scaling crisis, according to Steegen.

Once extreme-ultraviolet lithography becomes available, that will help the industry get through at least two process nodes, she added. FinFETs can “reset the roadmap,” Steegen said, and the industry has to “make sure the incentive is there” for 3DICs.

William Chen of ASE Group said of Moore’s Law and scaling, “The economic benefit is receding.” He looks toward system-in-package technology, with wafer-level packaging, 2.5D chip stacking, flip-chip packages, and wire bonding to help advance device scaling.

Robert Cappel, senior director of marketing at KLA-Tencor, said Monday, “Scaling is going to continue. It’s just going to be very, very hard.” Integrated device manufacturers need to collaborate with electronic design automation companies and fabless semiconductor companies to solve the scaling issues, he added.

The industry will need “virtual IBMs” – integrated efforts that can work on scaling from design to fabrication to packaging, Cappel asserted. That may come about when “the fabless powerhouses start to drive that,” he said.

Scaling still has several process nodes to get through. How that will be done will the subject of debate and interest for years to come.

New Materials Provide Innovation Yet Add Complexity

By Jeff Dorsch

If semiconductor materials had a personal Facebook page, its status would be: It’s Complicated.

The days of all silicon, all the time are starting to dwindle. Can any material or combination of materials be as simple and useful as Si?

Some say the semiconductor future belongs to carbon. Graphene, the carbon material that has many wondrous attributes, is not a good semiconducting material, however. IBM Research predicts that carbon nanotubes will take over from silicon at the 5-nanometer process node, when traditional scaling will no longer work. CNTs should be the basic semiconductor material of the 2020s, according to IBM.

For the latter half of this decade, however, there will still be silicon and other materials, including compound semiconductors and semiconductor alloys. Molybdenum disulfide is gaining fans among materials scientists.

“The channel is getting thinner and thinner,” says Aaron Thean, vice president of process technology and director of logic development at imec. With silicon germanium, “processing gets a lot more complicated,” he notes. “With III-V compounds, the key challenge there is the gate stack.”

The 10nm process node is “very tough,” Thean says, and that may be where SiGe really starts to shine. At the 7nm node, there is a “positive outlook for germanium,” he adds.

Thean is bullish on carbon nanotubes as a workhorse material of the future. CNTs possess “the upside of grapheme, but none of the downside,” he says. “The bandgap starts to open.

“A lot of people are working on this,” including IBM, Thean says, noting that there are several types of CNTs.

Gallium arsenide remains a popular material for specialty applications. Gallium nitride, gallium-nitride-on-silicon and silicon carbide are finding more uses these days. Research is going in strontium titanate and other oxide-based semiconductors.

For most providers of IC foundry services, plain old CMOS silicon answers most of their needs, according to Brian Trafas, chief marketing officer of KLA-Tencor. New architectures, such as FinFETs, are presenting challenges for foundries and other chipmakers, he says. A few years out, there may be a requirement for III-V FinFETs, Trafas adds. “That’s probably a 5-nanometer decision,” he says.

In addition to the new materials being used in logic devices, “there could be big changes in memory types” that will call for new and different materials, Trafas says. Magnetoresistive random-access memories (aka magnetic RAM), resistive RAM, and other cutting-edge memory chip technologies are bidding to replace DRAMs, SRAMs, and NAND/NOR flash memory devices, he notes.

With the adoption of new materials, collaboration between semiconductor manufacturing equipment vendors and their customers becomes “more important,” Trafas concludes.

Back for its second visit to SEMICON West this year is Element Six, the supplier of gallium-nitride-on-diamond wafers and synthetic diamond heat spreaders. In May, the company touted the use of its GaN-on-diamond wafers by Raytheon as an alternative to GaN-on-SiC as part of the Defense Advanced Research Project Agency’s Near Junction Thermal Transport program for improving power density and thermal management in GaN radio-frequency devices.

In addition to a TechXPOT session on materials for 3D NAND flash memories this week, Semiconductor Equipment and Materials International is planning its annual Strategic Materials Conference for September 30 and October 1 in Santa Clara, Calif. The 2014 theme for the SMC is “Materials Matter—Enabling the Future of IC Fabrication and Packaging.”

By the way, you can find “semiconductor materials” on Facebook – it’s a link to the Wikipedia article on semi materials.

Solid State Technology and SEMI Announce the 2014 “Best of West” Award Winner

Solid State Technology and SEMI, yesterday announced the recipient of the 2014 “Best of West” Award — Nikon Corporation — for its NSR-S630D Immersion Scanner.  The award recognizes important product and technology developments in the microelectronics supply chain. The Best of West finalists were selected based on their financial impact on the industry, engineering or scientific achievement, and/or societal impact.

Nikon has clearly demonstrated leadership with ArF immersion tools, particularly in the area of 450mm.

At SEMICON West this week, a collection of the first fully patterned 450mm wafers – using a Nikon immersion lithography tool — were on display at the newly merged SUNY CNSE/SUNYIT exhibit, booth 517, located in the Moscone Center’s South Hall.

best of the west

The Nikon immersion scanner will join existing 450mm infrastructure at the Albany NanoTech Complex in April of 2015 in accordance with the project timeline.  This critical milestone will enable G450C founding members and CNSE to perform 10nm and below, full wafer photolithography, while optimizing tool configuration and performance.

The Best of West award-winning NSR-S630D ArF Immersion Scanner leverages the well-known Streamlign platform, incorporating further developments in stage, optics, and autofocus technology to deliver unprecedented mix-and-match overlay and focus control with sustained stability to enable the 10/7 nm node.  The Nikon Corporation booth is in South Hall, Booth 1705.

The NSR-S630D incorporates newly designed optics that deliver multiple levels of active control, while The semiconductor industry is moving to development and high volume manufacturing of sub-10 nm generation process devices. Budgets are even tighter at these advanced nodes, making enhanced stability vital. The NSR-S630D leverages established immersion technology, while incorporating key innovations to deliver MMO capabilities below 2.5 nm and throughput greater than 250 wafers per hour, in addition to critical overlay and focus “sustained stability.”

The NSR-S630D leverages the Streamlign platform, incorporating further developments in stage, optics, and autofocus technology to deliver unprecedented performance with “sustained stability” to enable the 10/7 nm node. Additionally, the S630D provides world-class throughput ≥ 250 WPH, and is compatible with advanced software solutions that ensure peak manufacturing performance. Significant technical, infrastructure, and business-related issues continue for EUVL, with unclear cost benefits. A 300 mm process step and cost comparison for EUVL double patterning (DP) was 2x higher than ArF immersion multiple patterning, and EUV DP results were even less favorable under 450 mm conditions. From the overall cost perspective, new technologies are not always the best approach, and based on 10 years of success, it is believed that 193i immersion will remain the low cost solution moving forward. Multipoint High Speed phase measurement interferometry enables adjustment of the lens at intervals to reduce aberrations. These enhanced tuning capabilities enable extremely low wavefront rms. Beyond imaging, overlay and focus control are the critical performance factors for the 10/7 nm node.

Single nanometer distortion values have been achieved, which is a major factor in improving overlay/mix-and-match capabilities. In addition, the new NSR-S630D reticle stage uses an encoder servo system to increase accuracy while the wafer stage delivers improved temperature control, coupled with structural and water management innovations to enhance stability. The S630D has demonstrated single machine overlay (SMO) Avg.+3σ below 1.4 nm across the lot, with across lot S622D/S630D mix-and-match overlay (MMO) below 2.5 nm (Figure 2A). Further, the S630D autofocus system employs a narrower sensor pitch and improved edge mapping for better focus uniformity, and minimizes sensor fluctuations and process sensitivities. Together these factors optimize yield and increase edge dies per wafer.

Autofocus performance was verified with uniformity data (3σ) below 9 nm (including edge shots) and 5.9 nm for full field shots alone. Intrinsic CD uniformity results below 0.69 nm were also demonstrated for 41 nm lines on a 90 nm pitch.

At the most advanced nodes, tool stability and process robustness become increasingly critical. Additional calibrations help with this, but they must not compromise productivity. Therefore, long-term inherent tool stability and process robustness must be maintained. The S630D has demonstrated five lot SMO data below 1.7 nm (Avg. + 3σ) across a ten-day period (Figure 3A), and SMO performance (Avg. + 3σ) below 1.4 nm across the lot for both hydrophobic and hydrophilic processes. Additionally, a two week focus stability range of only 5.3 nm max/min was achieved.

Nikon provides a number of “Masters” – automated software solutions that ensure the scanner is performing at its best. These include LNS (lens) Master, OPE Master, CDU Master, and OVL (overlay) Master. LNS Master enables reticle-specific thermal compensation on the scanner. OPE Master uses customer designs and scanner adjustments to provide illumination condition matching for aligning performance across a fleet of scanners and ensuring that one OPC solution works on all of them. CDU Master provides optimization capabilities that enable the scanner to correct for other process window detractors. Because overlay matching plays a central role in multiple patterning applications, OVL Master enables automated grid and distortion matching, as well as automated reticle expansion correction to maximize yield. The NSR-S630D works in tandem with the Masters software to deliver optimized scanner exposure parameters that enhance performance on product wafers. In addition to maximized yield and manufacturing flexibility, enhanced productivity is imperative in making these advanced multiple patterning processes cost effective for chipmakers, and the S630D delivers world-class throughput ≥ 250 wafers per hour (WPH).