FinScale Incorporated, the semiconductor device and process innovation company, today announced immediate availability of its qFinFETTM technology, a next generation 3D MOSFET architecture and manufacturable process readily transferable to foundries and integrated device manufacturers. Crafted from the combination of many unique device and process innovations by FinScale’s scientists, the qFinFET technology offers significant improvements in performance, power efficiency and circuit density, along with substantially lower leakage, parametric variability and manufacturing costs than available advanced node FinFET and planar technology alternatives. From a device design optimized for quantum effects, ballistic transport and the nano-material properties of silicon, this quantum FinFET device architecture will scale to the end of the silicon MOSFET era.
“The technology shift from planar to 3D device architectures has opened new degrees of freedom and exciting opportunities for new innovations,” said George Cheroff, a prominent IBM Research manager and semiconductor pioneer who envisioned and developed the first n-channel planar MOSFET process used for memory and logic circuits in computers. “The qFinFET technology elegantly combines the advantages of current FinFET and planar FD-SOI technologies, and mitigates their inherent weaknesses to provide a unifying platform that will put the semiconductor industry back on track with Moore’s Law.”
“FinScale’s qFinFET offers manufacturers a high-yield 3D process for building scalable aspect-ratio fins that can be formed without double patterning down to the 14/16 nm node, and provide increased performance and transistor width (W) per unit area,” said Jeffrey Wolf, president and chief executive officer at FinScale. “Resulting fin transistor topologies deliver additional area reductions, and offer designers further area-saving and performance-boosting opportunities to differentiate at the cell library and circuit level when integrated with leading middle-of-line (MOL) technologies.”
“We conceived the Quantum FinFET by pushing silicon to its quantum scaling limits, while seeking to maximize carrier mobility, electrostatic gate control, yield and reliability,” said Dr. Victor Koldyaev, Finscale’s chief technology officer. “Using this approach we designed the qFinFET front-end-of-line (FEOL) device and process solution for the 7 and 10nm generations, and were pleased that the same device concept would significantly boost parametric performance and economic returns for manufacturers back to the 28/32nm node. We then laid out standard cells, SRAMs, eDRAMs and 2-bit/cell non-volatile memories using industry standard design rules and realized that we could readily exceed the best published results at those nodes and give manufacturers and designers opportunities for further improvement.”
The qFinFET technology offers unique benefits for foundries and integrated device manufacturers. The included high density and high performance logic and memory configurations, along with inherent low-noise analog/RF device characteristics, make qFinFET a robust SoC platform, either on bulk or SOI substrates. Standalone DRAM, flash and SRAM memory designers and manufacturers can configure the included bit cells into dense arrays, and build dense, highly reliable sense amplifiers and low-leakage pass transistors.
FinScale will be presenting its qFinFET technology at the Silicon Innovation Forum (www.semiconwest.com/SIF) at the SemiconWest conference on July 8, 2014 in San Francisco at the Moscone Center. CEO Jeffrey Wolf will present FinScale’s investor pitch at 10:15am in the North Hall, room 134. Then from 4:00pm to 6:00pm Mr. Wolf and Dr. Victor Koldyaev will be presenting posters at the Silicon Innovation Forum Showcase and Reception.