By Jeff Dorsch
Intel, Samsung Electronics, and Taiwan Semiconductor Manufacturing have made their moves into three-dimensional semiconductors. Now it remains to be seen how the rest of the semiconductor industry will make the transition to 3DICs.
It’s not going to be another dimension shrink, by any means. As difficult as the transition to fabrication with 28-nanometer features was for many chipmakers (and remains so for many second-tier semiconductor manufacturers), that scaling shift will seem like child’s play as integrated device manufacturers and silicon foundries deal with silicon interposers, through-silicon vias, and other accoutrements of the 3D chip world.
Yole Développement estimates the value of semiconductors with TSVs in 3DIC and 3D wafer-level chip-scale packages – including ambient light sensors, CMOS image sensors, power amplifiers, and inertial and radio-frequency microelectromechanical system devices – was $2.7 billion in 2012. It forecasts that such chips will represent 9 percent of the semiconductor market in 2017, with nearly $40 billion in value.
Transparency Market Research has a more modest forecast for 3DICs. It estimates the value of 3D chips in 2012 was $2.4 billion and will rise at a compound annual growth rate of 18.1 percent over the next five years, hitting $7.52 billion in 2019.
“Customers like to scale their devices for greater performance or better battery life,” says Brian Trafas, chief marketing officer of KLA-Tencor. “They’re moving from 2D to 3D.”
“The logic leader” (generally known as Intel) made its move at the 22-nanometer process node, Trafas notes, while “the foundry leader” (that would be TSMC) migrated to 3D at 16nm, Trafas notes. In advanced 3D memory chips, “one leader is out front,” he says, announcing that its wafer fabrication facility in China is producing 3D NAND flash memories (that’s Samsung).
As the technology leaders enter the brave new world of 3D chips, “we do now see some spending for 14- and 16-nanometer by foundries,” Trafas says.
Making 3DICs calls for multiple patterning in photolithography and “more process steps,” the KLA-Tencor executive says, which is good for sales of process control equipment. “The logic leader” experienced yield issues when it started making 3D chips, and “we’re seeing the same thing with foundries,” Trafas says. “It’s very challenging.
“It’s somewhat like 28-nanometer. It’s typical of what you see at all new nodes,” he adds.
Despite the challenges in defects and yield with 3DICs, “it should be successful,” Trafas concludes.
At SEMICON West, 3DICs will be under discussion in several forums, including the TechXPOT programs in Moscone Center’s North and South halls.
Like it or not, 3DICs are here. Better brush up on those TSVs.