OLEDs

OLEDS ARTICLES



C3nano seals acquisition of Asia's largest manufacturer of silver nanowire, Aiden Co. Ltd. Korea

04/28/2015  C3nano, Inc. announced today that it has acquired the major supplier of silver nanowire (AgNW) in Asia, Aiden Co. Ltd. of Korea.

ITRS 2.0: Top-Down System Integration

04/22/2015  ITRS2.0 will, for the first time, develop a top-down system-driven roadmap framework for key semiconductor industry drivers in the 2015-2030 period.

SOI: Revolutionizing RF and expanding in to new frontiers

04/17/2015  SOI provides the capability to revolutionize RF Front Ends and WAN RFSOCs through innovation in radio architectures.

Solid State Watch: April 10-16, 2015

04/17/2015  SEMI reports 2014 semiconductor photomask sales of $3.2B; Automotive touch panel revenues to hit $1.5B by 2018; Sensor shipments strengthen but falling prices cut sales growth; ClassOne enters ECD lab partnership with Shanghai Sinyang

Monolithic 3D processing using non-equilibrium RTP

04/17/2015  Qualcomm endorses CEA-Leti’s “CoolCube” transistor stacking approach.

Solid State Watch: April 3-9, 2015

04/10/2015  SEMI reports 2014 global semiconductor materials sales of $44.3B; Cavendish Kinetics adopts STATS ChipPAC’s wafer level technology; MEMS shipments to reach 43.3B units by 2018; TSMC certifies Synopsys design tools for 16nm finFET plus production

Web tension control in roll-to-roll web processing

04/07/2015  Achieving precise registration accuracy is a factor of two related variables: web tension and transport velocity.

C3Nano Inc. and Kimoto Ltd. Japan partner in a strategic alliance

04/02/2015  C3Nano, Inc., a developer and supplier of solution-based, transparent conductive inks and films announced today that it has entered into a partnership with Kimoto, Ltd. Japan.

Deeper Dive: Xpedition Enables Co-Design of Chips, Packages, Boards

03/31/2015  A new product from Mentor Graphics called Xpedition® Package Integrator provides a new methodology and platform in addition to a new suite of EDA tools. The platform enables chip, package and board designers to easily see how changing various design elements impact adjacent designs, an industry first.

Synopsys founder has plenty of work to do, isn't interested in politics

03/26/2015  Aart de Geus is not running for governor of California.

Stronger competition forecast for mobile phone display manufacturers this year

03/06/2015  Global mobile phone display module shipments in 2015 are expected to rise just 4 percent year-over-year to reach two billion units, leading to even stronger competition among mobile phone display manufacturers.

MicroWatt Chips shown at ISSCC

03/05/2015  With much of future demand for silicon ICs forecasted to be for mobile devices that must conserve battery power, it was natural for much of the focus at the just concluded 2015 International Solid State Circuits Conference (ISSCC) in San Francisco to be on ultra-low-power circuits that run on mere microWatts (µW).

Time to “shift left” in chip design and verification, Synopsys founder says

03/04/2015  Taking “Smart Design from Silicon to Software” as his official theme, Aart de Geus urged attendees to “shift left” – in other words, “squeezing the schedule” to design, verify, debug, and manufacture semiconductors.

Breakthrough in OLED technology

03/03/2015  Organic light emitting diodes (OLEDs), which are made from carbon-containing materials, have the potential to revolutionize future display technologies, making low-power displays so thin they'll wrap or fold around other structures, for instance.

SPIE Advanced Lithography conference concludes

02/27/2015  Exposures, and reducing their cost, were a theme running through the 2015 SPIE Advanced Lithography Symposium this week in San Jose, Calif., the center of Silicon Valley.

Learning to live with negative tone

02/27/2015  In lithography for manufacturing semiconductors, a negative tone can be a positive attribute.

Directed Self Assembly Hot Topic at SPIE

02/25/2015  At this week’s SPIE Advanced Lithography Symposium in San Jose, Calif., the hottest three-letter acronym is less EUV and more DSA, as in directed self-assembly.

Proponents of EUV, immersion lithography face off at SPIE

02/25/2015  The two main camps in optical lithography are arrayed for battle at the SPIE Advanced Lithography Symposium. EUVt lithography, on one side, is represented by ASML Holding, its Cymer subsidiary, and ASML’s EUV customers, notably Intel, Samsung Electronics, and TSMC. On the other side is 193i immersion lithography, represented by Nikon and its customers, which also include Intel and other leading chipmakers.

SPIE plenary takes in photonics, 3DICs, connected devices

02/23/2015  Speakers at the plenary session of the SPIE Advanced Lithography conference covered a wide variety of topics, from photonics to 3D chips to the Internet of Things, on Monday morning, February 23, in San Jose, Calif.

Complexity is the Theme at Lithography Conference

02/23/2015  Nikon and KLA-Tencor put on separate conferences in San Jose, Calif., on Sunday, February 22, tackling issues in advanced optical lithography. The overarching theme in both sessions was the increased complexity of lithography as it approaches the 10-nanometer and 7nm process nodes.




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WEBCASTS



Advanced Packaging: A Changing Landscape Rife with Opportunities

May 10, 2016 at 1 PM ET / Sponsored by Brewer Science

Die stacking enables better chip performance in a small form factor, meeting the needs of smartphones, tablets, and other advanced devices. Through-silicon vias are moving into volume packaging production, but problems with reliability, cost, and scaling remain. The supply chain also must adjust to this “mid” step between front- and back-end chip production. This webcast will explore the wafer thinning, bonding, TSV formation and other critical process steps necessary to enable 3D integration.

Sponsored By:
Trends in MEMS

May 11, 2016 at 12 PM ET / Sponsored by Boston Semi Equipment

MEMS have quite different process and material requirements compared to mainstream microprocessor and memory types of devices. This webcast will explore the latest trends in MEMS devices – including sensor fusion, biosensors, energy harvesting – new manufacturing challenges and potential equipment and materials solutions to those challenges.

Sponsored By:
Fan-Out Wafer Level Packaging

May 2016 (Date and time TBD) / Sponsored by Zeta Instruments

Wafer level packaging (WLP) using fan-out technology is an attractive platform for achieving low-cost low-profile package solutions for smart-phones and tablets, which require cost-effective, high-density interconnects in small form-factor packaging. Assembled directly on a silicon wafer, the approach is unconstrained by die size, providing the design flexibility to accommodate an unlimited number of interconnects between the package and the application board for maximum connection density, finer line/spacing, improved electrical and thermal performance and small package dimensions to meet the relentless form factor requirements and performance demands of the mobile market. In this webcast, industry experts will explain the FOWLP process, discuss recent advances and forecast future trends.

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TECHNOLOGY PAPERS



Protecting Electronics with Parylene

This whitepaper provides a comprehensive overview of parylene conformal coating, advantages of parylene, and applications for parylene to protect electronic devices. As technology continues to advance, devices will encounter rugged environments and it is vital that they are properly protected. Parylene conformal coating is one way that manufacturers are giving their devices a higher level of protection, along with increasing the overall quality of their products. Parylene conformal coating applications for Electronics include: · I/O & PCI Modules · Power Converters and Supplies · Backplanes · Other Embedded Computing applications · Other specialty electronics and assemblies April 26, 2016
Sponsored by Diamond-MT

NMT: A Novel Technology for In-Line Ultra-Thin Film Measurements

XwinSys identified the semiconductors recent market trends and developed a novel XRF technology, named NMT: Noise-reduced Multilayer Thin-film measurement. This innovative approach can be used for in-line inspection and metrology features, to accurately and precisely analyze single and multi-layered elements in ultra-thin films. NMT novel technology can be utilized for in-line applications ranging from localized ultra-thin film stacks to the inspection of 3D localized features to the analysis of defects involving geometries, voids and material elements. February 23, 2016
Sponsored by XwinSys Technology Development Ltd.

Adhesives for Electronic Applications

Master Bond custom formulates epoxy adhesives, sealants, coatings, potting and encapsulation compounds to meet the rigorous needs of the electronic industry. We are a leading manufacturer of conformal coatings, glob tops, flip chip underfills, and die attach for printed circuit boards, semiconductors, microelectronics, and more. Browse our catalog to find out more.January 05, 2016
Sponsored by Master Bond, Inc.,

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EVENTS



SID Display Week 2016
San Francisco, CA
http://www.displayweek.org
May 22, 2016 - May 27, 2016
Design Automation Conference
Austin, TX
https://dac.com
June 05, 2016 - June 09, 2016
The ConFab
Las Vegas, NV
http://theconfab.com
June 12, 2016 - July 15, 2016
SEMICON West 2016
San Francisco, CA
http://www.semiconwest.org
July 12, 2016 - July 14, 2016

VIDEOS