Author Archives: psinger

Semiconductor Materials: Growth, Opportunities and Challenges

Don’t miss this week’s webcast on Thursday at 1:00 pm Eastern, 10:00am Pacific.

We have two great speakers lined up. First, Lita Shon‐Roy, President/CEO of Techcet, will provide an overview of chip level materials markets, focusing on growth and opportunities. Next, SRC’s Jon Candelaria, Director, GRC Interconnect and Packaging Sciences, will describe how today’s researchers are exploring materials challenges beyond Moore’s Law.

Click here to register.

Here are some more details:

Lita will talk about how current 3-dimensional structures present new challenges relating to uniformity, lithographic resolution, high aspect ratio etching and fills, and planarization while addressing continuing need to stay at or below current technology node scaling.  What do these challenges really mean in terms of changing material requirements and materials growth opportunities?  In her presentation, Lita will highlight those processes that must have better, alternative process materials, and provide market forecasts on these materials opportunities.

In his presentation, Jon will focus on how the electronics industry is facing a growing crisis in being able to continue providing cost-effective processes and designs to support the continuation of what’s been referred to as ‘Moore’s Law.’ This ‘Law’, or more accurately ‘observation of the economics involved in scaling integrated circuits,’ has been a very useful guideline for several decades, but as with any similar types of projections, has been expected to some day run its course. While the exact timeframe is still uncertain, that ‘day’ is now within sight, and yet there are still no clear paths forward beyond that point. This presentation will provide a brief glimpse of some of the key materials-related challenges that exist within the frontend (devices), lithography, and backend-of-line (chip level interconnects). It will also include just a few of the research concepts that offer some potential paths forward, which the Semiconductor Research Corporation and its member companies are exploring alongside the university researchers they are supporting.

And speaker bios:

litaMug

Lita Shon‐Roy, President/CEO of Techcet, has worked in the electronics materials industry in business development and technical marketing for more than 25 years. Her work experience spans from business development, marketing and sales of IC’s, equipment, and materials to process development of flat panel displays (TFTs). She has developed new business opportunities for companies such as RASIRC/Matheson Gases and IPEC/Speedfam and helped establish marketing and sales proficiency in companies such as Air Products/Schumacher, Brooktree/Rockwell, and Hughes Aircraft. Lita helped build IPEC as a leader in CMP equipment as Director of International Sales. In 1998, Lita cofounded Techcet Group, LLC. She has authored and co‐authored various articles and texts focused on the semiconductor processing, industry forecasting, and the world economy and is now a recognized expert in electronic materials marketing and business development. Lita holds a Master’s Degree in Electrical Engineering, with a specialty in Solid State Physics from USC and a Bachelor’s Degree in Chemical Engineering from UCSD. She is currently completing her MBA at California State University, Dominguez Hills.

jon-candelaria

Jon Candelaria, Director, GRC Interconnect and Packaging Sciences

Jon Candelaria has over 35 years of experience in the electronics industry in a wide variety of engineering and managerial roles. He was most recently a Distinguished Member of the Technical Staff at Motorola’s Applied Research & Technology Center before joining the SRC in September, 2010 as the Director for Interconnect and Packaging Sciences. He has over a dozen issued patents and published technical articles, and received the Motorola Patent of the Year Award for an invention which contributed over $1B to Motorola over the course of its lifetime. He served as Technical Program Chair and General Chair of the IEEE Electron Devices Society’s flagship conference, the IEDM. Jon was the V.P. of Conferences for the IEEE’s Electron Devices Society (EDS), the EDS representative on a joint United Nations-IEEE Humanitarian Challenge advisory committee, and was Chair of both the IEEE Computer Society and Laser and Electro Optics Society Phoenix Chapters. He is currently the Treasurer and Technical Program Committee member for the International Interconnect Technology Conference (IITC), and is a member of the Editorial Panel for Future Fabs International.

Don’t Hack My Light Bulb, Bro

The age of the Internet of Things is upon us. It’s about all anyone talked about over the last few weeks, as I visited the TSMC Open Innovation Platform (Sept 29th), ARM TechCon (October 1-2) and Semicon Europa (Oct 7-9).

I think Rick Cassidy, Senior VP of TSMC and president of TSMC North America, captured most people’s feelings when he kicked off the TSMC OIP saying: “The IoT is hot, it’s hot, it’s really hot.” Pete Hutton, ARM Executive VC, speaking at the ARM TechCon a day later, said “ IoT is a very, very exciting area for us and a very, very exciting area for the industry.”

There are, of course, two aspects of IoT. One is at what you might call the sensor level, where small, low power devices are gathering data and communicating with one another and the “cloud.” The other is the cloud itself. “IoT devices are expanding fast. There’s vast innovation going on in the space. It’s innovation driven by a range of people. A range of people from very large multi-nationals all the way to small groups of engineers in a garage. That innovation is going to create lots of opportunities. It’s also going to create massive volumes of data. Massive amounts of small data rippling through the network, rippling through the infrastructure.”

There is a lot to think about at both levels – how sensors will be integrated with batteries, energy harvesting devices, networking/connectivity capabilities, etc. on the one hand, and how servers will need to change and adapt to process massive amounts of data in the cloud and the “edge” of the cloud on the other.

What I found interesting in listening to many speakers over the last couple of weeks is how many people believe that the lowly light bulb might be how the IoT makes it’s way into your home. Light bulbs  have a ready energy source, they are in every room of your home and if they’re LEDs, they already have some computer functionality built in (through the driver chip). Yes, the NEST smoke detector has grabbed the headlines lately, but it’s probably the light bulb that will win.

Of course, this needs to be easy to use. As Simon Segar noted in his keynote talk at ARM TechCon, you don’t want to unlock your phone, find an app and click on it to turn on the light when you walk into a room. Nor do you want to have your light bulb talk to a server in Norway before it communicates with the thermostat (or your fridge/toaster/smoke detector/washing machine).

And you don’t want your light bulb hacked.  At SEMICON Europa, I sat in on a presentation titled “Secure Connections for The Internet of Things” by Dr. Wouter Leibbrandt, Senior Director, Manager Systems & Applications, Central R&D CTO, NXP. He said that while some parts of the IoT, such as banking, are very secure, the various parts are not well connected. There is considerable vulnerability through devices such as an internet-connected light bulb that would allow hackers to broach your system and gain access to sensitive documents and perhaps even bring down your whole system (or hold it for ransom).

How big the IoT is going to get is anyone’s guess. At the ARM TechCon, ARM founder and CTO Mike Muller said there could be 50 billion devices connected to the internet by 2020. A week later, at a SEMI press conference, Claus Schmidt, managing director, Robert Bosch Venture Capital GmbH, said he’d heard 80 billion.

Clearly, the IoT is going to be huge. But security, even at the light bulb level, is going to be critical.

Editor’s Note: My muse for the headline.. On September 17, 2007, U.S. Senator John Kerry – now Secretary of State — addressed a Constitution Day forum at the University of Florida in Gainesville. A student, Andrew Meyer, became agitated during a subsequent Q&A and was arrested. During arrest, the officers asked him repeatedly to stop resisting, but Meyer continued to struggle and scream for help. While six officers held Meyer down one of the officers stunned him with a Taser following Meyer’s shouted plea to the police, “Don’t tase me, bro!” The YouTube video went “viral” and now has more than 7 million views.

Can we take cost out of technology scaling?

There is much talk these days about continued scaling, including some recent posts by my colleague Ed Korczynski, in “Moore’s Law is Dead” Part 1 (What?) and Part 2 (When?). At The ConFab in June, keynote speaker, Dr. Gary Patton, vice president, semiconductor research and development center at IBM, talked about scaling, adding some historical perspective. I previously blogged about the “three fundamental shifts” that Patton believes will lead to a bright future for the semiconductor industry.

“We will keep scaling,” he said. “We have shown a tremendous ability to innovate and keep moving that technology forward.”

In the 1990s, Patton notes that life was actually pretty simple. “You brought in a new lithography tool, you scaled the horizontal dimensions, you scaled the vertical dimensions and you got a new technology out. It was better performance, the same power density, and you could do a lot more on the chip,” he said.

Patton_Slide5

Around 2000, we hit the gate oxide limit. “Gate oxide got to be abount three atomic layers. We could have said at that point ‘game over, scaling has ended.’ But guess what, we innovated. We came up with a pretty fundamental shift in ideas which is let’s change the fundamental properties of silicon. If we can strain the silicon, we can enhance the mobility. We can change the gate oxide. We can enhance the coupling between the gate and the channel. And that’s what we get over that last decade. We said let’s go from SRAM to a very high performance eDRAM (embedded DRAM) so we can put a lot more memory next to the processor because we knew memory was a key gating factor for the processor speed. This enabled the personal computing era and smart consumer electronics,” Patton said.

In 2010, we were at another one of these inflection points. “It’s not surprising that the improvements in 20nm are less than people would like because we really reached the end of the planar device era. Again, we were saying ‘game over, we’re done scaling.’ But no, we continue to innovate. The next decade is really about 3D. 3D devices, finFETs, or 3D chip integration,” he added.

Patton said that design technology co-optimization will be a key piece of getting through the next decade. “That will probably take us to about 2020,” he said. At that point we’re going to “hit the atomic dimension limit and we’re going to have to do it all over again. Here, we’re going to get into nanotechnology. Nanowire devices, silicon nanowires, carbon nanotubes, photonics and multi-chip stacking to bring things together. That will enable wearable computing, everywhere connectivity and cognitive computing.”

Patton said the problem is not physics. “We’re going to have solved the physics problems,” he said. “The problem is financial.” Patton showed a chart (below) that depicted the history of our industry from 1980 to present. “What drove the industry was smaller features, which enabled better performance and better cost per function. It enabled new types of applications, and that enabled larger markets. If you look in this time period, there’s about a six order of magnitude improvement in cost per transistor and that enabled a seven order of magnitude increase in consumption of silicon transistors,” he said.

Patton_Slide6

The challenge we’re facing right now is depicted below, showing the compound growth rate reduction and the cost of a circuit. On the x-axis is linear scaling. “We’ve typically targeted about a 0.7X linear scaling, which means from an area perspective, you get about 50% improvement. Note the line, 50%, doesn’t go through 50% improvement because with each new technology, there is some increase in complexity. It might be more like 30% improvement at the die level. If we’re really good and provide some enhancements in the technology, self-aligned processes, things like that, we may get it to 40%. So 30-40% is about the range we’ve been getting in terms of the cost per die improvement as we scale up.

Patton_Slide7

“The challenge we’re facing now is two fold. Number one, we’re struggling to get that 0.7X linear scaling. It might be about 0.8X. And we’re adding a lot more complexity, especially when you adding double and triple patterning .The focus today in innovation has got to be heavily focused on ‘how do we drive cost?’ Not just how do you scale, because scaling would add a lot of extra cost at this point. How do we drive cost down, how do we keep adding value to the technology. The model is changing. Moore’s Law can still hold, but we have to focus on the cost equation. So there’s really two parts. Technology innovation which is focusing on the patterning, focusing on the materials, the processing, and how do we drive that to take cost out of the technology scaling,” Patton said.

Three fundamental shifts

At The ConFab last week, Dr. Gary Patton, vice president, semiconductor research and development center at IBM, said there is a bright future in microelectronics (I heartily agree). He said that although there seems to be a fair amount of doom and gloom that scaling is ending and Moore’s Law is over, he is very positive. “There are three huge fundamental shifts that are going to drive our industry forward, will drive revenue growth and will force us to keep innovating to enable new opportunities,” he said.

The first fundamental shift is the explosion of applications in the consumer and mobile space. Patton noted examples such as cars that can drive themselves and can detect people and bicyclists and avoid them, smart phones for as little as $25, wearable devices that not only tell you what you’re doing but how you’re doing, and 4K television. “That is an incredible TV system, but it’s going to demand a lot of bandwidth; twice the bandwidth that’s out there today. If you turn on your 4K system, your neighbors are going to start to notice it when they try to access the internet,” he said.

Patton said that it’s estimated that today there are about 12.5 billion devices connected to the internet. That’s expected to grow to $30 billion by 2020. This represents the second fundamental shift commonly known as Big Data. “All these interconnected devices are shoving tremendous amount of data up into the cloud at the rate of 1.5 Exabytes (1018) bytes of data per month,” Patton said. “And that’s grown by about an order of magnitude in just the last 13 years. The estimate is that in the next 4 years, it’s going to go up another order of magnitude. It’s accelerating.”

The third fundamental shift is with all this data going up into the cloud, the data is almost all unstructured data, such as video and audio. “It’s related data but disconnected. How do we take that data and do something with it? That brings us to analytics and cognitive computing. We have really just started in this arena.”

So there you have it. Three reasons to be very positive about the future of the semiconductor industry: an explosion of applications, the rise of big data and the need to analyze all that data.

The Rise of MEMS Sensors

Join us for a MEMS-focused webcast on Thursday, June 19th at 12:00pm Eastern time. Click here to go directly to the registration page.

Jay Esfandyari, Director of MEMS and Analog Product Marketing at STMicroelectronics, will discuss the rise of MEMS sensors. Although Micro-Electro-Mechanical Systems (MEMS) have been around for a long time, the introduction of the technology into consumer markets, with Nintendo’s Wii in late 2006, opened the floodgates with multiple MEMS – accelerometers, gyros, compasses, pressure sensors and microphones — now in smartphones and tablets. And you ain’t seen nothing, yet!
 
Next,
Simone Severi, lead for SiGe MEMS at imec, will discuss SiGe MEMS technology for monolithic integration on CMOS. He will describe the recent development of MEMS technologies at imec that enables the monolithic integration of MEMS on CMOS. This approach represents a potential key advantage for a variety of MEMS systems as it can lead to a device performance improvement and to the scaling of the system area with consequent cost and package size reduction. Systems requiring multiple MEMS devices on chip or large MEMS array will benefit the most out of this approach.

One route focuses on the direct post processing on top of CMOS of a low temperature SiGe material, fully compatible with standard Al back end of line processes. This platform can realize a compact system for multi sensing applications. Accelerometers, capacitive pressure, compass and temperature sensors are among the candidate sensors to be combined on the same chip, e.g., to yield implantable (or wearable) products for the medical field, chips for the consumer or automotive market. Array of Capacitive Micromachined Ultrasonic Transducers are demonstrated for potential medical imaging systems. Key asset for the success of this CMOS-MEMS monolithic approach is the implementation of an hermetic thin film packaging technology. Thin film hermetic SiGe packages are demonstrated with cavity pressure ranging from few Pa up to several 100mBar. This technology has the potential to enable a scaling of the form factors while reducing packaging and testing costs.

Jay Esfandyari has more than 20 years of industry experience in Semiconductor Technology, integrated circuits fabrication processes, MEMS & sensors design and development, sensor networking, product marketing, business development and product strategy. Jay holds a master’s degree and a Ph.D. in Electrical Engineering from the University of Technology of Vienna, Austria. He has more than 60 publications and conference contributions. Jay is currently the Director of MEMS and Analog Product Marketing at STMicroelectronics and he is located in Dallas, Texas.

Simone Severi joined IMEC Leuven in 2007, working on microsystems for mass data storage devices, poly-SiGe surface micromachining technology and CMOS integrated biosensors. In 2009 he became the team leader of the specialty component group at IMEC, with specific focus on MEMS and Bio-Photonics sensors.

Severi received his M.S. degree in microelectronic engineering from the University of Bologna, Italy, in 2001 and his Ph. D degree from the Katholieke Universiteit Leuven in 2006. During his Ph.D course he worked on ultimate device scaling, innovative channel engineering and processing for future CMOS devices technologies.

Register now for this free webcast.


 

The next big thing: IoT

The semiconductor industry has greatly benefited from the push to mobile technology, but what’s next? It could well be the Internet of Things (IoT), which includes smart homes, smart cars, smart TVs, wearable electronics and beacons. According to an analysis by Business Insider, The Internet of Things alone will surpass the PC, tablet and phone market combined by 2017, with a global internet device installed base of around 7,500,000,000 devices.

Source: Business Insider

Source: Business Insider

In a keynote talk at the Advanced Semiconductor Manufacturing Conference (ASMC), John Lin gave some insight into the technology challenges the IoT will create. John is the Vice President and General Manager of Operation of G450C Consortium. Prior to joining G450C, Dr. Lin was the Director of Manufacturing Technology Center in TSMC.

“What is the next big thing?,” he asked? In 2014, after mobile computing, we believe it is the Internet of things. Many of the devices needed to connect to the internet will grow very fast. We need to prepare the technology for that.” John said the ultra-low power will be a primary concern. Processors, sensors and connectivity will also be key. “To support this at TSMC, we will continue with our ultra-low power efforts and continue to support advanced nodes, from 28, 20, 16 to 10nm.” He also said the company will focus on “special” technologies such as image sensor, embedded DRAMs, high-voltage power ICs, RF, analog, and embedded flash. “All this will support all of the future Internet of Things,” he said.

The Business Insider report also notes that the wearables, connected car and tv markets will equal the tablet market by 2018. Smart appliances are already going mass market. More than 250,000 Nest thermostats, for example, have already shipped this year. Connected TVs are overtaking traditional TVs: A connection to the internet will become common in fully loaded cars. US regulators are slowly allowing more aerial drones. Also expect to see more “beacons” in retailer establishments, such as Apple’s iBeacons, which are used to communicate with shoppers in-store.

GLOBALFOUNDRIES’ Kengeri to speak at The ConFab

Subramani Kengeri, Vice President, Advanced Technology Architecture at GLOBALFOUNDRIES will speak at The ConFab 2014 on the “techno-economics” of how the relatively small semiconductor industry ($350 billion or $0.35 trillion) is driving the $85 trillion gross world product (GWP). He notes that semiconductors are only a fraction of GWP, but a critical enabler of global economic growth and productivity. Cost effective technology innovations have kept Moore’s law alive, although techno-economic challenges are mounting on each successive node. The cost of building a new advanced fab has reached $6B. Process development and chip design costs are going up astronomically, while next generation SoCs in the IoT era are pushing cost-per-function to unprecedented levels, he says. His talk will review advanced design and silicon technology challenges posing threats to cost effective scaling, potentially impacting global GWP and productivity. 

Subramani (“Subi”) is responsible for defining competitive process architecture on advanced nodes in support of “first time right” technology development. He is responsible for determining the technology feasibility, competitiveness and manufacturability of all elements of technology platform and to establish the advanced technology roadmap for GLOBALFOUNDRIES.

Subramani joined GLOBALFOUNDRIES in 2009 as the Vice President of Design Solutions. He implemented strategic Design enablement initiatives and established a strong foundation for collaboration with Design eco-system, before moving to focus on R&D. He started his Semiconductor career at Texas Instruments and prior to joining GLOBALFOUNDRIES, he was the Senior Director of Design and Technology Platform at TSMC.

 

What’s new in the latest ITRS

The newly revamped International Technology Roadmap for Semiconductors was released in early April. It’s actually called the 2013 ITRS, which makes it seem already out of date, but that’s the way the numbering has always been.

It’s a big undertaking, with input from the U.S., Europe, Japan, Korea and Taiwan. Through the cooperative efforts of the global chip manufacturers and equipment suppliers, research communities and consortia, the ITRS identifies critical gaps, technical needs, and potential solutions related to semiconductor technology. Some key findings and predictions of the 2013 ITRS include the following:

• The combination of 3D device architecture and low power devices will usher in a new era of scaling identified in short as “3D Power Scaling.” The increase in the number of transistors per unit area will eventually be accomplished by stacking multiple layers of transistors.

• Progress in manipulation of edgeless wrapped materials (e.g., carbon nanotubes, graphene combinations, etc.) offer the promise of ballistic conductors (as shown on this month’s cover), which may emerge in the next decade.

• There will be two additional ways of providing novel opportunities for future semiconductor products. The first consists of extending the functionality of the CMOS platform via heterogeneous integration of new technologies, and the second consists of stimulating invention of devices that support new information-processing paradigms.

The ITRS also covers system level integration, including the integration of multiple technologies in a limited space (e.g., GPS, phone, tablet, mobile phones, etc.).  

Looking at Long Term Devices and Systems (7-15 years horizon, beyond 2020) the 2013 ITRS reports on completely new devices operating on completely new principles and amenable to support completely new architectures. For instance, spin wave device (SWD) is a type of magnetic logic device exploiting collective spin oscillation (spin waves) for information transmission and processing. No surprise, the manufacturing of integrated circuits, driven by dimensional scaling, will reach the few nanometers range well within the 15-year horizon of the 2013 ITRS.

An addition to the 2013 ITRS edition is a new sub-chapter on big data (BD). The fab is continually becoming more data driven and requirements for data volumes, communication speeds, quality, merging, and usability need to be understood and quantified.

IITC: New Materials for Advanced Interconnects

On-chip interconnects have not been scaling at the same speed as transistors. When TSMC went from 20nm to 16/14nm, for example, they decided to replace the bulk MOSFET with a FinFET, but they left the interconnect stack as is. In part, interconnect scaling has been slow because companies don’t want to make too many major changes at the same time and introduce risk. Costs, of course, are also an issue. “When you’ve got ten layers of metal and let’s say six layers of those are close to minimum pitch, it gets very expensive once you start doing double patterning,” said Dr. Deepak Chandra Sekar, general co-chair of the upcoming 2014 IITC/AMC joint conference. “With the interconnect layers, people want to save litho costs. That’s one reason they are not scaling as much as they used to.”

But the major reason is that it’s difficult to make interconnects much smaller without introducing significant increases in resistivity. “If you scale down and your resistivity goes up exponentially, it can be a problem,” Sekar said. “Copper resistivity shoots up when you scale it down because of surface scattering, grain boundary scattering and interface roughness.”

The 17th annual International Interconnect Technology Conference (IITC) will be held May 21 – 23, 2014 in conjunction with the 31st Advanced Metallization Conference (AMC) at the Doubletree Hotel in San Jose, California. It will be preceded by a day-long workshop on “Manufacturing of Interconnect Technologies: Where are we now and where do we go from here?” on Tuesday, May 20.

Sekar highlighted a number of papers that will be presented this year. Many of them focus on new materials that could lead to reduced resistivity and enable further interconnect scaling. “There is a lot of excitement about carbon and carbon-copper composites eventually replacing copper,” he said. “At IITC this year, we have a couple of papers, one on graphene showing lower resistivity than copper, and then one on carbon nanotubes showing good resistivity as well. They are still a bit far out in the sense that there’s a lot more process integration work that needs to be done because these are proof of concept demos, but they show that there might be more beyond copper.”

In a paper from AIST, titled “Sub 10nm wide intercalated multi-layer graphene interconnects with low resistivity,” work will be presented that demonstrates 8nm wide 6.4nm thick graphene interconnects with a resistivity of 3.2uohm-cm, which is significantly better than copper with similar dimensions. This milestone for graphene interconnect research is expected to motivate the process integration research that is required to take the technology to the next level.

8nm wide graphene interconnects

8nm wide graphene interconnects

Carbon nanotubes (CNTs) have been explored as a material for vertical interconnects for many years since they can handle higher current densities than copper and offer ballistic transport. A paper from imec titled “Electron Mean Free Path for CNT in Vertical Interconnects Approaches Copper,” work will be presented that demonstrates a 5x improvement in electron mean free path for CNTs compared to previous work. The CNT mean free path of 24-74nm approaches copper. Contact resistance is improved significantly compared to previous work as well.

Carbon Nanotube (CNT) vias in integrated structures

Carbon Nanotube (CNT) vias in integrated structures

Another challenge to scaling of interconnects: reliability. Both time-dependent-dielectric-breakdown (TDDB) and electromigration lifetimes for interconnects drop rapidly when scaled. In work to be presented at IITC/AMC, IBM and Applied Materials will present a multi-layer SiN cap process is developed that shows higher breakdown and lower leakage compared to conventional SiCNH caps. Selective cobalt caps in combination with the multi-layer SiN cap are shown to provide a 10x improvement in electromigration lifetimes. Wrap-around cobalt liners in combination with the cap layer schemes are shown to provide a 1000x improvement in electromigration lifetimes. The paper is titled “Advanced Metal and Dielectric Barrier Cap Films for Cu Low k Interconnects.”

10x improvement in electromigration lifetimes with multi-layer SiN and selective cobalt cap layers. 1000x improvement in electromigration lifetimes with multi-layer SiN cap, cobalt cap and wrap-around cobalt liners.

10x improvement in electromigration lifetimes with multi-layer SiN and selective cobalt cap layers. 1000x improvement in electromigration lifetimes with multi-layer SiN cap, cobalt cap and wrap-around cobalt liners.

Of course, an alternative to making everything smaller by scaling is to go 3D. That will be addressed by a variety of papers, including one from CEA-Leti focused on 3D monolithic integration. While most of today’s through-silicon vias (TSVs) are in the 5µm range, monolithic 3D technologies offer TSVs in the 50nm range, which allows dense connectivity between different layers in a 3D-IC. In the Leti paper, such dense connectivity is shown to provide 55% area reduction and 47% energy-delay product improvement for a 14nm FPGA design. Transistor technologies that allow monolithic 3D integration are experimentally demonstrated. “When you make the TSVs smaller and smaller, you can reduce the length of on-chip wires as well by taking what’s on a single now and stacking them into two layers,” Sekar said. “That might save a lot of power and area. There’s been a lot of talk about monolithic 3D, but these are some of the first few experimental demonstrations showing that it’s possible.”

Monolithic 3D-ICs

Monolithic 3D-ICs