Author Archives: psinger

IITC: New Materials for Advanced Interconnects

On-chip interconnects have not been scaling at the same speed as transistors. When TSMC went from 20nm to 16/14nm, for example, they decided to replace the bulk MOSFET with a FinFET, but they left the interconnect stack as is. In part, interconnect scaling has been slow because companies don’t want to make too many major changes at the same time and introduce risk. Costs, of course, are also an issue. “When you’ve got ten layers of metal and let’s say six layers of those are close to minimum pitch, it gets very expensive once you start doing double patterning,” said Dr. Deepak Chandra Sekar, general co-chair of the upcoming 2014 IITC/AMC joint conference. “With the interconnect layers, people want to save litho costs. That’s one reason they are not scaling as much as they used to.”

But the major reason is that it’s difficult to make interconnects much smaller without introducing significant increases in resistivity. “If you scale down and your resistivity goes up exponentially, it can be a problem,” Sekar said. “Copper resistivity shoots up when you scale it down because of surface scattering, grain boundary scattering and interface roughness.”

The 17th annual International Interconnect Technology Conference (IITC) will be held May 21 – 23, 2014 in conjunction with the 31st Advanced Metallization Conference (AMC) at the Doubletree Hotel in San Jose, California. It will be preceded by a day-long workshop on “Manufacturing of Interconnect Technologies: Where are we now and where do we go from here?” on Tuesday, May 20.

Sekar highlighted a number of papers that will be presented this year. Many of them focus on new materials that could lead to reduced resistivity and enable further interconnect scaling. “There is a lot of excitement about carbon and carbon-copper composites eventually replacing copper,” he said. “At IITC this year, we have a couple of papers, one on graphene showing lower resistivity than copper, and then one on carbon nanotubes showing good resistivity as well. They are still a bit far out in the sense that there’s a lot more process integration work that needs to be done because these are proof of concept demos, but they show that there might be more beyond copper.”

In a paper from AIST, titled “Sub 10nm wide intercalated multi-layer graphene interconnects with low resistivity,” work will be presented that demonstrates 8nm wide 6.4nm thick graphene interconnects with a resistivity of 3.2uohm-cm, which is significantly better than copper with similar dimensions. This milestone for graphene interconnect research is expected to motivate the process integration research that is required to take the technology to the next level.

8nm wide graphene interconnects

8nm wide graphene interconnects

Carbon nanotubes (CNTs) have been explored as a material for vertical interconnects for many years since they can handle higher current densities than copper and offer ballistic transport. A paper from imec titled “Electron Mean Free Path for CNT in Vertical Interconnects Approaches Copper,” work will be presented that demonstrates a 5x improvement in electron mean free path for CNTs compared to previous work. The CNT mean free path of 24-74nm approaches copper. Contact resistance is improved significantly compared to previous work as well.

Carbon Nanotube (CNT) vias in integrated structures

Carbon Nanotube (CNT) vias in integrated structures

Another challenge to scaling of interconnects: reliability. Both time-dependent-dielectric-breakdown (TDDB) and electromigration lifetimes for interconnects drop rapidly when scaled. In work to be presented at IITC/AMC, IBM and Applied Materials will present a multi-layer SiN cap process is developed that shows higher breakdown and lower leakage compared to conventional SiCNH caps. Selective cobalt caps in combination with the multi-layer SiN cap are shown to provide a 10x improvement in electromigration lifetimes. Wrap-around cobalt liners in combination with the cap layer schemes are shown to provide a 1000x improvement in electromigration lifetimes. The paper is titled “Advanced Metal and Dielectric Barrier Cap Films for Cu Low k Interconnects.”

10x improvement in electromigration lifetimes with multi-layer SiN and selective cobalt cap layers. 1000x improvement in electromigration lifetimes with multi-layer SiN cap, cobalt cap and wrap-around cobalt liners.

10x improvement in electromigration lifetimes with multi-layer SiN and selective cobalt cap layers. 1000x improvement in electromigration lifetimes with multi-layer SiN cap, cobalt cap and wrap-around cobalt liners.

Of course, an alternative to making everything smaller by scaling is to go 3D. That will be addressed by a variety of papers, including one from CEA-Leti focused on 3D monolithic integration. While most of today’s through-silicon vias (TSVs) are in the 5µm range, monolithic 3D technologies offer TSVs in the 50nm range, which allows dense connectivity between different layers in a 3D-IC. In the Leti paper, such dense connectivity is shown to provide 55% area reduction and 47% energy-delay product improvement for a 14nm FPGA design. Transistor technologies that allow monolithic 3D integration are experimentally demonstrated. “When you make the TSVs smaller and smaller, you can reduce the length of on-chip wires as well by taking what’s on a single now and stacking them into two layers,” Sekar said. “That might save a lot of power and area. There’s been a lot of talk about monolithic 3D, but these are some of the first few experimental demonstrations showing that it’s possible.”

Monolithic 3D-ICs

Monolithic 3D-ICs

Extreme Stress for Existing Foundry/Fabless Model

Dr. Roawen Chen, senior vice president of global operations at Qualcomm, will provide the keynote talk at The ConFab 2014 this year. The event will be held June 22-25 at The Encore at The Wynn in Las Vegas.

In his talk, Dr. Chen, will describe how the increased performance and the rapid shift from traditional handsets to consumer computing device post a number of manufacturing and supply chain challenges for fabless chip makers. He says the scale of the challenges also creates an “extreme stress” for the existing foundry/fabless model to defend its excellence in this dynamic landscape. In this talk of “what’s on our mind?” he will deliberate on a number of headwinds and opportunities.

In his role at Qualcomm, Roawen oversees the worldwide operations and supply chain, silicon and package technology, quality/reliability, and procurement functions for the Qualcomm semiconductor business. He has overall responsibility for driving the global integrated fabless strategy and execution.

Roawen is an experienced leader in all aspects of semiconductor operations and supply chain management with a solid background in leading large-scale fabless operations. In addition to his strong technical depth, he has proven experience in building close supplier and vendor relationships and executing to support customer demand and product development. Prior to Qualcomm, Roawen was Vice President of Manufacturing Operations at Marvell Semiconductor in Santa Clara, California. During his more than 12 years at Marvell, Roawen held a variety of leadership roles, including Vice President and General Manager of the Communications and Computing business unit and Vice President and General Manager of the Connectivity business unit. He has also served in management roles in Marvell’s Foundry Operations and Manufacturing Technology groups.

Prior to Marvell, Roawen held technical positions at TSMC-USA and Intel. He earned a bachelor’s degree in Physics from National Tsing-Hua University in Taiwan, a master’s degree in Materials Science from the University of California, San Diego and a PhD in Electrical Engineering and Computer Science from the University of California, Berkeley.

At The ConFab 2014: The Outlook for the Semiconductor Industry

The semiconductor market will continue at a steady growth rate for the next several years. For a semiconductor company to achieve significant growth in this ultra-competitive environment, it needs to identify market opportunities and predict the future, in terms of markets, both regionally and globally, anticipate technological advancements, as well as envision new applications. At The ConFab in June, Session 1 will provide an overview of these critical issues.

The presenters will be:

Vijay Ullal, COO, Fairchild Semiconductor

Dave Anderson, President and CEO, Novati Technologies

Gopal Rao, Senior Director Business Development, SEMATECH

Adrian Maynes, Program Manager, F450C

Bill McClean, President, IC Insights

Here’s an overview of what each presenter plans to cover:

The Economics of Semiconductor Manufacturing and the Escalating Cost of R&D

Vijay Ullal, COO, Fairchild Semiconductor

While innovation in semiconductor technology is driving change in industries from automotive to mobile, and the sophistication of computers, mobile devices, automobiles, industrial systems and consumer goods evolves, greater pressure is placed on semiconductor research and development (R&D) as well as Supply Chain Management (SCM). Now, the bar has been raised from not only delivering leading-edge technology, but also to delivering far greater value to an organization. This presentation will use examples of to focus R&D as well as revitalize your supply chain in order to highlight your competitive advantages, and better meet these market place demands by moving beyond the “product sell” to an approach that focuses instead on the key attributes customer’s value.

More-than-Moore: A New Era of Innovation

Dave Anderson, CEO, Novati Technologies

The semiconductor industry has focused on Moore’s Law for more than 40 years in its quest for ever shrinking geometries to squeeze more transistors on a chip and improve device speed and performance.  Digital microcircuits have benefited immensely from this extreme scaling but, with fewer companies having the ability to support further scaling, More-than-Moore (MtM) has emerged to apply decades of semiconductor process knowledge to novel applications to produce state-of-the-art biochips, sensors, actuators, imagers and more. Perhaps most importantly, MtM technology is enabling companies to build these components more cost-effectively and with better performance and smaller size than ever before.

Providing a significant advantage over traditional volume foundries, a new wave of boutique nanotechnology development centers is in a unique position to integrate new materials with custom processes. This provides a rapid acceleration of development and production for world-leading ideas and breakthrough MtM products.

The result is a new era of innovation that couples the best of the past with future demands to create valuable applications and markets. The era for enabling the most rapid, but affordable, new product development and deployment has begun.

Enabling the Supply Chain to Accelerate R&D

Gopal Rao, Senior Director of Business Development, SEMATECH

There is a push/pull market energy that is now, more than ever, influencing the device makers, suppliers and the consumers who are thirsty for innovative mobile computing and connected devices. The IC industry has relied on a push based roadmaps to bring products to market. It is important that we acknowledge that the consumer appetite for innovative and cool products has created a pull system that may be considered a roadmap. The challenge facing the whole IC industry is how to recognize, rationalize and leverage these push/pull roadmaps. This talk examines this IC industry challenge and opportunity, specifically in moving the vast supply chain to feed into this fast moving market. The pace of R&D through entire supply chain is essential in staying ahead of the curve and driving down cost of technology and manufacturing. Radical, innovative product designs to meet consumer demand will push into the IC supply chain the need to identify and develop significant cost/performance improvements in IC device performance. What are these improvements? Are the current roadmaps highlighting them or do we need to better, integrated intelligent roadmap that helps the supply chain stay on treadmill of innovation and cost reduction?

450mm Transition towards Sustainability: Facility & Infrastructure Requirements

Adrian Maynes, F450C Program Manager

It is widely accepted that in the next few years the semiconductor industry will begin to transition to the next generation 450mm wafer size. Experts throughout the semiconductor industry are striving to make 450mm a reality from a technical and manufacturing standpoint. Along with the increase in wafer size, the industry is closely examining impacts to the facility infrastructure, as merely scaling the manufacturing process is not a practical option. The size of the 450mm facility infrastructure and its associated utility consumption projections would simply exceed affordability and resource availability.

The facility experts involved in establishing and later implementing 450mm infrastructure requirements are facing the same degree of challenges as the IC and equipment manufacturers. For the first time in semiconductor history, facility professionals are collaborating closely with the industry’s top five consolidated IC manufacturers to bring their collective expertise to bear on the most pressing 450mm fab issues. With special focus on safety, cost, schedule, sustainability, and environmental footprint, this global consortium of industry specialists is aiming to reduce the cost of production, increase productivity for manufacturers, and reduce the environmental footprint on a per chip basis

This presentation will address these various infrastructure requirements and potential issues for a more sustainable manufacturing process. The session will be co-presented by leaders of the Facilities 450mm Consortium (F450C) and the Global 450mm Consortium (G450C). These two groups are collaborating as experts from across the entire supply chain to ensure a smooth transition to the 450mm technology.

Major Trends Impacting the IC Industry of the Future

Bill McClean, Presdient, IC Insights

IC Insights forecasts that 2014 will continue the integrated circuit industry cyclical upturn that began in 2013.  This cyclical upturn is expected to gain momentum over the next several years, resulting in a 6.4% IC market CAGR over the 2013-2018 time period, which would be more than 3x the 1.7% CAGR the IC market displayed from 2007-2012. Although a high level of uncertainty still looms over the global economy, sales of smartphones and tablet PCs continue to soar.  IC Insights will present its forecast for the IC market in the context of the IC industry cycle model.  In order to make sense out of the current turmoil, a top-down analysis of the IC market will be given and include trends in worldwide GDP growth, electronic system sales, and semiconductor industry capital spending and capacity.

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The ConFab R&D Panel is Set

A panel session at The ConFab, to be held June 22-25 in Las Vegas, will focus on how the semiconductor industry can continue to innovate in an environment where lower revenue growth is combined with rising development costs and consolidation.  The panel will discuss where the next big growth drivers will come from and the ability of the industry to continue scaling and remain on Moore’s Law through the introduction of new technologies such as EUV, Advanced Packaging and 450mm.  How will the costs to develop these and other technologies affect innovation and what levers can be utilized to gain more efficiencies in R&D.  The panel will also discuss what role startups will play in the industries going forward and how can increased collaboration benefit the industry. 

The panel, to be moderated by Scott Jones of Alix Partners, will consist of:

Rory McInerny, Vice President Platform Engineering Group, Intel

Chris Danely, Senior Analyst, JP Morgan

Mike Noonen, Co-founder, Silicon Catalyst

Lode Lauwers, Senior Director of Business Development, imec

Some of the subjects that will be covered:

Where does do the next growth drivers come from?

When will wearables, medical devices and the internet of things really drive revenue growth?

What challenges do we have on the R&D side in servicing the growth areas more quickly?

How are the costs of scaling and the development costs of SOCs affecting growth?

What advances from the chip design and architecture side are compensating for the challenges in scaling?

What view does the institutional investing community have on investing in innovation versus acquiring it?

What is the state of the Start-up environment in Semiconductors?

How do we leverage collaboration more to improve on our return on R&D investment?

Click here for more information on The ConFab 2014 agenda.

Webcast on 3D Integration/Advanced Packaging, Lithography

If you’ve been following the field of 3D integration for any time at all, then you’re familiar with Sitaram Arkalgud. In addition to being a great guy, he led the charge on 3D integration at SEMATECH in the early days. He’s now at Invensas and I’m very much looking forward to hearing from him again, this Thursday at 1:00 Eastern. You can hear from him too, by tuning into our webcast. But first you’ll have to register: https://event.webcasts.com/starthere.jsp?ei=1032084

Sitaram will be joined by Rich Rogoff, vp and general manager of the Lithography Systems Group at Rudolph Technologies. Rich recently wrote an interesting article “A square peg in a round hole: The economics of panel-based lithography for advanced packaging” and he’s going to expand on that in the second part of the webcast on Thursday.

Here’s a little more information on the webcast, Sitaram and Rich.

2.5/3D integration and advanced packaging enable better chip performance in a smaller form factor, meeting the needs of smartphones, tablets, and other advanced devices. However, 2.5/3D packaging creates a new set of manufacturing challenges, such as the need to fabricate copper pillars, TSVs, wafer bumping and redistribution layers – which may involve thicker photoresists, spin-on dielectrics and BCB coatings — and processing may be done on panels instead of round wafers. In this webcast, experts will detail various options, future scenarios and challenges that must still be overcome.

Sitaram Arkalgud is Vice President, 3D technology at Invensas Corp., where he leads the company’s 3D-IC research and development efforts. Prior to Invensas, he started and led 3D-IC development at SEMATECH, where the focus was on delivering manufacturable process technologies for 3D interconnects. Previously, Sitaram worked in a variety of roles spanning R&D and manufacturing in memory and logic technologies at Infineon/Qimonda and Motorola. He is the author of several publications and holds 14 U.S. patents. Sitaram holds a master’s degree and a Ph.D. in materials engineering from Rensselaer Polytechnic Institute in Troy, N.Y., and a bachelor’s degree in metallurgical engineering from Karnataka Regional Engineering College, Surathkal, India.

Richard Rogoff is Vice President and General Manager of the Lithography Systems Group at Rudolph Technologies. Prior to joining Rudolph he spent 23 years with ASML in various executive, operational and engineering positions. Most recently he served as Vice President of ASML optics business unit. He received a B.S. in Microelectronic Engineering from Rochester Institute of Technology and a M.B.A. from INSEAD Business School.

Qualcomm’s Dr. Roawen Chen to keynote at The ConFab

I’m delighted to report that Dr. Roawen Chen, Senior Vice Present of global operations at Qualcomm, has accepted our invitation to deliver the keynote talk at The ConFab, on Monday June 23rd. As previously announced, Dr. Gary Patton, Vice President of IBM’s Semiconductor Research and Development Center in East Fishkill, New York, will deliver the keynote on the second day, on Tuesday June 24th. I’m thrilled to have these two visionaries speak to The ConFab audience.

In his role at Qualcomm, Roawen oversees the worldwide operations and supply chain, silicon and package technology, quality/reliability, and procurement functions for the Qualcomm semiconductor business. He has overall responsibility for driving the global integrated fabless strategy and execution.

Roawen is an experienced leader in all aspects of semiconductor operations and supply chain management with a solid background in leading large-scale fabless operations. In addition to his strong technical depth, he has proven experience in building close supplier and vendor relationships and executing to support customer demand and product development. Prior to Qualcomm, Roawen was Vice President of Manufacturing Operations at Marvell Semiconductor in Santa Clara, California. During his more than 12 years at Marvell, Roawen held a variety of leadership roles, including Vice President and General Manager of the Communications and Computing business unit and Vice President and General Manager of the Connectivity business unit. He has also served in management roles in Marvell’s Foundry Operations and Manufacturing Technology groups.

Prior to Marvell, Roawen held technical positions at TSMC-USA and Intel. He earned a bachelor’s degree in Physics from National Tsing-Hua University in Taiwan, a master’s degree in Materials Science from the University of California, San Diego and a PhD in Electrical Engineering and Computer Science from the University of California, Berkeley.

The ConFab will be held June 22-25 at The Encore at The Wynn in Las Vegas.

Dr. Gary Patton to provide keynote at The ConFab

I’m very pleased to announce that IBM’s Dr. Gary Patton will provide the keynote talk at The ConFab on Tuesday, June 24th. Gary is Vice President of IBM’s Semiconductor Research and Development Center in East Fishkill, New York. He has responsibility for IBM’s semiconductor R&D roadmap, operations, and technology development alliances, with primary locations in East Fishkill, New York, Burlington, Vermont, and the Albany Nanotech Research Center in Albany, New York. During his career at IBM, Dr. Patton has held various management and executive positions in IBM’s Microelectronics, Storage Technology, and Research Divisions, including positions in technology and product development, manufacturing, and business line management. Dr. Patton received his B.S. degree in electrical engineering from UCLA and his M.S. and Ph.D. degrees in electrical engineering from Stanford University. He is also a Fellow of the IEEE.

After Gary’s keynote, we’ll have a panel session focused on R&D collaboration. Moderated by Scott Jones of Alix Partners, the panel will include Rory McInerney, VP of the platform engineering group at Intel; Chris Danely, the Managing Director and global coordinator for J.P. Morgan’s semiconductor research team; and Mike Noonen, co-founder of Silicon Catalyst, the industry’s first semiconductor startup “incubator”.

It promises to be a very interesting morning! The ConFab will be held June 22-25 at The Encore at The Wynn in Las Vegas.

Mission accomplished. Now what?

In the late ‘80s and ‘90s, when our magazine staff gathered for dinner we often made a toast: “Here’s to chip silicon!” I really believed (and still do) that making electronics more affordable would increase their use and make our lives better and the world a better place to be.

I haven’t toasted to cheap silicon for a while. Why? Because that mission has been accomplished.

At SEMI’s ISS, Paul Farrar, manager of the G450C consortium put the industry progress over the last 40+ years in perspective. “1 Megabyte of memory in 1970 was $750,000. It was sold as an IBM add-on,” he said. “The great technology was made of 57mm wafers, five masking levels, and one level of metal. Today, it’s is less than a penny. That is a 100 million X improvement.”  

Of course, most people would like to see this trend continue, but it’s highly unlikely that we’ll see such dramatic progress. Scaling is getting too expensive. The transition to 450mm looks feasible from a technical standpoint (see my column on pg. 10) but it’s not yet clear if it will be less expensive than 300mm, particularly when you factor in 450mm lithography. 

So if the scaling mission is accomplished, what’s next? There’s exploding interest in the “Internet of Things” where almost everything is tagged and connected. That will require some big upgrades in the server/network infrastructure, but that can be done with existing technology. It will also require inexpensive sensors and wireless communication. By some estimates, the technology to achieve that is not ready. We need about a 10X improvement in price/performance. Ditto for wearable electronics and a whole host of applications in medical, automotive and the smart grid.

In the future, perhaps electronics will be printed like potato chip bags on roll-to-roll machines with ink-jet-like deposition of materials. Perhaps tiny MEMS with integrated sensors, thin-film batteries, energy harvesting, microprocessors and other functions will be produced for less than a penny. Perhaps everyone will have inexpensive body area networks embedded in their clothing that constantly monitor their health.

It’s all possible, but it will take some innovation in processing equipment and materials.

Take the NCMS survey, but first figure out your nano position

I recommend taking the new survey out by the National Center for Manufacturing Sciences (NCMS) – www.usnanosurvey.org — but you may first want to give some thought as to what is and what isn’t “nanotechnology.” That’s been something of a puzzle for the semiconductor and related industries over the last 10+ years. Some put semiconductor manufacturing, where matter is regularly manipulated on an atomic scale, squarely in the nanotechnology camp. Judging by Nanotechnology Initiative (NNI) definitions, this is surely the case: “Nanotechnology is the creation, characterization and application of novel materials, devices and systems by control or restructuring of matter at dimensions of roughly 1 – 100 nanometers,” read the NNI definition, which includes nanomanufacturing as “the repeatable building of materials, structures, components, devices and systems designed with nanoscale features.”

Others say no, that’s just really small, it’s only nanotechnology when it takes advantage of the very unique properties of carbon nanotubes, silicon nanowires, quantum dots and other materials and structures which operate on the nanoscale.

Of course, compounding the confusion is the chase for nanotechnology-earmarked funding. Seven or eight years ago, it seems as if overnight everything that was branded semiconductor technology was relabeled as nanotechology. Although it seems to be the fervor has died down a bit, there’s clearly been been increased interest in materials such as CNTs and silicon nanowires in the semiconductor industry lately, particularly as the search for next generation “gate-all-around” transistors and post-CMOS switching technology heats up.

Perhaps there are ways for the U.S. government to help fund such efforts? Figuring that out is one of the goals of the survey.

Themed “Achieving Sustainable Nanotechnology Products,” the goal of the 2014 study is to document best practices in nano-product development and integration, and identify the common challenges organizations (academia, government labs, start-ups or established corporations) face in transitioning nano-scale advances from the laboratory into sustainable commercial applications. Due to the importance of the subject and massive public-private investments made in nanotechnology, NCMS is polling a broad cross-section of U.S. industry.

For this survey, “sustainable nanotechnology products” are defined as market-oriented products engineered by leveraging nano-scale features using materials and processes that minimize negative environmental impacts, conserve energy and resources, are safe for employees, end-users and consumers, and are economically sound.

You are urged to the brief survey if your organization’s activities in nanotechnology meet one of the following National Nanotechnology Initiative (NNI) definitions:

Nanotechnology is the creation, characterization and application of novel materials, devices and systems by control or restructuring of matter at dimensions of roughly 1 – 100 nanometers.

Nanomanufacturing is the repeatable building of materials, structures, components, devices and systems designed with nanoscale features.

The National Center for Manufacturing Sciences (NCMS) has partnered with the National Science Foundation under the National Nanotechnology Initiative (NNI) to launch this latest study of commercialization trends in nanotechnology and nanofabrication– previous studies were performed in 2003, 2006 and 2009.

In the 2009 study, aggregate results indicated that nearly 25% respondents’ organizations were already marketing products and instruments incorporating nanotechnology, and about 85% expected to commercialize products by 2013. Current applications were dominated by nanomaterials (e.g. nano-structured catalysts, carbon nanotubes, quantum dots, nanowires and dopants), complementary metal-oxide semiconductor (CMOS)-based electronics/semiconductor manufacturing processes, as well as other silicon-based energy conversion process industries that leverage similar large-scale fabrication equipment, thin-film coating processes, and closed-environment handling systems. Diverse nanotechnology-enabled, miniaturized biomedical and diagnostic devices, designer drugs and targeted therapies were also progressing, with early products such as nanoemulsions and viricides in advanced clinical trials.

Senior executives and researchers in stakeholder organizations are encouraged to share their experience and opinions about nanotechnology development in the U.S. Individual responses are kept confidential and the data will only be used in the aggregate. NCMS’ insightful reports are widely distributed to federal and state agencies, and elected representatives. All survey respondents will receive the insightful study results in advance of public release this summer. The 15-minute interactive survey may be accessed at www.usnanosurvey.org until March 15, 2014. www.usnanosurvey.org

Questions cover the stage of your commercial entity, the top 3 goals, the urgency of your commercialization efforts, overall capacity, infrastructure, prioritization challenges and what you view as the government’s role in the development of nanotechnologies.

Although the survey is directed at U.S.-based companies, all are welcome to participate.

No technical barriers seen for 450mm

Paul Farrar, general manager of the G450C consortium, said early work has demonstrated good results and that he sees no real barriers to implementing 450mm wafers from a technical standpoint. Speaking at the SEMI ISS meeting in January, Farrar showed impressive results from, etch, CVD, PVD, CMP, furnaces, electroplating, wet cleans and lithography processes and said the inspection/metrology tools were in place to measure results. “I don’t believe we will find fundamental technology limiters,” he said. “But we will have to keep working to find ways to maximize the efficiency.” Gaining such efficiencies are critical in order to meet the cost-saving goals of the program. “In the end, if this isn’t cheaper, no one is going to do it,” he said.

G450C is a consortium based at the CNSE campus in Albany, NY. It is financed by Intel, TSMC, Samsung, IBM, GLOBALFOUNDRIES, and New York State (CNSE). “Our job is to make it as easy as possible to innovation and be collaborative between the semiconductor makers and our key friends in the industry who enable the 450 work to be done in an economic way,” Farrar said.

At the end of 2013, G450C at 34 tools delivered to its 50,000ft2 fab in Albany, with another 7 tools in place at partner’s facilities. “The FOUPS are going, the overhead transport is well underway and some of the cleanroom is actually starting to look like a cleanroom,” Farrar said.

FarrarISS_F3

Farrar started with etch results, saying they were “starting to see some pretty good data – 3 sigma at about 2%. Yes, there’s still some work to get to the very edge of the wafer but relatively good progress and good jobs on gas delivery, etc.

FarrarISS_F6

He showed good results with both oxide and silicon nitride CVD, with close to 1.5mm edge exclusion. “It’s very representation data from early in the program,” Farrar said, noting that they were starting to pattern some of the more complex oxides.

FarrarISS_F7

He said the goal for PVD was to demonstrate better than 5% uniformity. “We know we have step coverage challenges for both the 10 and 7nm nodes. There’s tremendous work going on in the injection rings for gases, high density plasmas from multiple RF sources, but again some progress to me made but pretty good data for right out of the chute,” he said.

FarrarISS_F8

CMP results demonstrated repeatability less than 4%. “Very good job done by our suppliers,” Farrar said.

FarrarISS_F9

Farrar described data from furnaces as reasonably good. “We still need to do more characterization at what I call the micro level,” he said. “We see some hot spots on the edge, but we’re starting to work on those.”

FarrarISS_F10

Also “pretty good data” from electrochemical plating (ECP) of copper. “Well done here,” Farrar said. “The challenge is thermal and pattern loading effects, and gap fill.”

FarrarISS_F11

More of the same with wet cleans. “We’re starting to see some pretty good particle data. We’re cleaning wafers relatively well. We are seeing a few things like what I would call micro-metallic contamination that can grow some things so we’re still working on that. But from a particle removal standpoint, pretty good unit process work,” Farrar said.

FarrarISS_F12

Farrar acknowledged that lithography remained as one of the biggest challenges in the 450mm transition, but showed good results from directed self assembly across a 450mm wafer, and said the consortium had a very strong partnership with Nikon. “We’re working with them and we’ve seen some tremendous progress at their factory,” he said. “I’m fully confident that we’ll have capability by July to run patterned wafers. Immersion is going to be the workhorse. I think that’s a key enabler to get to 450mm.” He said the industry would have to see how the economics of EUV played out later in time. “I don’t think it’s going to be early in time,” he said.

FarrarISS_F13FarrarISS_F14

Farrar seemed to draw hope from the earlier transition from 200mm to 300mm wafers, which started around 1998.  “By 2008, we were getting more than 2X the number of wafers per tool out compared to what was going in 2003. There was about a 70% improvement over 5 years,” he said.