Author Archives: psinger

50 years ago: February 1964

In February of 1964, The Beatles landed for the first time at JFK in New Work and appeared on the Ed Sullivan show on February 9th. Their song “I want to hold your hand” – their 1st #1 hit – was still #1 after 7 weeks.  France & Great-Britain signed an accord over building the channel tunnel (construction for the “chunnel” began in 1988; it opened in 1992). The GI Joe toy (it is not a doll!) was introduced to the U.S. market.

In the electronics arena, it was a time when undersea telephone cables were being installed. In the February 1964 issue of Solid State Technology, Bell Laboratories described scientific advances that made possible a telephone cable system across the Atlantic Ocean. “In service beginning October 14, 1963, it transmits 128 simultaneous two-way telephone conversations,” an ad boasts. “In 1964, a cable of this kind will be laid between Hawaii and Japan, providing an extension across the Pacific Ocean of the telephone cable system now in service to Hawaii.”

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In the area of R&D, the development of two experimental NPN transistors for solid-state memory applications was reported by scientists of IBM. From the 1964 issue: “One of the transistors is a high voltage, high speed, medium power device; and the other is an ultra-fast, medium power, low voltage device. Both are silicon, epitaxial, planar, double-diffused types. The high voltage transistor is capable of switching 600 mA of current through a 90V swing in less than 25 ns.The low-voltage device can switch one ampere of current through a 25V swing in less than 8 ns.” The developments were described at the 1963 meeting of the IEEE Profession Group on Electron Devices in two papers, presented by P. P. Castrucci.  I believe that has to be the same Paul P. Castrucci who went on to start IBM’s 200mm line. I knew him personally and enjoyed his many stories, many of which are recounted in a discussion for the Computer History Museum.

Sadly, Paul passed away in June of last year.

Another interesting story in February 1964: How solid state electronics helped save space at the Voice of America (the official external broadcast institution of the U.S. federal government) installation in Bethany, Ohio. The Bethany Relay Station operated from 1944 to 1994. In 1962, high voltage stacks replaced the expensive 870A and 872A tubes.

The February Solid State Technology contained features on GaAs IR emitters, tunnel diode amplifiers, and an article focused on the ways to determine thermal resistance by flux plotting.

The Editorial examined the potential of thermionic energy converters. “The observation of the Edison effect, a phenomenon describing the collection of electrons emitted from a thermionic cathode, may be considered the starting conception of a family of energy converters which have no moving parts and which are being developed rapidly to achieve efficiency better than 10 percent and power outputs in the order of hundreds of watts.” Sam Marshall wrote that in 1964. 50 years later, the potential is still being explored,” wrote Sam Marshall.

Today, 50 years later, the potential of these devices is still being explored today. Stanford University and the SLAC National Accelerator Laboratory, are working on applying thermionic energy convertors to applications in the field of Concentrating Solar Power (CSP).  The research team is creating a “new solid-state energy conversion technology based on microfabricated and photon-enhanced thermionic energy converters (PTECs). When used as a topping cycle in concentrated solar thermal electricity generation, PTECs will enable system efficiencies in excess of 50%.”

Microscale-enhanced thermionic emitters will enable high efficiency solar to electrical conversion by taking advantage of both heat and light.

Microscale-enhanced thermionic emitters will enable high efficiency solar to electrical conversion by taking advantage of both heat and light.

The goals of this project are to:

    Design thermally isolated thermionic arrays and microelectromechanical systems (MEMS)-based wafer-stack technologies for PTEC fabrication that could exceed the SunShot Initiative targets for system conversion efficiency and cost

    Fabricate heterostructure semiconductor cathodes based on active-layer absorbers with the addition of band-engineered passivating layers to demonstrate PTECs with high quantum efficiency

    Demonstrate a next-generation thermionic energy converter device with a stand-alone laboratory efficiency >15% as a significant intermediate step toward a stand-alone unit of >30%.

“Through the use of modern design tools and wafer-scale microfabrication methods, this project is demonstrating for the first time a manufacturable approach to thermionic energy converter production that overcomes the space-charge-induced efficiency limitations of traditional thermionic devices. Also, through the novel application of appropriately designed and fabricated semiconductor heterostructure cathodes, the efficiency is being further improved by the photon-enhanced thermionic emission process,” a press release notes. Interesting, but I’d like to know why it’s taken 50 years to get there.

Check out a few of the ads from the issue:

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High cost per wafer, long design cycles may delay 20nm and beyond

Handel Jones, founder and CEO of International Business Strategies (IBS), spoke at SEMI’s Industry Strategy Symposium last week, focusing on key trends, factors impacting the growth of the industry and the migration to smaller feature dimensions. He is bullish about 2014 and industry innovation, but cautious about how quickly the industry will move to new technology nodes due to higher costs, and long design cycles. Overall, he said he believed semiconductor market growth this year will be slightly better than 2013, due in part to the strength of the global GDP.

Perhaps most surprisingly, he had a fair amount of uncertainly about 20nm.  “Will 20nm be a high tech technology node and when will that occur?” he said. “We’re tracking design starts and design completions and we see a few 20nm designs but not a lot. Frankly, whether 20nm will be big or not will really depend on two customers: one is Qualcomm and the other is Apple.” Handel said “there is a significant challenge in getting lower cost at 20nm” compared to 28nm due to a lack of increase in the gate density and the potential yield impact. “We think 20nm, if it does go into volume production, it will not be in 2014. Potentially 2015 and maybe 2016,” he said.

Similarly, Handel believes there will be a postponement of 16/14nm. “We expect initial production in late 2016, beginning of 2017. That’s for the SoC business. The FPGA markets will be different,” he said. “There will also be delays in 10nm. Delays mean you can’t really go on the 2 year cycle or even the 3 year. I know people will vehemently disagree with that, but if you look at what’s really happening from a design start point of view and also the end customers, I think you’ll agree with our conclusion,” he said.

“If you look at the reality of the industry, 28nm high-k metal gate went into high volume production toward the end of 2013,” said, adding that they define high volume as 10% of the output. “It took almost 4 years for 28nm high-k metal gate to go into high volume production. Now we’re basically starting 20nm. Even if the fabs are ready what you have is the design cycle time. Preparing libraries and IP can take six months at least. Doing a complex design in 20nm can take you at least a year. Validating the design can take you another half a year. If it’s a modem, and you need approval from the carriers, that’s another half a year. Even if the fab is ready, you start these things and it’s two years,” he said. “We have an industry that is trying to adopt three technologies in three years. It’s impossible,” he said. “It’s not realistic from an infrastructure point of view, even if it the fabs are there, for three technology nodes to ramp in three years.”

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Handel said that application processor (AP)/modem design can cost about $450-500 million in 16/14nm, with a timeframe of around 18 months. “You need 10X revenue so for that design, so if you’re spending $450 million, you need $4.5 billion in revenue. A few companies can get that, but not many,” he added.

“The economics of the industry are forcing changes. You’ve seen them already. The long ramp up time for 28nm HKMG, and 20nm with double patterning is clearly a major challenge from a technology point of view, and a bigger challenge from a cost point of view. FinFETs will be an even bigger challenge. Intel is having delays in their 14nm FinFETs, whether in high volume at 22nm, how will companies that have never done FinFETS before, how will design companies that have never designed in FinFETs before, how will they ramp faster?” he asked.

 Not surprisingly, Handel also had a dim outlook for 10nm. He estimates that 10,000 wafers/month at 10nm will cost more than $2billion. “If you want to install 40,000 wafers/month, it’s going to be an $8 billion bill. If you want to install 100,000 wafers/month, it’s going to be $20 billion. Even before you get to 450mm, it’s going to be significantly more capital intensive,” he said.

Just looking at the location of the headquarters of semiconductor companies, he said the U.S. was still strong, but there was also strong growth from Korea – mostly in the form of Samsung – but also China and Taiwan. “We see a relatively flat Europe and then a continuing decline in Japan. In fact, we don’t see Japan strengthening unless we see some major changes,” he said.

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That also has an impact in terms of the technology requirements. In terms of minimal dimensions, Handel most of the advanced technology designs are in the U.S., with advanced technology defined as being 28, 20 and now starting 16/14nm. “In developing countries, many of the designs are still at 40nm. 28 is a new technology and the next technology after 28 is going from polysilicon up to high-k metal gate,” he said.

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Handel also sees uncertainly in the use of FinFET devices due to higher wafer cost. “We see quite a few new designs. The problem again is the cost per wafer. For 28nm, we have about $2600 and for 20nm we have about $3200 and for 16/14 we have about $4000. You now have this increasing cost per wafer and can you get the higher gate density and can you also get higher parametric yields?” he asked.

Handel said the gate utilization is an issue because of limitations of the design tools and parasitic effects. “The other factor is parametric yields, which are strictly tied into leakage control for the 20nm and of course for the 16nm FinFETs,” he said. “You can break this. Intel has shown that it can be broken and of course that’s an excellent achievement. But, it’s based on very high design costs, potentially $1 billion per design, so you need $10 billion in revenue. It also takes a number of years,” he said. He noted that, in the smartphone market, designs move very fast. “You can’t make that kind of investments in designs.”

The magic behind the gadget and the need for innovation

Rick Wallace, president and CEO of KLA-Tencor, provided the keynote talk at the SEMI Industry Strategy Symposium (ISS) this year, held Jan 12-15 in Half Moon Bay, CA. He said he believes the semiconductor industry might be facing a “Concorde” moment, referring to the demise of supersonic passenger transport, the last flight of which was on 24 October 2003. “That failed not because of technology but because of economics,” Wallace said. He sees a similar challenge coming down the road for continued scaling. “Moore’s Law is much more likely to die in the boardroom than the laboratory,” said.

Wallace also spoke about “The Road Less Traveled,” seeming to indicate that the more traveled one is that of consolidation, which Wallace said leads to “losses in agility, flexibility and innovation.” He said larger firms are not effective at driving innovation although they are effective at driving continuous improvement. “It’s tough to see how a large scale merger makes a company better,” he said. “Some firms will be too big to fail but my fear is that they will become too big to innovate.”

The solution he said is young people. “We need to attract the young talent if we want real innovation. The longer you’re around the more you see what can’t be done,” he said.

Wallace told a story about explaining to his 10 year old daughter what his company by using the iPad as an example. His daughter thought about it and said she understood: it was the magic behind the gadget.

Part of attracting young people to the semiconductor industry is through education. After Rick’s presentation, Denny McGuirk, president of SEMI, presented an award to Rick and to L.T. Guttadauro, president of the Fab Owners Association, in recognition of their work on SEMI’s High Tech University (HTU). HTU is a career exploration program that encourages student interest in science, technology, engineering and match. Since 2001, the SEMI Foundation has delivered 143 programs to 4800 students and teachers worldwide.

Although some view the semiconductors as a commodity, hopefully efforts such as that of the HTU will explain the magic behind the gadget. “Who doesn’t want to work on magic?” Wallace asked.

50 years ago: January 1964

The origin of Solid State Technology began in 1958, the same year that Jack Kilby of Texas Instruments invented the integrated circuit (the invention of the transistor is credited to Bell Labs; the first transistor was demonstrated on December 23, 1947). The initial name of the magazine was “Semiconductor Products” and that was changed to “Semiconductor Products and Solid State Technology” by 1962.  

In this news series, we’ll look back 50 years and see how much has changed.. or perhaps more often, how much hasn’t.  

In January of 1964, it was clear that microelectronics were here to stay, and were rapidly changing the shape of the electronics industry (Gordon Moore did not propose his now famous Moore’s Law until April of 1965, more than a year later. Intel was not founded until 1968). In the Editorial in the January 1964 issue, Editor Sam Marshall writes that estimates for the market for microelectronics in 1964 “vary between 25 and 50 million dollars.” The market exceeded $300 billion in 2013.002 (444x640)

Sams adds: “There is a parallelism between the manner in which semiconductor devices have gradually displaced vacuum tubes, and the manner in which microelectronics is encroaching into the territory formerly enjoyed by discrete devices such as diodes and transistors. This movement is directly related to the increasing demands for higher frequencies of operation, greater miniaturization and surprisingly enough, reliability.”

Sam also foresaw how the relationship between design and manufacturing was getting more complex and even hints at the trends toward the fabless/foundry model. He said that a new order of procedure must be followed.  “The engineer must either turn over his proprietary design to a firm engaged in microelectronics manufacturing or he might search the open market for functional blocks that will best meet his needs. In either case, an unhealthy situation arises. In the first case, the design engineer has to reveal information which could jeopardize his firm’s market advantage. In the second case, the manufacturer who merely purchases functional blocks and assembles them into a product justifiably feels that he has lost his status as that of a true manufacturer and has become nothing more than an assembler and tester.”

The issue had a feature on electron beam processing of semiconductor devices, which noted how useful the analysis of X-rays generated from e-beams could be for metrology. “The technique is extremely useful in determining which elements are present on the specimen surface as well as detecting local variations in their concentrations after such treatments as localized melting, annealing, diffusion and oxidation.” Today, energy dispersive x-ray spectroscopy or (commonly called EDS, EDX or EDAX) is widely used.

Perhaps the most obvious change in the last 50 years: wafer size. Note these two advertisements, one touting a production breakthrough of 40mm wafers (that’s a little over 1.5 inches), the other depicting a wafering machine. Of course, today the industry is working with 300mm wafers and contemplating going to 450mm. It’s also interesting to note the die size, number of die per wafer and pincount shown on the left, although it’s hard to say if that was typical of the time.

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Other odds and ends from 1964: Kulicke and Soffa reported its sales fro the fiscal year ending Sept 30, 1063, were $3,615,519, an increase of 95%. ITT planned to construct a 135,00 square foot, $3 million plant in West Palm Beach, FL to manufacture integrated circuits and other semiconductor devices. Philco Corp.’s Lansdale Division (which produced Indium Antimonide IR detectors among other types of electronics), planned to triple the divisions facilities for microelectronic engineering and product development, with plans to develop new production facilities capable of producing 10,000 silicon microcircuits per month by Spring of 1964. Total 1964 R&D expenditures in the U.S. were expected to reach the $20 billion mark. In 1963, about $18.3 billion has been spent on R&D compared to $16.6 billion in 1962. Advanced achieved with graphite and carbon as engineering materials were detailed by Speer Carbon Co.  A novel approach to the fabrication of a high speed tunnel diode was described by IBM: a gallium arsenide, planar, epitaxial device. Today, the potential of tunnel transistors is being discussed as a replacement to FETs. Based in part on what? Gallium Arsenide! The more things change…

Coming next month: GaAs IR emitters, tunnel diode amplifers and thermal resistance of transistors.

Is It Time for A Roadmap for Equipment and Materials?

Hopefully everyone is familiar with the International Technology Roadmap for Semiconductors (ITRS). It was launched in 1992, when the Semiconductor Industry Association (SIA) coordinated the first efforts of producing what was originally The National Technology Roadmap for Semiconductors (NTRS). This roadmap of requirements and possible solutions was generated three times in 1992, 1994, and 1997. The NTRS provided a 15-year outlook on the major trends of the semiconductor industry. As such, it was a good reference document for semiconductor manufacturers, suppliers of equipment, materials, and software and provided clear targets for researchers in the outer years.

When the semiconductor industry became increasingly global, the realization that a Roadmap would provide guidance for the whole industry and would benefit from inputs from all regions of the world led to the creation of the International Technology Roadmap for Semiconductors (ITRS).

The invitation to cooperate on the ITRS was extended by the SIA at the World Semiconductor Council in April of 1998 to Europe (represented by the European Electronics Component Manufacturers Association [EECA]), Korea (Korea Semiconductor Industry Association [KSIA]), Japan (formerly the Electronic Industry Association of Japan [EIAJ] and now the Japan Electronics and Information Technology Industries Association [JEITA]), and Taiwan (Taiwan Semiconductor Industry Association [TSIA]).

Much has been written about the ITRS, which is perhaps the best roadmapping effort of all time in any industry. In fact, I stumbled across a dissertation titled “Technological Innovation in the Semiconductor Industry: A Case Study of the International Technology Roadmap for Semiconductors (ITRS)” written by Robert R. Schaller in his pursuit of a degree in philosophy at George Mason University. Robert did a great job analyzing the importance of the roadmap and includes anecdotes such as a short-lived attempt at AMD to create an internal roadmap, and how the ITRS relates to the roadmap to peace in the Middle East.

While the latest updates and revisions of the ITRS usually come out around this time of year, the organizers tell me that it will be in the spring of 2014 for the latest edition (which will be a full revision vs an update, which alternate every year).

A key aspect of the ITRS is that they go out of the way to NOT try to pick “winners and losers” as I’ve heard it called. It is clearly stated that: “The ITRS is devised and intended for technology assessment only and is without regard to any commercial considerations pertaining to individual products or equipment”.

That’s all well and good I suppose, and there is plenty of information that a savvy supplier can pull from the Roadmap about what technology is needed and what the market demand might look like. But it’s time to take it to the next step.

It’s time to think about creating a roadmap for equipment and materials companies, and their suppliers (i.e., suppliers of critical components and subsystems and raw materials). I recently had a conversation on exactly this topic with Gopal Rao, SEMATECH’s senior director of business development. Prior to joining SEMATECH, Rao served as director of Manufacturing Research at Intel, where he led a strategic portfolio of advanced manufacturing projects in partnership with universities and national labs. A 24-year veteran of Intel, Rao progressed through a variety of assignments in senior engineering and management roles.

Gopal attended The ConFab 2013 as a representative of Intel, and said he found the private meeting with suppliers quite useful. What he proposes we do in 2014 was at least introduced the concept of a roadmap for equipment and materials suppliers, perhaps in a panel session, and suggest it be a common thread in the private meetings between sponsors (suppliers) and VIPs (delegates from IC manufacturing companies). We had more than 170 such meetings in 2013. At the end of the conference, we’ll come up with a list of 4 or 5 “action items” for the industry to address. I like this concept a lot, and it’s perfect timing since we’re just now defining session topics and recruiting speakers and panelists.

I like this idea a lot and will plan on adding it to the agenda. If we can define what suppliers need to deliver in terms of throughput, uptime, automation, footprint, uniformity (wafer-to-wafer and tool-to-tool), data reporting and communication protocol, in-situ inspection… and what else?

The ConFab 2014, by the way, will be held June 22-25 at The Encore at The Wynn in Las Vegas. Don’t miss it!

Challenges of 10nm and 7nm CMOS at IEDM

The International Electron Devices Meeting (IEDM) was held in Washington, D.C. this week. I attended a short course on Sunday focused on the Challenges of 10nm and 7nm CMOS Technologies, organized by Aaron Thean of imec. The speakers were Frederic Boeuf of ST Microlelectronics, who gave a general overview of drivers and challenges; Zsolt Tokei of imec, who spoke on interconnect challenges; Andy Wei of GLOBALFOUNDRIES who talked about process integration challenges, Paul Franzon of North Carolina State University who gave an overview of 2.5D and 3D stacked ICs, and Mark Neisser of Sematech of spoke on lithography challenges and EUV readiness for 10nm and beyond.

Monday morning brought three plenary speakers in the form of a talk on graphene integrated circuits by Andrea Ferrari from the University of Cambridge, a fascinating “super chip” concept presented by Mitsumasa Koyanagi from Tohoku University, and a most excellent talk by Geoffrey Yeap of Qualcomm Technologies on how smart mobile SoCs are now driving the semiconductor industry. During lunch, IEDM chairs Ken Rim of Qualcomm and Suman Datta of Penn State highlighted 15 of the top papers, many of them showing recording breaking results

I also attended an interesting evening panel session hosted by Leti that gave an overview of their electronics research efforts, a panel session hosted by Applied Materials on 3D NAND, and a luncheon talk by Eric Enderton of NVDIA research.

I’ll be summarizing what I learned in the coming weeks and months, but it was very clear to me that process technology (including litho) and process integration remains the most critical factor in determining success moving forward. In FinFET production, for example, a gate-last/high-k last process is detrimental to total parasitic capacitance compared to a gate last/high-k first approach. Hopes remain high for EUV – the urgent need for it was clearer than ever – but Andy Wei said it was not going to happen for 10nm (let’s leave it at that he said) and Neisser said the delay has already cause most companies to look earnestly for alternatives. He said DSA was showing great promise, particularly for vias, but it was difficult to assess progress since those involved were not yet publicly discussing results.

“A dream for the device engineer could be a nightmare for a process integration engineer,” said Boeuf in the opening talk. That seemed to be echoed throughout the conference, where the potential of new devices such as tunnel FETs or materials such as graphene were always tempered with a dose of reality that materials had to be deposited, patterned, annealed to create devices, and those devices had to be connected. There was also the perhaps inevitable discussion about how long the industry could continue scaling. We are “running out of numbers,” Wei said in a response to a question regarding what was after 7nm. “We’re running out of atoms,” he added. What was most startling was a comment from Serge Tedesco of Leti who said that ML2 and DSA, as cost effectives and complementary solutions, could extend 193i lithography to the end of the roadmap! The end of the roadmap? I have not given much thought to an end to the roadmap, although the ITRS looks out to 2026. For now, I’ll assume that means the end of conventional scaling, but I have to say I never want to see it end.  

Countdown to The ConFab 2014

We had our second conference call yesterday with advisory board of The ConFab (a special thanks to Lori Nye of Brewer Science who called in from Japan at 2:00 am her time. Above and Beyond the call of dutry!). The ConFab will be held June 22-25 at The Encore at The Wynn in fabulous Las Vegas, Nevada. It will be the 10th anniversary of the event and I’m working hard to make it the best one ever.

We’ve recently updated the event website, www.theconfab.com. It includes a short video where, using my best radio voice, we scroll through pictures of last year’s event, including a not so flattering picture of Bill Ross of ISMI (sorry Bill!).

As you know, I travel around a lot, attending various semiconductor meetings and conferences. In fact, I’m off to IEDM tomorrow! Short courses begin at 9:00 am on Sunday and I can’t wait. It’s like drinking the Kool-Aid from a fire hose! But I digress.

The ConFab is vastly different from any other event I’ve attended for several reasons. For one, it’s focused entirely on the economics of semiconductor manufacturing. All of the keynotes and presentations are tuned to that direction. Yes, we get into technology challenges in design, manufacturing, packaging and test, but with a huge helping of why and at what cost? We may kind of sip the Kool-Aid but then talk about how it tastes (okay, any analogy breaks down at some point, but you know what I mean).

Another reason The ConFab is different: We combine thought-provoking conference sessions with private meetings arranged between our sponsors and our VIP attendees or “delegates” as we like to call them. These aren’t “speed dating” kinds of meeting, but 45 minute meetings where both parties come prepared to talk business. I’ve found this is one of the least understood aspect of The ConFab. People often ask me: “Why would leading semiconductor manufacturers feel the need to travel and sit down with their suppliers when they could just pick up the phone and call them whenever they want.” The answer to that is simple. One, it’s true they can do that, but those kinds of conversations are usually focused on some kind of problem. The tool isn’t working; get it fixed. We need this or that. I’m not privy to the private conversations in these meetings at The ConFab, but people have told me they’ve accomplished more in one day than would have in a year otherwise. They’ve also told me it was the first time they met with a customer and didn’t get yelled at.. but that’s a different story. I think it’s also true that most of the technology in a fab come from the tool and equipment suppliers (and software suppliers – let’s not forget EDA!). At The ConFab, they can at least touch base with all of their main suppliers and have useful meetings. People come to this absolutely fabulous hotel, which is easy to get to, relax and listen to luminaries discuss industry trends and challenges, and then sit down with folks that can make business happen. We combine all this seriousness with a variety of networking events, including breakfasts, lunches and evening receptions, as well as refreshment breaks.

At the 2013 ConFab, more than 175 private meetings took place during which sponsors and their customers, both prospective and existing, engaged in strategic discussions and created crucial alliances for the future. These pre-scheduled boardroom meetings offer an efficient and highly effective approach to conducting face-to-face business in a global industry

I was talking to Bill Tobey yesterday after our conference call. Bill, who is a true industry veteran, has been involved with The ConFab from the very beginning and has seen many things come and go. He reminded me that in the mid 2014 we will know a lot more than we do today. EUV alone – whether it works or not — is going to be a major factor in determining the “economic balance” as Bill put it. He said we should keep that in mind as we develop our session topics and invite our speakers. Sage advice if I’ve ever heard it. Bill was one of the co-founders of Micronix, which was focused on providing a single point X-ray solution. That didn’t take off because of problems with the X-rays masks. Guess what – the same problem still exists with EUV masks. But I digress yet again.

With Bill’s help – and the rest of our fantastic board members — we’re putting together the agenda for 2014. I’m more than confident that it will be as exciting as past years, when we had such speakers as: Y.W. Lee of Samsung, Subu Iyer of IBM, John Chen of Nvidia, Bob Bruck and Jackie Sturm of Intel, BJ Woo of TSMC, Ali Sebt of Renesas and many others (check out our most excellent lineup from this year).

We will be covering the economic outlook for 2014 and beyond, major technology challenges facing the industry – such as the move to 450mm wafers – and of course the big issues such as the escalating costs of R&D.

More on this later, but we are also planning a second ConFab event, The ConFab II, in November. This will focus on critical subsystems and components: all the things that go into today’s extremely complex processing and assembly tools, including robotics, vacuum pumps, pressure gauges, power supplies, exhaust treatment, wafer aligners, etc.

This is all a long-winded way of saying I hope you join us next June at The ConFab for our 10th anniversary, and The ConFab II in November. Check out our website for more: www.theconfab.com.

Pete

P.S. If you’re interested in a sponsorship, contact Sabrina Straub at sstraub@extensionmedia.com.

IEDM’s special focus session highlights diverse challenge

As part of the technical program at the annual IEEE International Electron Devices Meeting (IEDM), scheduled for December 9 – 11, 2013 at the Washington Hilton Hotel, a special focus session has been planned to highlight advanced processing and platforms for semiconductor manufacturing technology, including ‘more-than-Moore’ applications.

The technical session, scheduled for Tuesday, December 10 from 9am – 12pm, will feature presentations on many of today’s hot topics: memory, LEDs, silicon photonics, interposers, SOI finFETS and 450mm.

Memory industry transition from planar to 3D scaling and the introduction of emerging memory devices into manufacturing over the next decade will drive several unique challenges. The inflection point faced by the semiconductor memory industry is a new paradigm where advancements in materials science, equipment technology, and control methodologies are critical for scaling cadence. This will be the focus of “Challenges in 3D Memory Manufacturing and Process Integration,” an invited paper given by N. Chandrasekaran, Micron Technology

The output power at high temperature required for LEDs applied in solid-state lighting can be obtained by reducing threading dislocation density (TDD) on silicon substrates using a new technology, SiN multiple-modulation interlayers, to realize highly efficient blue LEDs grown on high-crystalline-quality GaN templates on 8-inch silicon wafers. This will be presented in “LED Manufacturing Issues Concerning Gallium Nitride-on-Silicon (GaN-on-Si) Technology and Wafer Scale up Challenges,” an invited paper given by S. Nunoue, et.al., Toshiba Corporation

Recently, silicon photonics has generated a renewed interest in integrated optical communications.  A paper titled “A Multi-Wavelength 3D-Compatible Silicon Photonics Platform on 300mm SOI Wafers for 25Gb/s Applications,” presented by F. Boeuf, et. al., STMicroelectronics will describe the main process features and device results for a 300mm silicon photonics platform designed for 25Gb/s and above applications, at the three typical communication wavelengths that are compatible with 3D integration.

A paper from TSMC will present the details of the first fabrication of a 300mm, 50μm ultra-thin glass interposer – a promising technology for future high frequency mobile RF applications.  The merits of on-glass inductors and transmission lines are compared to their on-silicon counterparts in Q-factor, power dissipation, and power/signal integrity. “300mm Size Ultra-Thin Glass Interposer Technology and High-Q Embedded Helical Inductor for Mobile Applications,” will be presented by W.-C. Lai, et. al., TSMC.

The first rigorous experimental study of effective current (Ieff) variability in high-volume manufacturable 14nm SOI FINFETs, will be presented by A. Paul of GLOBALFOUNDRIES. The study identifies, threshold voltage (Vtlin), external resistance (Rext), and channel transconductance (gm) as three independent sources of variation. The variability in gm, Vtlin (AVT=1.4(n)/0.7(p) mV-μm), and Ieff exhibit a linear Pelgrom fit (indicating local variations), along with non-zero intercept (which suggests global variations at the wafer level). Both n- and p-FINFETs show the above-mentioned trends. The paper is titled “Comprehensive Study of Effective Current Variability and MOSFET Parameter Correlations in 14nm Multi-Fin SOI FINFETs.”

The 450mm transition represents an opportunity to reduce die cost and stimulate another wave of innovations and greener manufacturing. Key challenges ahead, including tool productivity, uniformity, precision, cost-of-ownership reduction, and green concept design-in tool and manufacturing systems, are presented. “Opportunities and Challenges of the 450mm Transition,” is an invited presentation by J. Lin and P. Lin, TSMC.

Progress in Intrachip Optical Interconnects and Silicon Photonics

In a keynote talk at The ConFab earlier this year, Samsung exec Yoon Woo (Y.W.) Lee. predicted that optical interconnects would soon be required. “Exascale computing will require optical interconnection to communicate between the CPU and memory chip,” he said. This appears to be moving closer to reality with last week’s demonstration by Fujitsu and Intel of the world’s first Optical PCIe Express (OPCIe) based server. 

Intel’s 50Gbps silicon photonics link was demonstrated in 2010, and it has now been put into practice. Just last week, Fujitsu said it has demonstrated the world’s first Intel Optical PCIe Express (OPCIe) based server.  In a blog, Intel’s Victor Krutul said that Fujitsu took two standard Primergy RX200 servers and added an Intel Silicon Photonics module into each along with an Intel designed FPGA.  The FPGA did the necessary signal conditioning to make PCI Express “optical friendly”.  Using Intel Silicon Photonics they were able to send PCI Express protocol optically through an MXC connector to an expansion box.  In this expansion box was several solid state disks (SSD) and Xeon Phi co-processors.

It’s commonly known that silicon is not a good material for generating or detecting light (although silicon dioxide is quite good at channeling light). Optical interconnects will require III-V lasers to convert electrical signals into pulses of light and, on the receiving end, photodetectors, typically germanium-based, to convert that light back into electrical signals. Intel has demonstrated that it’s feasible to directly integrate photonics with silicon CMOS in an impressive prototype, but most solutions will require some type of some type of advanced packaging, such as flip-chipped lasers.

During a discussion with Ludo Deferm, executive vice president at imec on interconnects – imec had recently released details about the benefits of manganese as a diffusion barrier and some work on low-temperature low-k etch – I asked him about optical interconnects.

For intrachip applications – such as between microprocessor and memory — Deferm said that will depend on the data rates required. “If you have 1000, 5000 parts to be connected over a distance of a couple of millimeters and you want to transfer a Gb of data, just copper lines can have some limitations,” he said.  “If you have the space — and it takes space — you can do it. But you will do that where you need the high transmission rates. There is no need to change the intrachip interconnects with photonics. But the interchip, between the different chips, we are working on that because we are even now providing photonics technology to startup companies and other companies who want to design in it.“

Part of the challenge is that various optical components are required – waveguides, detectors, modulators and polarizers, for example – and those are not available at standard foundries. Imec has a design kit and a library and IME in Singapore has capabilities as well.  

Deferm said these components are not so easily integrated. “Most of the problems are related to losses. Optical kinds of interconnects have the advantage – they’re good at data speed – but you have to be careful because you can create losses because you need wide ideal structures. Not because they have to be so small in dimension, but they have to be controlled very well over the edges: it is light and light scatters. You also have losses because of coupling,” he said. On a silicon substrate, a high frequency signal in Gb/seconds also creates coupling towards the substrate and that creates losses as well.

SST’s Editorial Calendar for 2014 is Out

The new Solid State Technology Editorial calendar for 2014 – the whole media planner actually – is out and live on our site: http://electroiq.com/advertise-docs/2014mediakit.pdf

The editorial mission remains that same: we’re dedicated to covering mainstream semiconductor manufacturing technology, with a strong focus on transistors, interconnects and packaging. We also cover other types of advanced electronics, including MEMs, LEDs, displays, bioelectronics, photonics and power electronics. In 2014, we’ll be looking at CMOS imagers, thin film batteries, OLEDs, smart sensors, and plastic electronics, among others.

We also delve into the process technologies – lithography, etch, deposition, implant, planarization – and materials. We will also be addressing over-arching topics such as metrology, contamination control, defect detection, thermal management, automation and supply chain issues. And, of course, the 450mm transition.

We’ll be covering these in the magazine (8X in 2014), on the website (www.solid-state.com and www.semimd.com), and through regular webcasts, newsletters, video reports and at our live event, The ConFab in June (www.theconfab.com).

If you’re interested in contributing material on these or other topics, just shoot me a line at psinger@extensionmedia.com, or give me a call at 978-470-1806 I look forward to hearing from you!

SST