Pete's Posts Blog


Is It Time for A Roadmap for Equipment and Materials?

Hopefully everyone is familiar with the International Technology Roadmap for Semiconductors (ITRS). It was launched in 1992, when the Semiconductor Industry Association (SIA) coordinated the first efforts of producing what was originally The National Technology Roadmap for Semiconductors (NTRS). This roadmap of requirements and possible solutions was generated three times in 1992, 1994, and 1997. The NTRS provided a 15-year outlook on the major trends of the semiconductor industry. As such, it was a good reference document for semiconductor manufacturers, suppliers of equipment, materials, and software and provided clear targets for researchers in the outer years.

When the semiconductor industry became increasingly global, the realization that a Roadmap would provide guidance for the whole industry and would benefit from inputs from all regions of the world led to the creation of the International Technology Roadmap for Semiconductors (ITRS).

The invitation to cooperate on the ITRS was extended by the SIA at the World Semiconductor Council in April of 1998 to Europe (represented by the European Electronics Component Manufacturers Association [EECA]), Korea (Korea Semiconductor Industry Association [KSIA]), Japan (formerly the Electronic Industry Association of Japan [EIAJ] and now the Japan Electronics and Information Technology Industries Association [JEITA]), and Taiwan (Taiwan Semiconductor Industry Association [TSIA]).

Much has been written about the ITRS, which is perhaps the best roadmapping effort of all time in any industry. In fact, I stumbled across a dissertation titled “Technological Innovation in the Semiconductor Industry: A Case Study of the International Technology Roadmap for Semiconductors (ITRS)” written by Robert R. Schaller in his pursuit of a degree in philosophy at George Mason University. Robert did a great job analyzing the importance of the roadmap and includes anecdotes such as a short-lived attempt at AMD to create an internal roadmap, and how the ITRS relates to the roadmap to peace in the Middle East.

While the latest updates and revisions of the ITRS usually come out around this time of year, the organizers tell me that it will be in the spring of 2014 for the latest edition (which will be a full revision vs an update, which alternate every year).

A key aspect of the ITRS is that they go out of the way to NOT try to pick “winners and losers” as I’ve heard it called. It is clearly stated that: “The ITRS is devised and intended for technology assessment only and is without regard to any commercial considerations pertaining to individual products or equipment”.

That’s all well and good I suppose, and there is plenty of information that a savvy supplier can pull from the Roadmap about what technology is needed and what the market demand might look like. But it’s time to take it to the next step.

It’s time to think about creating a roadmap for equipment and materials companies, and their suppliers (i.e., suppliers of critical components and subsystems and raw materials). I recently had a conversation on exactly this topic with Gopal Rao, SEMATECH’s senior director of business development. Prior to joining SEMATECH, Rao served as director of Manufacturing Research at Intel, where he led a strategic portfolio of advanced manufacturing projects in partnership with universities and national labs. A 24-year veteran of Intel, Rao progressed through a variety of assignments in senior engineering and management roles.

Gopal attended The ConFab 2013 as a representative of Intel, and said he found the private meeting with suppliers quite useful. What he proposes we do in 2014 was at least introduced the concept of a roadmap for equipment and materials suppliers, perhaps in a panel session, and suggest it be a common thread in the private meetings between sponsors (suppliers) and VIPs (delegates from IC manufacturing companies). We had more than 170 such meetings in 2013. At the end of the conference, we’ll come up with a list of 4 or 5 “action items” for the industry to address. I like this concept a lot, and it’s perfect timing since we’re just now defining session topics and recruiting speakers and panelists.

I like this idea a lot and will plan on adding it to the agenda. If we can define what suppliers need to deliver in terms of throughput, uptime, automation, footprint, uniformity (wafer-to-wafer and tool-to-tool), data reporting and communication protocol, in-situ inspection… and what else?

The ConFab 2014, by the way, will be held June 22-25 at The Encore at The Wynn in Las Vegas. Don’t miss it!

Challenges of 10nm and 7nm CMOS at IEDM

The International Electron Devices Meeting (IEDM) was held in Washington, D.C. this week. I attended a short course on Sunday focused on the Challenges of 10nm and 7nm CMOS Technologies, organized by Aaron Thean of imec. The speakers were Frederic Boeuf of ST Microlelectronics, who gave a general overview of drivers and challenges; Zsolt Tokei of imec, who spoke on interconnect challenges; Andy Wei of GLOBALFOUNDRIES who talked about process integration challenges, Paul Franzon of North Carolina State University who gave an overview of 2.5D and 3D stacked ICs, and Mark Neisser of Sematech of spoke on lithography challenges and EUV readiness for 10nm and beyond.

Monday morning brought three plenary speakers in the form of a talk on graphene integrated circuits by Andrea Ferrari from the University of Cambridge, a fascinating “super chip” concept presented by Mitsumasa Koyanagi from Tohoku University, and a most excellent talk by Geoffrey Yeap of Qualcomm Technologies on how smart mobile SoCs are now driving the semiconductor industry. During lunch, IEDM chairs Ken Rim of Qualcomm and Suman Datta of Penn State highlighted 15 of the top papers, many of them showing recording breaking results

I also attended an interesting evening panel session hosted by Leti that gave an overview of their electronics research efforts, a panel session hosted by Applied Materials on 3D NAND, and a luncheon talk by Eric Enderton of NVDIA research.

I’ll be summarizing what I learned in the coming weeks and months, but it was very clear to me that process technology (including litho) and process integration remains the most critical factor in determining success moving forward. In FinFET production, for example, a gate-last/high-k last process is detrimental to total parasitic capacitance compared to a gate last/high-k first approach. Hopes remain high for EUV – the urgent need for it was clearer than ever – but Andy Wei said it was not going to happen for 10nm (let’s leave it at that he said) and Neisser said the delay has already cause most companies to look earnestly for alternatives. He said DSA was showing great promise, particularly for vias, but it was difficult to assess progress since those involved were not yet publicly discussing results.

“A dream for the device engineer could be a nightmare for a process integration engineer,” said Boeuf in the opening talk. That seemed to be echoed throughout the conference, where the potential of new devices such as tunnel FETs or materials such as graphene were always tempered with a dose of reality that materials had to be deposited, patterned, annealed to create devices, and those devices had to be connected. There was also the perhaps inevitable discussion about how long the industry could continue scaling. We are “running out of numbers,” Wei said in a response to a question regarding what was after 7nm. “We’re running out of atoms,” he added. What was most startling was a comment from Serge Tedesco of Leti who said that ML2 and DSA, as cost effectives and complementary solutions, could extend 193i lithography to the end of the roadmap! The end of the roadmap? I have not given much thought to an end to the roadmap, although the ITRS looks out to 2026. For now, I’ll assume that means the end of conventional scaling, but I have to say I never want to see it end.  

Countdown to The ConFab 2014

We had our second conference call yesterday with advisory board of The ConFab (a special thanks to Lori Nye of Brewer Science who called in from Japan at 2:00 am her time. Above and Beyond the call of dutry!). The ConFab will be held June 22-25 at The Encore at The Wynn in fabulous Las Vegas, Nevada. It will be the 10th anniversary of the event and I’m working hard to make it the best one ever.

We’ve recently updated the event website, www.theconfab.com. It includes a short video where, using my best radio voice, we scroll through pictures of last year’s event, including a not so flattering picture of Bill Ross of ISMI (sorry Bill!).

As you know, I travel around a lot, attending various semiconductor meetings and conferences. In fact, I’m off to IEDM tomorrow! Short courses begin at 9:00 am on Sunday and I can’t wait. It’s like drinking the Kool-Aid from a fire hose! But I digress.

The ConFab is vastly different from any other event I’ve attended for several reasons. For one, it’s focused entirely on the economics of semiconductor manufacturing. All of the keynotes and presentations are tuned to that direction. Yes, we get into technology challenges in design, manufacturing, packaging and test, but with a huge helping of why and at what cost? We may kind of sip the Kool-Aid but then talk about how it tastes (okay, any analogy breaks down at some point, but you know what I mean).

Another reason The ConFab is different: We combine thought-provoking conference sessions with private meetings arranged between our sponsors and our VIP attendees or “delegates” as we like to call them. These aren’t “speed dating” kinds of meeting, but 45 minute meetings where both parties come prepared to talk business. I’ve found this is one of the least understood aspect of The ConFab. People often ask me: “Why would leading semiconductor manufacturers feel the need to travel and sit down with their suppliers when they could just pick up the phone and call them whenever they want.” The answer to that is simple. One, it’s true they can do that, but those kinds of conversations are usually focused on some kind of problem. The tool isn’t working; get it fixed. We need this or that. I’m not privy to the private conversations in these meetings at The ConFab, but people have told me they’ve accomplished more in one day than would have in a year otherwise. They’ve also told me it was the first time they met with a customer and didn’t get yelled at.. but that’s a different story. I think it’s also true that most of the technology in a fab come from the tool and equipment suppliers (and software suppliers – let’s not forget EDA!). At The ConFab, they can at least touch base with all of their main suppliers and have useful meetings. People come to this absolutely fabulous hotel, which is easy to get to, relax and listen to luminaries discuss industry trends and challenges, and then sit down with folks that can make business happen. We combine all this seriousness with a variety of networking events, including breakfasts, lunches and evening receptions, as well as refreshment breaks.

At the 2013 ConFab, more than 175 private meetings took place during which sponsors and their customers, both prospective and existing, engaged in strategic discussions and created crucial alliances for the future. These pre-scheduled boardroom meetings offer an efficient and highly effective approach to conducting face-to-face business in a global industry

I was talking to Bill Tobey yesterday after our conference call. Bill, who is a true industry veteran, has been involved with The ConFab from the very beginning and has seen many things come and go. He reminded me that in the mid 2014 we will know a lot more than we do today. EUV alone – whether it works or not — is going to be a major factor in determining the “economic balance” as Bill put it. He said we should keep that in mind as we develop our session topics and invite our speakers. Sage advice if I’ve ever heard it. Bill was one of the co-founders of Micronix, which was focused on providing a single point X-ray solution. That didn’t take off because of problems with the X-rays masks. Guess what – the same problem still exists with EUV masks. But I digress yet again.

With Bill’s help – and the rest of our fantastic board members — we’re putting together the agenda for 2014. I’m more than confident that it will be as exciting as past years, when we had such speakers as: Y.W. Lee of Samsung, Subu Iyer of IBM, John Chen of Nvidia, Bob Bruck and Jackie Sturm of Intel, BJ Woo of TSMC, Ali Sebt of Renesas and many others (check out our most excellent lineup from this year).

We will be covering the economic outlook for 2014 and beyond, major technology challenges facing the industry – such as the move to 450mm wafers – and of course the big issues such as the escalating costs of R&D.

More on this later, but we are also planning a second ConFab event, The ConFab II, in November. This will focus on critical subsystems and components: all the things that go into today’s extremely complex processing and assembly tools, including robotics, vacuum pumps, pressure gauges, power supplies, exhaust treatment, wafer aligners, etc.

This is all a long-winded way of saying I hope you join us next June at The ConFab for our 10th anniversary, and The ConFab II in November. Check out our website for more: www.theconfab.com.

Pete

P.S. If you’re interested in a sponsorship, contact Sabrina Straub at sstraub@extensionmedia.com.

IEDM’s special focus session highlights diverse challenge

As part of the technical program at the annual IEEE International Electron Devices Meeting (IEDM), scheduled for December 9 – 11, 2013 at the Washington Hilton Hotel, a special focus session has been planned to highlight advanced processing and platforms for semiconductor manufacturing technology, including ‘more-than-Moore’ applications.

The technical session, scheduled for Tuesday, December 10 from 9am – 12pm, will feature presentations on many of today’s hot topics: memory, LEDs, silicon photonics, interposers, SOI finFETS and 450mm.

Memory industry transition from planar to 3D scaling and the introduction of emerging memory devices into manufacturing over the next decade will drive several unique challenges. The inflection point faced by the semiconductor memory industry is a new paradigm where advancements in materials science, equipment technology, and control methodologies are critical for scaling cadence. This will be the focus of “Challenges in 3D Memory Manufacturing and Process Integration,” an invited paper given by N. Chandrasekaran, Micron Technology

The output power at high temperature required for LEDs applied in solid-state lighting can be obtained by reducing threading dislocation density (TDD) on silicon substrates using a new technology, SiN multiple-modulation interlayers, to realize highly efficient blue LEDs grown on high-crystalline-quality GaN templates on 8-inch silicon wafers. This will be presented in “LED Manufacturing Issues Concerning Gallium Nitride-on-Silicon (GaN-on-Si) Technology and Wafer Scale up Challenges,” an invited paper given by S. Nunoue, et.al., Toshiba Corporation

Recently, silicon photonics has generated a renewed interest in integrated optical communications.  A paper titled “A Multi-Wavelength 3D-Compatible Silicon Photonics Platform on 300mm SOI Wafers for 25Gb/s Applications,” presented by F. Boeuf, et. al., STMicroelectronics will describe the main process features and device results for a 300mm silicon photonics platform designed for 25Gb/s and above applications, at the three typical communication wavelengths that are compatible with 3D integration.

A paper from TSMC will present the details of the first fabrication of a 300mm, 50μm ultra-thin glass interposer – a promising technology for future high frequency mobile RF applications.  The merits of on-glass inductors and transmission lines are compared to their on-silicon counterparts in Q-factor, power dissipation, and power/signal integrity. “300mm Size Ultra-Thin Glass Interposer Technology and High-Q Embedded Helical Inductor for Mobile Applications,” will be presented by W.-C. Lai, et. al., TSMC.

The first rigorous experimental study of effective current (Ieff) variability in high-volume manufacturable 14nm SOI FINFETs, will be presented by A. Paul of GLOBALFOUNDRIES. The study identifies, threshold voltage (Vtlin), external resistance (Rext), and channel transconductance (gm) as three independent sources of variation. The variability in gm, Vtlin (AVT=1.4(n)/0.7(p) mV-μm), and Ieff exhibit a linear Pelgrom fit (indicating local variations), along with non-zero intercept (which suggests global variations at the wafer level). Both n- and p-FINFETs show the above-mentioned trends. The paper is titled “Comprehensive Study of Effective Current Variability and MOSFET Parameter Correlations in 14nm Multi-Fin SOI FINFETs.”

The 450mm transition represents an opportunity to reduce die cost and stimulate another wave of innovations and greener manufacturing. Key challenges ahead, including tool productivity, uniformity, precision, cost-of-ownership reduction, and green concept design-in tool and manufacturing systems, are presented. “Opportunities and Challenges of the 450mm Transition,” is an invited presentation by J. Lin and P. Lin, TSMC.

Progress in Intrachip Optical Interconnects and Silicon Photonics

In a keynote talk at The ConFab earlier this year, Samsung exec Yoon Woo (Y.W.) Lee. predicted that optical interconnects would soon be required. “Exascale computing will require optical interconnection to communicate between the CPU and memory chip,” he said. This appears to be moving closer to reality with last week’s demonstration by Fujitsu and Intel of the world’s first Optical PCIe Express (OPCIe) based server. 

Intel’s 50Gbps silicon photonics link was demonstrated in 2010, and it has now been put into practice. Just last week, Fujitsu said it has demonstrated the world’s first Intel Optical PCIe Express (OPCIe) based server.  In a blog, Intel’s Victor Krutul said that Fujitsu took two standard Primergy RX200 servers and added an Intel Silicon Photonics module into each along with an Intel designed FPGA.  The FPGA did the necessary signal conditioning to make PCI Express “optical friendly”.  Using Intel Silicon Photonics they were able to send PCI Express protocol optically through an MXC connector to an expansion box.  In this expansion box was several solid state disks (SSD) and Xeon Phi co-processors.

It’s commonly known that silicon is not a good material for generating or detecting light (although silicon dioxide is quite good at channeling light). Optical interconnects will require III-V lasers to convert electrical signals into pulses of light and, on the receiving end, photodetectors, typically germanium-based, to convert that light back into electrical signals. Intel has demonstrated that it’s feasible to directly integrate photonics with silicon CMOS in an impressive prototype, but most solutions will require some type of some type of advanced packaging, such as flip-chipped lasers.

During a discussion with Ludo Deferm, executive vice president at imec on interconnects – imec had recently released details about the benefits of manganese as a diffusion barrier and some work on low-temperature low-k etch – I asked him about optical interconnects.

For intrachip applications – such as between microprocessor and memory — Deferm said that will depend on the data rates required. “If you have 1000, 5000 parts to be connected over a distance of a couple of millimeters and you want to transfer a Gb of data, just copper lines can have some limitations,” he said.  “If you have the space — and it takes space — you can do it. But you will do that where you need the high transmission rates. There is no need to change the intrachip interconnects with photonics. But the interchip, between the different chips, we are working on that because we are even now providing photonics technology to startup companies and other companies who want to design in it.“

Part of the challenge is that various optical components are required – waveguides, detectors, modulators and polarizers, for example – and those are not available at standard foundries. Imec has a design kit and a library and IME in Singapore has capabilities as well.  

Deferm said these components are not so easily integrated. “Most of the problems are related to losses. Optical kinds of interconnects have the advantage – they’re good at data speed – but you have to be careful because you can create losses because you need wide ideal structures. Not because they have to be so small in dimension, but they have to be controlled very well over the edges: it is light and light scatters. You also have losses because of coupling,” he said. On a silicon substrate, a high frequency signal in Gb/seconds also creates coupling towards the substrate and that creates losses as well.

SST’s Editorial Calendar for 2014 is Out

The new Solid State Technology Editorial calendar for 2014 – the whole media planner actually – is out and live on our site: http://electroiq.com/advertise-docs/2014mediakit.pdf

The editorial mission remains that same: we’re dedicated to covering mainstream semiconductor manufacturing technology, with a strong focus on transistors, interconnects and packaging. We also cover other types of advanced electronics, including MEMs, LEDs, displays, bioelectronics, photonics and power electronics. In 2014, we’ll be looking at CMOS imagers, thin film batteries, OLEDs, smart sensors, and plastic electronics, among others.

We also delve into the process technologies – lithography, etch, deposition, implant, planarization – and materials. We will also be addressing over-arching topics such as metrology, contamination control, defect detection, thermal management, automation and supply chain issues. And, of course, the 450mm transition.

We’ll be covering these in the magazine (8X in 2014), on the website (www.solid-state.com and www.semimd.com), and through regular webcasts, newsletters, video reports and at our live event, The ConFab in June (www.theconfab.com).

If you’re interested in contributing material on these or other topics, just shoot me a line at psinger@extensionmedia.com, or give me a call at 978-470-1806 I look forward to hearing from you!

SST

Should lifetime of EUV optics be a concern?

It’s well known that EUV adoption is running later than hoped, mostly due to inadequate source power (although ASML and Cymer say they are on track to provide workable solutions and imec says it’s on track for the 10nm node). After that, the main challenge could be those associated with EUV mask blanks, which are essentially sophisticated mirrors. The dual challenge there is that they are not only difficult to produce without defects, but they are difficult to inspect. Presently, the only way to really test them is to fabricate them and see what kind of pattern results after they’re used.

But another challenge recently came to my attention: the optics in the EUV system, which are also sophisticated mirrors made of multi-layer structure, get contaminated during operation. This degrades their quality over time, and eventually the system must be disassembled and the optics recoated or replaced.

EUV optics F1

I recently talked to Dr. Harro Hagedorn, head of R&D at Leybold Optics in Alzenau, Germany. Located about 20 minutes outside of Frankfurt, the company supplies evaporation and magnetron sputtering systems used to fabricate the multi-layer coatings used for EUV collector optics and or many other applications such as synchrotron labs and X-ray devices. And they work with ASML and Zeiss, and the Fraunhofer Institute.

Speaking on EUV, Dr. Hagedron, said the output of the light source is still not high enough, and also the lifetime of the optics was a concern. “This light source is normally an awful thing for the optics because you have a metal droplet that is heated up by a laser and then it creates a plasma. These metal droplets are also contaminating the optics,” he said. To correct, this “they have to disassemble the system and recoat these optics. They are very expensive. Also, the life throughput that comes from this light source and through the optics goes down. They have to also manage this,” he said.

Part of the complexity and expense of the optics is that they rely on interference coatings that require stacks of layers. “The challenge is that these layer stacks are incredibly thin, 3-4nm, with coating uniformities in the range of 0.1%,” Hagedron said. “It’s not any more than a diameter of an atom.” The goal for these optics is a reflectivity of nearly 70%.

Investigating a bit further, I found that there has been a significant amount of research into the lifetime of EUV optics. In fact, earlier this year in April, a session at SPIE was dedicated to damage to VUV, EUV, and X-ray Optics. One of the papers by Laser-Lab in Germany, KLA-Tencor and Fraunhofer, described work that characterized EUV damage thresholds and imaging performance of Mo/Si multilayer mirrors. Here’s a summary:

Currently, more and more powerful EUV sources for next generation semiconductor microlithography are being developed, for which novel optical elements like multilayer or grazing-incidence mirrors are required. Consisting of very thin alternating layers, especially molybdenum and silicon for the wavelength of 13.5 nm, multilayer mirrors are typically employed for near-normal reflection angles. These mirrors are presently being optimized with respect to thermal resistivity and reflectivity. However, only very few ablation and damage threshold studies at a wavelength of 13.5 nm are available up to now for these optical elements.

We studied 1-on-1 and 10-on-1 damage thresholds of Mo/Si multilayers with EUV radiation of 13.5 nm wavelength, using a table-top laser produced plasma source based on solid gold as target material. The experiments were performed on different types of Mo/Si mirror, showing no significant difference in single pulse damage thresholds. However, the damage threshold for ten pulses is ≈60 % lower than the single pulse threshold, implying a defect dominated damage process.

Using Nomarski (DIC) and atomic force microscopy (AFM) we analysed the damage morphologies, indicating a primarily thermally induced damage mechanism for higher fluences. Additionally, we characterised transmission and reflection properties of novel Mo/Si multilayer beam splitters performing wavefront measurements with a Hartmann sensor at 13.5 nm wavelength. Such wavefront measurements allow also actinic investigations of thermal lens effects on EUV optics.

My main takeaway from all of this is that even if the technical challenges of EUV make it ready for production for the 10nm device generation, there still must be lots of questions about the ultimate cost of ownership and how that will compare to double and triple patterning approaches with 193nm immersion.

What’s down the road for bulk FinFETs

For the 10nm node and beyond, transistor research efforts are focused on high mobility designs with Ge and III-V channel, reducing VDD supply voltage as well as the subthreshold slope in transistors and optimizing multi-Vt  designs. Eventually, lateral finFETs built from silicon nanowires may be required. As previously reported in the post “Status update on logic and memory roadmaps,” the 14nm node (which imec calls the “N” node”) is in development today, heading toward early production in 2013/2014. That will be followed by the N10 node in production at the end of 2015 and beginning of 2016. Then N7 and N5 will follow in 2017 and 2019.

A detailed look at the likely roadmap for logic devices built on bulk silicon wafers using finFET technology was provided at the recent International Technology Forum for the press at imec in Leuven, Belgium in October. An Steegen, senior vice president process technology provided the overview, highlighting research underway for the 10nm, 7nm and 5nm nodes.

Steegen F1

Steegen said power was a concern in both high performance logic devices, which are thermally limited, and in mobile devices, which are battery limited. “What we’ve been trying to do at all our technology nodes is to try to step down that power curve, mainly be trying to lower the Vdd,” she said. The trick, she said, was to lower the power, but still retain performance, and the best way to do that is to make the subthreshold slope of the device steeper. She said the target was 16mv/decade, which is the limit of conventional transistors.

Steegen F2

There’s a tradeoff, however, in that reduced Vdd often means increased variability, depending on the threshold voltage of the devices. “On the High Vt device, when you go low Vdd, you’re so close to the threshold voltage of your device that the spread becomes enormous. What you could do is switch to a low Vt device. That’s better for variability but your leakage is going to increase,” she said.

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At imec, their research is focused on bulk silicon finFETs (others are exploring fully depleted SOI) with a replacement gate and high k. Work is still underway on ways to best integrate a replacement metal gate, and on multi-Vt devices. “That’s still work we are executing,” she said. She noted that imec has worked on high-k metal (HKMG) gates for more than 15 years, and is now looking at how to implement a replacement metal gate on a finFET device and enginner the Vts. “Uou also need to make sure your reliability comes together,” she said.

One way in which they have enabled multi-VT tuning (range up to 600mV) is with controlled Al diffusion in metal gate stack. “You want to make sure you can offer the designers a low Vt device, a standard Vt device and a high Vt device, which means that you need to be able to tweak the materials in your gate to cover that entire range of Vt scaling,” Steegen said.

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She added that, for the 10nm node, they are engineering an entire silicon finFET platform. “That means we work on every single module going in, from scaling to the N10 dimensions, control of the fin height, making sure you get conformal doping in the fin, and source/drain engineering because you still want to get some form of stress from your source/drain.”

Steegen F5

For the 7nm node, Steegen believes the channel materials will need to be replaced with higher mobility materials, germanium for PFETs and InGaAs for NFETS. To integrate these materials, a technique known as Aspect Ratio Trapping (ART) is used. This technique uses high aspect ratio sub-micron trenches to trap threading dislocations, greatly reducing the dislocation density of lattice mismatched materials grown on silicon. “You have engineer your dislocations and defects,” Steegen said.

ART is shown to be very effective for a wide variety of materials including Ge, GaAs and InP. It has been combined with epitaxial lateral overgrowth to create long, 18 micron wide strips of low dislocation density material. ART has been used to integrate many types of Ge and III-V devices on silicon including GaAs MOSFETs, GaAs lasers, GaAs tunnel diodes and a silicon infrared imager chip with monolithically integrated Ge photodiodes.

For PFETs, the technique involved, “recessing the silicon, growing silicon germanium buffer back and then strained germanium on the top. The STI is then going to be recessed and you have a strained germanium fin on the top,” Steegen explained. The same integration scheme is used for NFETs, but “it’s a little more complex to try to get to a strained InGaAs NFET channel because the lattice mismatch with silicon is larger. You have to use more buffers here and go a little bit deeper to grow all these buffers through the trench,” she said. “Aspect ratio trapping makes sure all the defects — and you’re going to have them in that strained/relaxed buffer — are trapped at the sidewalls of the STI so that they don’t reach the top silicon.”

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This added complexity appears to be worth the effort based on modeling, which shows a net gain of 25% more performance at constant power, compared to a bulk silicon finFETs. “There is still a lot of benefit you’re going to get in one node by replacing these channel materials,” Steegen noted.

Steegen F8

Beyond 7nm, imec is looking at higher mobility materials such as graphene, and also looking at new device architectures such as tunnel FETS. “At this point, we are looking at germanium source tunnel FET to overcome the tunneling barrier with a lower bandgap material at the source,” Steegen said. “We truly want to try to break that 60mv/decade subthreshold slope.” She said lots of progress has been made but there was more work to do to understand band-to-band tunneling mechanisms. The team is also looking at “2D” materials such molybdenum disulfide and tungsten diselenide.

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EUV is late but on the way for 10nm; DSA is promising

EUV lithography is late, but it is on the way and will be ready for insertion into the 10nm node, which is slated to go into production in late 2015/early 2016. Meanwhile, results from early work into directed self-assembly (DSA) is quite promising. DSA could be used in conjunction with EUV for the 7nm node, scheduled to go into production in the 2017/2018 timeframe. These were some of the conclusions from the imec International Technology Forum for the press earlier this month, where the latest results from EUV and DSA work were presented. Imec and ASML also announced an advanced patterning center that will be based at imec’s Leuven campus focused on EUV.

Luc Van den hove, president and CEO of imec, described EUV as a cost-effective lithography approach that is “absolutely needed.” He said: “We realize that EUV is late. There are challenges here. But I have to say over the last couple of months, significant and steady progress has been realized.” In terms of imaging performance, imec has been characterizing some of the latest hardware together with ASML and have showed very good resolution performance of 13nm half pitch and 22nm contact holes. “With double patterning, we have even demonstrated 9nm half pitch,” Van den hove said. “Who would have thought a couple of years ago that this would be realizable with lithography?”

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Adequate source power, which directly determines throughput, is one of the challenges. “We are seeing a steady increase quarter by quarter,” Van den hove said. “We see that we get the improvements and I’m very convinced that very soon EUV will be ready to enter manufacturing.”

An Steegen, senior vice president of process technology at imec, provided some more details: “The standalone Cymer source has been demonstrated at 55Watt. The next checkpoint is the 80W by the end of 2013. That is on the assembled system, source and scanner, and [throughput] should be approximately 58 wafers/hour. The goal is by the end of 2014, about 126 wafer/hour,” she said.

EUV F1

Steegen said ASML’s 3300 system has already been verified. “We definitely and clearly can see the resolution benefits as well as overlay capability,” she said (the demonstrations were done in at ASML’s facilities in Veldhoven; imec has a 3000 system installed, but won’t get a 3300 until February 2014).

The ideal entry point for EUV is the 10nm node (or N10 using imec’s terminology). “If you look at the cost calculation, the best entry point for EUV is actually at N10 because you can replace triple patterning layers in immersion with a single patterning layer in EUV,” Steegen said. Since that will come relatively soon with early production occurring toward the end of 2015 and in early 2016, that means that likely the whole development phase will have already been built on immersion and multi-patterning. “Likely you will see on the most difficult levels, a swap, an introduction of EUV at the most critical levels later on in manufacturing for N10,” Steegen said. “That is still what the forecast is today. You would also see a benefit later on inserting EUV in N10.”

When you move to N7 and do multi-patterning, it’s getting even more complicated, since almost every level is going to be triple patterning. “If you replace that with EUV, will still are going to try to have single patterning on most of the levels, but there’s some complexity coming in even with EUV, that you would have to go to multi-patterning for N7 to get to those dimensions,” Steegen added.

However, she acknowledged that more work needed to be done.

She noted that defectivity in mask and the reticles was still a challenge, particularly those defects embedded in the multi-layered films. “Between those mutli-layers in the reticle, you might have embedded defects that you can’t see today with any inspection tool. You actually need an actinic inspection tool that also runs at the wavelength of the EUV tool to really see those embedded defects on the reticle. Today, the only way we find those is by printing the wafer and see the printable defects in your patterns,” she said.  

Van den hove added: “Now that the tool is really progressing tremendously and becoming ready for manufacturing, you also have to make sure that the rest of the infrastructure is ready. In our program, we are now focusing very much also on how to handle defects – defectivity on the mask is one of the big challenges.”

In an earlier interview, Veeco’s Tim Pratt, Senior Director, Marketing, said that indeed the next major roadblock to progress in the ongoing push to develop EUV lithography for volume production is the availability of defect-free mask blanks. He said that the tools in place today are not capable of producing mask blanks with the kind of yield necessary to support a ramp in EUV.

Imec is also evaluating the use of a pellicle on EUV reticles. Pellicles are used to keep particles from falling on the reticle during exposure and transport, but since EUV masks are reflective instead of transparent, it’s no clear how a pellicle would work. “For years, we have been thinking that pellicles would be impossible in EUV, and whether we can use a pellicle or not,” Van den hove said. But he said there were some options that are being evaluated at this moment. Steegen said: “We’re looking into would it make sense to avoid added defects during scanning to introduce a pellicle on these EUV reticles.”

Steegen also said they have also seen good progress with the resists needed for EUV for the 22/20nm contact hole and line space range, including improved line edge roughness (LER) and local critical dimension uniformity (LCDU). “We see quite some improvement in LER post-etch and also in LCDU post-etch where we combined the exposures on the 3300 with etch and basically try to improve our line edge roughness and local CDU,” she said. Imec has integrated litho and etch together in such a way that the resulting dimensions are improved after etch. “What you can see is that you cannot only shrink your holes after etch, but you also improve your line edge roughness and local CDU after etch,” Steegen said. “That’s pretty significant because basically you can shrink the nominal dimension of the hole by about 14% and the local variation of that CD, we can improve about 30% post etch.”

Here’s how imec summed up EUV’s readiness:  

• NXE-3300 resolution benefit and overlay capability demonstrated.

• CH and LS resist materials for NXE-3300 selected, based on CDU, LER/LCDU and defectivity; good progress in resist process down-selection towards 16nm LS (@ 0.33NA)

• 4.2nm of CH CD reduction for 26 nm HP post etch (14%); 1.4nm LCDU reduction for 26nm HP post etch (30%)

• Source power and mask defectivity remain key challenges:

• ASML/Cymer demonstrated 55W power on standalone Cymer source, outlook 80W (58wph) by YE13,

250W (126wph) by YE14.

• Introduction of actinic inspection tools by 2015 for mask blank embedded defect detection and of pellicle to reduce mask defect adders.

• Expectation that EUV will be introduced at a few critical levels in N10 nanufacturing (replace LE3) with cost reduction benefit. Potential EUV area benefit from tip-to-tip and tip-to-line and pitch scaling, with redesign.

DSA is very promising

Van den hove described direct self-assembly (DSA) as “very promising” and Steegen said work there has largely focused on reducing defectivity. In DSA, resists that contain block copolymers are deposited on top of guiding structures. The self-directed nature of the process results in very regular patterns with very high resolution.

EUV F4

The trick with DSA is that it requires a double exposure to take away the random patterns at the edge of the device, and the resolution needed for this “cut mask” is also very high. “We’re convinced that it’s not a replacement for EUV or any high resolution lithography technique. We are very convinced it will be used in conjunction with EUV,” Van den hove said. “It certainly keeps the pressure on EUV very high.”

Steegen described DSA as a complimentary litho technique that is having quite some momentum. The process starts with a “relaxed” guiding pattern on your wafer.  Then, depending on the polymer length in the block copolymer, the space in between the guiding structure is replicated into multiple lines and spaces. “The defectivity of these materials are going to be key to bring the defects down. Our year end target is 60 defects/cm2 and this needs to go down even further next year,” she said.

EUV F3

Work at imec has shown that the polymers, with a hard mask on top, are robust enough to enable the etching of the patterns into silicon. “That’s fairly new data and very promising,” Steegen said. Imec is already looking at where DSA levels could be inserted into the logic N7 flow, with fins and spacers being primary targets. Steegen said the Metal1 level would be a challenge due to its irregular pattern. “That makes it not easy to be replaced with DSA, but we’re looking into techniques to do that,” she said.

Here’s how imec summed up DSA readiness:

• Good progress in material selection and integration flow optimization for line-multiplication down to 14nm, pattern transfer into bulk Si demonstrated.

• First templated DSA process available using SOG/SOC hard mask stack.

• Focus on defectivity reduction & understanding, currently at 350 defects/cm2, YE13 target 60 def/cm2

• Alignment and overlay strategy needs to be worked out

• First N7 implementation levels identified: Finfet (replace SADP EUV or SAQP 193i) and Via (replace EUV SP/DP or 193i LE3).

Intel stands firm on 450mm; challenged by defects at 14nm

Brian Krzanich, chief executive officer of Intel, said Intel is standing firm on 450mm development (despite rumors to the contrary), during a quarterly conference call with financial analysts. He also blamed defects on a slight push-out of next-generation 14nm technology.

When asked about 450mm plans, Krzanich said: “We have not changed our timing. We are still targeting the second, latter half of this decade. We continue to see great value in 450. It brings tremendous economic value to everybody who participates in it. We continue to work with our partners. We are here part of the joint development program in New York, continuing to work on 450. We continue to work with our partners, especially TSMC and Samsung and we are still targeting the back half of this decade. This is a long 10-year program when you really take a look at it. So I think you will get mixed signals throughout those 10 years,” he said.

As noted in my last post, progress is on track at the G450C consortia — an initiative by five big chip makers, Intel, TSMC, GLOBALFOUNDRIES, IBM and Samsung, partnered with New York state and CNSE — to develop 10nm capability on 450mm wafers in 2015 or 2016.

Krzanich also commented on the status of the firm’s 14nm roll out. “We continue to make progress with the industry’s first 14nm manufacturing process and our second generation 3D transistors. Broadwell, the first product on 14nm, is up and running as we demonstrated at Intel Developer Forum, last month. While we are comfortable with where we are at with yields, from a timing standpoint, we are about a quarter behind our projections. As a result, we are now planning to begin production in the first quarter of next year,” he said.  

When asked about why the delay, Krzanich said it was “simply a defect density issue,” and said it was just part of the development process. “As we develop these technologies, what you are doing? You are continually improving the defect densities,” he said. “As you insert a set of fixes in groups, you will put four or five, maybe sometimes six or seven fixes into a process and group it together, run it through and you will expect an improvement rate occasionally as you go through that,” he said. He said the fixes don’t deliver all of the improvements. “We had one of those,” he said. “Why do I have confidence? Because, we have got back now and added additional fixes, gotten back onto that curve, so we have confidence that the problem is fixed, because we have actually data and defects and so that gives us the confidence that we are to keep moving forward now.”

Intel has already started construction on a 450mm pilot line at its Ronler Acres location on Northwest Highway in Hillsboro. The D1X module 2 is about the same size (1.1 million square feet) as the original fab D1X and is built specifically for 450mm wafers. When the second module is complete, it will start up on 450mm wafers once it is equipped with appropriate manufacturing tools and gear.

Intel is currently equipping its D1X development fab to process 300mm wafers using 14nm manufacturing and expects to initiate production this year. While the D1X module 1 facility is 450mm-capable, it will come online as a 300mm fab.

Image by Portland Business Journal.

Image by Portland Business Journal.

Intel DX1

TSMC is the only other company with an effort underway to develop a 450mm production facility. In June 2012 it was reported that the Taiwanese government had approved a proposal to build a 450mm wafer fab in central Taiwan early in 2014. TSMC said back in 2011 that it planned to install 450mm pilot lines within a couple of established wafer fabs — Fab 12 in Hsinchu and Fab 15 in Taichung, Taiwan.