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The ConFab 2018 Update

A new wave of growth is sweeping through the semiconductor industry, propelled by a vast array of new applications, including artificial intelligence, virtual and augmented reality, automotive, 5G, the IoT, cloud computing, healthcare and many others. The big question facing today’s semiconductor manufacturers and their suppliers is how can they best position themselves to take advantage of this tremendous growth.

Finding answers to that question is the goal of The ConFab 2018, to be held May 20-23 at The Cosmopolitan of Las Vegas. Now in its 14th year, The ConFab is a conference and networking event designed to inform and connect leading semiconductor executives from all parts of the supply chain. It is produced by Solid State Technology magazine, the semiconductor industry’s oldest and most respected business publication.

Kicking things off will be IBM’s Rama Divakaruni, who will speak on “How AI is Driving the New Semiconductor Era.” This is hugely important to how semiconductors will be designed and manufactured in the future, because AI — now in its infancy — will demand dramatic enhancement in computational performance and efficiency. Fundamental changes will be required in algorithms, systems and chip design.  Devices and materials will also need to change.

Rama is well position to address these changes: As an IBM Distinguished Engineer, he is responsible for IBM Advanced Process Technology Research (which includes EUV technologies and advanced unit process and Enablement technologies) as well as the main interface between IBM Semiconductor Research and IBM’s Systems Leadership. He is one of IBMs top inventors with over 225+ issued US patents.

We’re also pleased to announce several other speakers at this point. Joining us will be George Gomba, VP of technology research at GlobalFoundries. George has overall responsibility for GlobalFoundries’ semiconductor technology research programs, including global consortia and strategic supplier management (and, like Rama, has a long history at IBM). The focus of George’s talk will be on EUV lithography.

Dan Armbrust, Founder and Director of Silicon Catalyst, the world’s first incubator focused exclusively on semiconductor solutions startups will also be on the dais. A frequent speaker at The ConFab, Dan has a great background, including President and Chief Executive Officer of SEMATECH, IBM VP, 300mm Semiconductor Operations, and Strategic Client Exec for IBM’s Systems and Technology Group.

Another great speaker is Tom Sonderman, President of SkyWater Technology Foundry. Tom also has a great background including GlobalFoundries’ VP of manufacturing technology, and two decases at AMD, where he had global responsibility for development, integration, support and scalability of automation and manufacturing systems in the company’s wafer fabrication and assembly operations. Prior to joining SkyWater, Prior to joining SkyWater, Tom was the group vice president and general manager for Rudolph Technologies’ Integrated Solutions Group. In this position, he created a Smart Manufacturing ecosystem based on big data platforms, predictive analytics and IoT.

We’re so excited about the other speakers we tentatively have lined up, our plans for several thought-provoking panels and much more, so stay tuned. You register and keep up-to-date by visiting www.theconfab.com. For sponsorship inquiries, contact Kerry Hoffman at khoffman@extensionmedia.com.  For those interested in attending as a guest or qualifying as a VIP, contact Sally Bixby at sbixby@extensionmedia.com.

Is the Semiconductor Industry Ready for Industry 4.0 and the IIoT?

An industrial revolution is in the making, equivalent some say to the introduction of steam power at the tail end of the 18th century. Known as smart manufacturing, Industry 4.0 (after the German initiative Industrie 4.0), the industrial internet of things (IIoT), or simply the fourth industrial revolution, the movement will radically change how manufacturing is done.
The first industrial revolution was based on water/steam, the second was due electricity, and the third was from automation.

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The semiconductor industry is sure to benefit by the “digitization” of manufacturing in that it’s an important component of the IoT explosion, along with smart homes, smart cities, smart health, etc. But is the semiconductor manufacturing industry – already one of the most advanced in the world – ready for the revolution? Will the cobbler’s children get new shoes?
I believe it will, but there are some major roadblocks that need to be overcome.

New innovation is required for a couple of reasons. First, the path to continued cost reduction through scaling has come to an end. The industry will continue to push to smaller dimensions and pack more functionality on a single chip because the world will always need super-advanced electronics for data servers, cloud computing and networking. But it’s looking to be an increasingly expensive proposition.

At the same time, the industry is looking to the Internet of Things explosion as the “next big thing.” The two most important aspects of IoT devices will be low power and low cost. Speaking at a press conference at Semicon Europa in October, Rutger Wijburg, Senior VP and General Manager Fab Manufacturing for GlobalFoundries put things in perspective: “The wave of the Internet of Things is building. There will be a massive wave with tens of billions of devices. What is very important for our industry is that the two waves that have been driving our industry for a very long time – computers and mobile – are slowing down.” He noted that the IoT represents massive volume, but it doesn’t need the most advanced technology. “What it needs are two things: low power and low cost,” he said.

Wijburg said a typical figure of merit in the mobile space is $0.25/mm2. “My estimation is that the massive volume going into the Internet of Things has to be delivered for ASPs (average selling price) between $0.05 and $0.10/mm2.

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How to bring the cost per square mm of silicon down by at least 5X from where it is today? “One of the things that the industry has done extremely well with is finding new ways of innovation to bring down the cost of the next node. That has actually been driving the Law of Moore for many, many years,” he said. “But at this moment, we are at a point where it doesn’t work anymore,” Wijburg said.

One solution outlined by Wijburg is FDSOI technology, which he said is less expensive than FinFETs and has other advantages as well. GlobalFoundries introduced a 22nm FD-SOI platform in July that will largely be manufactured at the plant in Dresden, Germany.

Beyond that, it’s like that some other kind of major innovation will be required to reduce costs. Work is underway to fabricate various kinds of electronics with printing with, for example, roll-to-roll inkjet printing. Indeed, a conference dedicated to printed electronics was co-located with Semicon Europa. But it’s likely that this technology will limited to relatively low-tech and novel devices (i.e., electronic tattoos).

Could the Industry 4.0 movement enable a dramatic reduction in costs? It’s possible, but it will take some time.

In a recent report, McKinsey defines Industry 4.0 as digitization of the manufacturing sector, with embedded sensors in virtually all product components and manufacturing equipment, ubiquitous cyberphysical systems, and analysis of all relevant data. It is driven by four clusters of disruptive technologies. The first consists of data, computational power, and connectivity – low-power, wide-area networks are one example. Analytics and intelligence form the second, while human-machine interaction is the third, comprising, for instance, touch interfaces and augmented reality. Digital-to-physical conversion is the fourth: advanced robotics and 3D printing are two examples.

Proponents of Industry 4.0 say greater connectivity and information sharing — enabled by new capabilities in data analytics, remote monitoring and mobility — will lead to increased efficiency and reduced costs. There will be a paradigm shift from “centralized” to “decentralized” production. There will also be greater efficiency across the supply chain, and more companies involved in the supply chain, providing services such as security.

Industry 4.0

I know what you’re thinking. The semiconductor industry embraced all these things years ago. It’s the poster child for this kind of thing!

Sadly, there’s a long way to go to realize the kind of data sharing and “digitization” embodied in the Industry 4.0 concept. “The set of problems getting to 4.0 is profound,” said Nick Ward, director, marketing service group, Applied Global Services, Applied Materials. Ward, who presented on the topic at Semicon Europa, said data collection is not the issue in that the semiconductor industry has been collecting data for a long time, with a 40% increase node-to-node. “The MES is constantly being asked for more granularity and higher speed,” he said.

The challenge is that the industry has been extremely secretive, to the point where people entering the fab aren’t allowed cell phones with cameras.

Ward said the industry will need to change how it thinks about IP. There needs to be a new data structure that allows it to be shared in some way, with “broad brush” IP treated differently than what’s really important.

“Industry 4.0 is about marginal gains,” Ward said. “It’s not about ‘give me all your data.’”

What we really need is a map that includes process data, design data and financial data, Ward said.

He pointed to the open innovation models presently being explored by companies such as GE, GM and Ford as something the semiconductor industry should consider.

Update: The day after this was posted, Mentor Graphics introduced new tools for Industry 4.0, although targeted at the PCB industry (which is not as secretive as the semi industry).

Additional reading: Industry 4.0 — Opportunities and Challenges of the Industrial Internet

GLOBALFOUNDRIES’ Kengeri to speak at The ConFab

Subramani Kengeri, Vice President, Advanced Technology Architecture at GLOBALFOUNDRIES will speak at The ConFab 2014 on the “techno-economics” of how the relatively small semiconductor industry ($350 billion or $0.35 trillion) is driving the $85 trillion gross world product (GWP). He notes that semiconductors are only a fraction of GWP, but a critical enabler of global economic growth and productivity. Cost effective technology innovations have kept Moore’s law alive, although techno-economic challenges are mounting on each successive node. The cost of building a new advanced fab has reached $6B. Process development and chip design costs are going up astronomically, while next generation SoCs in the IoT era are pushing cost-per-function to unprecedented levels, he says. His talk will review advanced design and silicon technology challenges posing threats to cost effective scaling, potentially impacting global GWP and productivity. 

Subramani (“Subi”) is responsible for defining competitive process architecture on advanced nodes in support of “first time right” technology development. He is responsible for determining the technology feasibility, competitiveness and manufacturability of all elements of technology platform and to establish the advanced technology roadmap for GLOBALFOUNDRIES.

Subramani joined GLOBALFOUNDRIES in 2009 as the Vice President of Design Solutions. He implemented strategic Design enablement initiatives and established a strong foundation for collaboration with Design eco-system, before moving to focus on R&D. He started his Semiconductor career at Texas Instruments and prior to joining GLOBALFOUNDRIES, he was the Senior Director of Design and Technology Platform at TSMC.

 

No technical barriers seen for 450mm

Paul Farrar, general manager of the G450C consortium, said early work has demonstrated good results and that he sees no real barriers to implementing 450mm wafers from a technical standpoint. Speaking at the SEMI ISS meeting in January, Farrar showed impressive results from, etch, CVD, PVD, CMP, furnaces, electroplating, wet cleans and lithography processes and said the inspection/metrology tools were in place to measure results. “I don’t believe we will find fundamental technology limiters,” he said. “But we will have to keep working to find ways to maximize the efficiency.” Gaining such efficiencies are critical in order to meet the cost-saving goals of the program. “In the end, if this isn’t cheaper, no one is going to do it,” he said.

G450C is a consortium based at the CNSE campus in Albany, NY. It is financed by Intel, TSMC, Samsung, IBM, GLOBALFOUNDRIES, and New York State (CNSE). “Our job is to make it as easy as possible to innovation and be collaborative between the semiconductor makers and our key friends in the industry who enable the 450 work to be done in an economic way,” Farrar said.

At the end of 2013, G450C at 34 tools delivered to its 50,000ft2 fab in Albany, with another 7 tools in place at partner’s facilities. “The FOUPS are going, the overhead transport is well underway and some of the cleanroom is actually starting to look like a cleanroom,” Farrar said.

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Farrar started with etch results, saying they were “starting to see some pretty good data – 3 sigma at about 2%. Yes, there’s still some work to get to the very edge of the wafer but relatively good progress and good jobs on gas delivery, etc.

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He showed good results with both oxide and silicon nitride CVD, with close to 1.5mm edge exclusion. “It’s very representation data from early in the program,” Farrar said, noting that they were starting to pattern some of the more complex oxides.

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He said the goal for PVD was to demonstrate better than 5% uniformity. “We know we have step coverage challenges for both the 10 and 7nm nodes. There’s tremendous work going on in the injection rings for gases, high density plasmas from multiple RF sources, but again some progress to me made but pretty good data for right out of the chute,” he said.

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CMP results demonstrated repeatability less than 4%. “Very good job done by our suppliers,” Farrar said.

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Farrar described data from furnaces as reasonably good. “We still need to do more characterization at what I call the micro level,” he said. “We see some hot spots on the edge, but we’re starting to work on those.”

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Also “pretty good data” from electrochemical plating (ECP) of copper. “Well done here,” Farrar said. “The challenge is thermal and pattern loading effects, and gap fill.”

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More of the same with wet cleans. “We’re starting to see some pretty good particle data. We’re cleaning wafers relatively well. We are seeing a few things like what I would call micro-metallic contamination that can grow some things so we’re still working on that. But from a particle removal standpoint, pretty good unit process work,” Farrar said.

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Farrar acknowledged that lithography remained as one of the biggest challenges in the 450mm transition, but showed good results from directed self assembly across a 450mm wafer, and said the consortium had a very strong partnership with Nikon. “We’re working with them and we’ve seen some tremendous progress at their factory,” he said. “I’m fully confident that we’ll have capability by July to run patterned wafers. Immersion is going to be the workhorse. I think that’s a key enabler to get to 450mm.” He said the industry would have to see how the economics of EUV played out later in time. “I don’t think it’s going to be early in time,” he said.

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Farrar seemed to draw hope from the earlier transition from 200mm to 300mm wafers, which started around 1998.  “By 2008, we were getting more than 2X the number of wafers per tool out compared to what was going in 2003. There was about a 70% improvement over 5 years,” he said.