Tag Archives: Moore’s Law

Semiconductor Materials: Growth, Opportunities and Challenges

Don’t miss this week’s webcast on Thursday at 1:00 pm Eastern, 10:00am Pacific.

We have two great speakers lined up. First, Lita Shon‐Roy, President/CEO of Techcet, will provide an overview of chip level materials markets, focusing on growth and opportunities. Next, SRC’s Jon Candelaria, Director, GRC Interconnect and Packaging Sciences, will describe how today’s researchers are exploring materials challenges beyond Moore’s Law.

Click here to register.

Here are some more details:

Lita will talk about how current 3-dimensional structures present new challenges relating to uniformity, lithographic resolution, high aspect ratio etching and fills, and planarization while addressing continuing need to stay at or below current technology node scaling.  What do these challenges really mean in terms of changing material requirements and materials growth opportunities?  In her presentation, Lita will highlight those processes that must have better, alternative process materials, and provide market forecasts on these materials opportunities.

In his presentation, Jon will focus on how the electronics industry is facing a growing crisis in being able to continue providing cost-effective processes and designs to support the continuation of what’s been referred to as ‘Moore’s Law.’ This ‘Law’, or more accurately ‘observation of the economics involved in scaling integrated circuits,’ has been a very useful guideline for several decades, but as with any similar types of projections, has been expected to some day run its course. While the exact timeframe is still uncertain, that ‘day’ is now within sight, and yet there are still no clear paths forward beyond that point. This presentation will provide a brief glimpse of some of the key materials-related challenges that exist within the frontend (devices), lithography, and backend-of-line (chip level interconnects). It will also include just a few of the research concepts that offer some potential paths forward, which the Semiconductor Research Corporation and its member companies are exploring alongside the university researchers they are supporting.

And speaker bios:


Lita Shon‐Roy, President/CEO of Techcet, has worked in the electronics materials industry in business development and technical marketing for more than 25 years. Her work experience spans from business development, marketing and sales of IC’s, equipment, and materials to process development of flat panel displays (TFTs). She has developed new business opportunities for companies such as RASIRC/Matheson Gases and IPEC/Speedfam and helped establish marketing and sales proficiency in companies such as Air Products/Schumacher, Brooktree/Rockwell, and Hughes Aircraft. Lita helped build IPEC as a leader in CMP equipment as Director of International Sales. In 1998, Lita cofounded Techcet Group, LLC. She has authored and co‐authored various articles and texts focused on the semiconductor processing, industry forecasting, and the world economy and is now a recognized expert in electronic materials marketing and business development. Lita holds a Master’s Degree in Electrical Engineering, with a specialty in Solid State Physics from USC and a Bachelor’s Degree in Chemical Engineering from UCSD. She is currently completing her MBA at California State University, Dominguez Hills.


Jon Candelaria, Director, GRC Interconnect and Packaging Sciences

Jon Candelaria has over 35 years of experience in the electronics industry in a wide variety of engineering and managerial roles. He was most recently a Distinguished Member of the Technical Staff at Motorola’s Applied Research & Technology Center before joining the SRC in September, 2010 as the Director for Interconnect and Packaging Sciences. He has over a dozen issued patents and published technical articles, and received the Motorola Patent of the Year Award for an invention which contributed over $1B to Motorola over the course of its lifetime. He served as Technical Program Chair and General Chair of the IEEE Electron Devices Society’s flagship conference, the IEDM. Jon was the V.P. of Conferences for the IEEE’s Electron Devices Society (EDS), the EDS representative on a joint United Nations-IEEE Humanitarian Challenge advisory committee, and was Chair of both the IEEE Computer Society and Laser and Electro Optics Society Phoenix Chapters. He is currently the Treasurer and Technical Program Committee member for the International Interconnect Technology Conference (IITC), and is a member of the Editorial Panel for Future Fabs International.

Can we take cost out of technology scaling?

There is much talk these days about continued scaling, including some recent posts by my colleague Ed Korczynski, in “Moore’s Law is Dead” Part 1 (What?) and Part 2 (When?). At The ConFab in June, keynote speaker, Dr. Gary Patton, vice president, semiconductor research and development center at IBM, talked about scaling, adding some historical perspective. I previously blogged about the “three fundamental shifts” that Patton believes will lead to a bright future for the semiconductor industry.

“We will keep scaling,” he said. “We have shown a tremendous ability to innovate and keep moving that technology forward.”

In the 1990s, Patton notes that life was actually pretty simple. “You brought in a new lithography tool, you scaled the horizontal dimensions, you scaled the vertical dimensions and you got a new technology out. It was better performance, the same power density, and you could do a lot more on the chip,” he said.


Around 2000, we hit the gate oxide limit. “Gate oxide got to be abount three atomic layers. We could have said at that point ‘game over, scaling has ended.’ But guess what, we innovated. We came up with a pretty fundamental shift in ideas which is let’s change the fundamental properties of silicon. If we can strain the silicon, we can enhance the mobility. We can change the gate oxide. We can enhance the coupling between the gate and the channel. And that’s what we get over that last decade. We said let’s go from SRAM to a very high performance eDRAM (embedded DRAM) so we can put a lot more memory next to the processor because we knew memory was a key gating factor for the processor speed. This enabled the personal computing era and smart consumer electronics,” Patton said.

In 2010, we were at another one of these inflection points. “It’s not surprising that the improvements in 20nm are less than people would like because we really reached the end of the planar device era. Again, we were saying ‘game over, we’re done scaling.’ But no, we continue to innovate. The next decade is really about 3D. 3D devices, finFETs, or 3D chip integration,” he added.

Patton said that design technology co-optimization will be a key piece of getting through the next decade. “That will probably take us to about 2020,” he said. At that point we’re going to “hit the atomic dimension limit and we’re going to have to do it all over again. Here, we’re going to get into nanotechnology. Nanowire devices, silicon nanowires, carbon nanotubes, photonics and multi-chip stacking to bring things together. That will enable wearable computing, everywhere connectivity and cognitive computing.”

Patton said the problem is not physics. “We’re going to have solved the physics problems,” he said. “The problem is financial.” Patton showed a chart (below) that depicted the history of our industry from 1980 to present. “What drove the industry was smaller features, which enabled better performance and better cost per function. It enabled new types of applications, and that enabled larger markets. If you look in this time period, there’s about a six order of magnitude improvement in cost per transistor and that enabled a seven order of magnitude increase in consumption of silicon transistors,” he said.


The challenge we’re facing right now is depicted below, showing the compound growth rate reduction and the cost of a circuit. On the x-axis is linear scaling. “We’ve typically targeted about a 0.7X linear scaling, which means from an area perspective, you get about 50% improvement. Note the line, 50%, doesn’t go through 50% improvement because with each new technology, there is some increase in complexity. It might be more like 30% improvement at the die level. If we’re really good and provide some enhancements in the technology, self-aligned processes, things like that, we may get it to 40%. So 30-40% is about the range we’ve been getting in terms of the cost per die improvement as we scale up.


“The challenge we’re facing now is two fold. Number one, we’re struggling to get that 0.7X linear scaling. It might be about 0.8X. And we’re adding a lot more complexity, especially when you adding double and triple patterning .The focus today in innovation has got to be heavily focused on ‘how do we drive cost?’ Not just how do you scale, because scaling would add a lot of extra cost at this point. How do we drive cost down, how do we keep adding value to the technology. The model is changing. Moore’s Law can still hold, but we have to focus on the cost equation. So there’s really two parts. Technology innovation which is focusing on the patterning, focusing on the materials, the processing, and how do we drive that to take cost out of the technology scaling,” Patton said.

Three fundamental shifts

At The ConFab last week, Dr. Gary Patton, vice president, semiconductor research and development center at IBM, said there is a bright future in microelectronics (I heartily agree). He said that although there seems to be a fair amount of doom and gloom that scaling is ending and Moore’s Law is over, he is very positive. “There are three huge fundamental shifts that are going to drive our industry forward, will drive revenue growth and will force us to keep innovating to enable new opportunities,” he said.

The first fundamental shift is the explosion of applications in the consumer and mobile space. Patton noted examples such as cars that can drive themselves and can detect people and bicyclists and avoid them, smart phones for as little as $25, wearable devices that not only tell you what you’re doing but how you’re doing, and 4K television. “That is an incredible TV system, but it’s going to demand a lot of bandwidth; twice the bandwidth that’s out there today. If you turn on your 4K system, your neighbors are going to start to notice it when they try to access the internet,” he said.

Patton said that it’s estimated that today there are about 12.5 billion devices connected to the internet. That’s expected to grow to $30 billion by 2020. This represents the second fundamental shift commonly known as Big Data. “All these interconnected devices are shoving tremendous amount of data up into the cloud at the rate of 1.5 Exabytes (1018) bytes of data per month,” Patton said. “And that’s grown by about an order of magnitude in just the last 13 years. The estimate is that in the next 4 years, it’s going to go up another order of magnitude. It’s accelerating.”

The third fundamental shift is with all this data going up into the cloud, the data is almost all unstructured data, such as video and audio. “It’s related data but disconnected. How do we take that data and do something with it? That brings us to analytics and cognitive computing. We have really just started in this arena.”

So there you have it. Three reasons to be very positive about the future of the semiconductor industry: an explosion of applications, the rise of big data and the need to analyze all that data.