3D-Integration

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3D Packaging Processes

Mon, 3 Mar 2008
adapted for print by AP editors

(March 5, 2008) — This article is the third in a series on 3D packaging technology, and summarizes information presented during a January 2008 webcast hosted by Advanced Packaging magazine. Participants were: Fred Roozeboom, Research Fellow, NXP Semiconductors and professor at TU Eindhoven; Kai Zoschke, Research Engineer for Fraunhofer IZM; and Thorsten Matthias, Director of Technology North America, EV Group.

System-in-Cube Technology Addresses Parasitics, KGD

Tue, 3 Mar 2007
(March 7, 2007) COSTA MESA, CA — Irvine Sensors Corporation demonstrated its 3D packaging technologies to stack four 500-mHz DDR memory chips without operating-speed degradation, which was verified by the chip maker. The company will now explore commercial exploitation of packaging techniques for the memory chips.

Samsung Develops DRAM Stack with TSVs

Mon, 4 Apr 2007
(April 23, 2007) SEOUL, South Korea — Samsung Electronics Co., Ltd., has developed an all-DRAM stacked-memory package using through-silicon vias (TSVs) housed in aluminum pads to avoid performance slow-downs caused by the redistribution layer. The company applied a proprietary wafer-thinning technique to eliminate warped die in the low-profile package.

IEEE Recognizes Fraunhofer's Reichl

Wed, 4 Apr 2007
(April 18, 2007) BERLIN — The IEEE components, packaging, and manufacturing technology (CPMT) society — an international forum for scientists and engineers in microsystems packaging design and manufacture R&D and development — named professor Herbert Reichl, director of Fraunhofer IZM, recipient of its electronics manufacturing technology award.

Consumers, Integration Dictate Future of MEMS, 3-D Packages

Wed, 1 Jan 2007
(January 24, 2007) LYON, France and PITTSBURGH — The future of MEMS and 3-D packages relies on similar factors — consumer drivers and increased integration — according to industry analysts. 3-D integration will affect MEMS and IC packaging industries, says Yole Développement's "3-D ICs." Advanced packages require acceptance from the consumer market to reach targets for technological advancement, commercialization, and sector revenues.

Thin-wafer Handling System

Tue, 7 Jul 2007
A polymeric spin-on coating, WaferBOND HT-250, temporarily attaches device substrates to a carrier substrate, enabling wafer thinning and subsequent processing. It will reportedly permit advanced packaging processes such as the creation of through-silicon vias (TSVs), 3D stacking, and other etching, plating, and follow-on processes.

CEA Installs Alcatel Systems for TSVs

Mon, 7 Jul 2007
(July 23, 2007) GRENOBLE and ANNECY, France — Alcatel Micro Machining Systems will provide two 200-mm DRIE and LTPE CVD systems at CEO/Léti-Minatec R&D institute under a joint development agreement. The parties will collaborate to develop and demonstrate a suite of turnkey silicon microvia technologies for 3D integration at wafer and die levels.

Seminar Series Targets Integrated Process Solutions for 3D Packaging

Tue, 9 Sep 2007
(September 25, 2007) MUNICH, Germany— SUSS Microtec, NEXX Systems, and Surface Technology Systems (STS), manufacturers of semiconductor process equipment, announced their collaboration with Fraunhofer IZM to demonstrate integrated process solutions for 3D wafer-level packaging (WLP).

Embedded Passives' Role in 3D Packaging

Mon, 10 Oct 2007
By Happy Holden, Mentor Graphics, Inc.
3D packaging technology is evolving rapidly to improve functionality and performance while maintaining a compact form-factor. Embedded passive components (EP) will play a major role in all of these 3D schemes.

Invensas, Allvia ink 3D IC tie-up

Tue, 11 Nov 2011

Invensas has "acquired" dozens of 3D IC packaging patents from Allvia, and the two have agreed to further collaboration in the area.


3D packaging enters the mainstream: Attend the conference

Tue, 11 Nov 2011

2.5D, 3D and Beyond - Bringing 3D Integration to the Packaging Mainstream will take place November 9 in Santa Clara, CA. The MEPTEC conference follows the trend of 3D and 2.5D packaging moving from roadmap to factory production.


Xilinx FPGA boasts 6.8B transistors

Tue, 10 Oct 2011

Xilinx Inc. (Nasdaq:XLNX) began shipping its Virtex-7 2000T field programmable gate array (FPGA), a programmable logic device with 6.8 billion transistors: 2 million logic cells, a die-stack architecture, low power consumption, and a more flexible design than large ASICS and monolithic FPGAs.


TSV electroplating dev team unites SVTC, Amerimade Technology, Shanghai Sinyang Semiconductor Materials

Wed, 10 Oct 2011

Nanotech accelerator SVTC Technologies, wet chem equipment maker Amerimade Technology, and chemicals company Shanghai Sinyang Semiconductor Materials will collaborate on electroplating processes for TSV that are production-ready for advanced packages and MEMS.


SUSS MicroTec wins thin-wafer temporary bonder order

Tue, 10 Oct 2011

SUSS MicroTec, in partnership with temporary bonding adhesive maker TMAT, will deliver SUSS MicroTec's new-generation high-volume temporary wafer bond tool clusters to a leading IDM.


Fraunhofer, EVG develop temporary wafer bonding for thicker die

Tue, 10 Oct 2011

EV Group (EVG) will work with Fraunhofer IZM's ASSID research center to develop temporary bonding/debonding technologies for thicker die structures, some as large as 600

Fraunhofer IZM's packaging center installs Altatech CVD

Tue, 10 Oct 2011

All Silicon System Integration Dresden (ASSID) installed an Altatech 300mm CVD tool for dielectric film deposition on advanced through silicon vias (TSV), with diameters as small as 10

Thin wafers win majority in electronics by 2016

Thu, 10 Oct 2011

Thanks to MEMS, 3D packaging, LEDs, power devices, and other applications, thinned wafers will be the majority of wafers in the market by 2016, according to Yole D

Rudolph wins TSV inspection systems order

Mon, 10 Oct 2011

Rudolph Technologies Inc. (NASDAQ:RTEC) shipped its Wafer Scanner 3880 3D Inspection System, multiple NSX Macro Defect Inspection Systems and its Discover Yield Management Software Suite to a leading semiconductor manufacturer for use in developing through silicon via (TSV) structures.


Samsung embedded memory fits 8 die in 1.4mm stack

Thu, 9 Sep 2011

Samsung Electronics Co. Ltd. developed a high-performance 64GB embedded memory with 64Gb NAND. The package contains an 8 die stack in a low profile for smartphones, tablets and other mobile devices.


IMAPS International 2008 In Review

Mon, 11 Nov 2008
By Gail Flower, Editor-in-Chief
This year's IMAPS International Symposium had great international participation, good attendance and excellent presentations from keynoters to the technologically cutting-edge educational papers. It was election day when the IMAPS conference began, and by the second day of the conference, a new president entered the picture. Therefore, the first day proceeded without a rush of attendees as expected, but the second perked up with lively conversation.

Dual-purpose 300mm dicing frame prober

Mon, 11 Nov 2008
The WDF 12DP is designed to address increased demand for probing ultrathin and diced wafers, and wafer-level testing of chip-scale and wafer-level packaging, stacked, and 3D technologies, as well as KGD testing of ultra-hin wafers, singulated wafers, and strips on a dicing frame.

Electronics Industry Association News

Mon, 7 Jul 2008
(July 14, 2008) — IMEC and Qualcomm collaborate on 3D packaging technologies; IPC meets internationally to discuss urgent trends; iNEMI releases recommendations for lead-free alloy alternatives.

STMicroelectronics to Manufacture TSV-based Image Sensors on EV Group 300-mm Tools

Tue, 7 Jul 2008
(July 8, 2008) ST FLORIAN, AUSTRIA — EV Group(EVG)announced the order and successful installation of its 300-mm bonding, alignment, and photoresist fully automatic processing tools at ST Microelectronics'(ST) 300-mm through-silicon-via (TSV) pilot line in Crolles, France. The company says the tools will be used in the manufacture of CMOS imaging sensors (CIS) Using TSV technology.

Mask Aligner for 3D Packaging

Tue, 7 Jul 2008
The second-generation SUSS MA300, from SUSS MicroTec is a highly automated mask aligner platform for 300-mm and 200-mm wafers. Specifically designed for 3D packaging, it features a dedicated alignment kit for creating 3D interconnects for applications like chip stacking and 3D image sensor packaging. It also targets wafer bumping and wafer level packaging (WLP) applications, but can be used for other technologies where geometries in the range of 5 and 100 µm must be exposed.

June Names in the News

Mon, 6 Jun 2008
(June 30, 2008) It was a month for names in the news as acquisitions and evolving business strategies inspired executive appointments and reorganization; industry organizations added members and directors, and books got published. Company announcements came in from JP Sercel Associates, TRUMPF, Dage Precision Industries, ECD, Jordan Valley, Rogers Corp., Formfactor, Unisem Group, Mentor Graphics, and Alchimer.

Photonic Interconnects Enable the Continuation of Moore's Law

Tue, 11 Nov 2008
By Fran

SEMICON Europe: Connecting Companies for 3D Interconnects

Fri, 10 Oct 2008
By Paul Collander, Poltronics, Inc. At the recent Advanced Packaging Conference at SEMICON Europe in Stuttgart, Germany, (October 7-9, 2008) Fran

IMEC Research Energetically Stacks Up

Tue, 10 Oct 2008
by Gail Flower, Editor-in-Chief, Advanced Packaging
IMEC remains on the forefront of research in many areas including nanotechnology, RF MEMS packaging, flip-chip, substrates, organic electronics, CMOS-based research, solar cells, and 3D stacked integrated circuits. In 3D stacked packages an area of predicted high-growth, IMEC has announced notable achievements.

Advanced Materials CVD and ALD Tool

Tue, 10 Oct 2008
The AltaCVD chemical vapor deposition (CVD) and atomic layer deposition (ALD) tool from Altatech combines a unique vaporizer technology, chamber design, and gas/liquid panel integration. The combination of a proprietary reactor design and precursor introduction path with a pulsed liquid injection and vaporization is said to enable nanoscale control of thickness, uniformity, composition, and stoichiometry in complex materials.

Online Interview: Ziptronix Joins Low-cost Quest for True 3D-IC

Tue, 10 Oct 2008
By Fran

X-Ray Inspection Identifies Flip Chip Detects

Tue, 9 Sep 2008
Using 2D and 3D X-ray techniques to find and confirm manufacturing defects in flip-chip devices
By Evstatin Krastev, Ph.D. Dage Precision Industries, a Nordson Company
While flip chip design eliminates excessive packaging, high-density flip chip devices place a greater burden upon device inspection. The combination of 2D x-ray and CT analysis offers powerful analytical capabilities need for the complete inspection of flip-chip devices and stacked packages.

SEMICON West Exhibitor 2008 Spotlight

Tue, 7 Jul 2008
by Fran

DNP Develops Slim Leadframe

Thu, 1 Jan 2009
(January 29, 2009) TOKYO — Dai Nippon Printing Co. Ltd. (DNP) developed a package leadframe to slim down the semiconductor package mounted on electronic devices. The leadframe enables known good die (KGD) semiconductor packaging with a thickness of 0.15 mm, using precision plating processes.

Replisaurus/S.E.T. to Collaborate with IMEC on 3D Integration

Tue, 1 Jan 2009
(January 13, 2009) SAINT JEOIRE, France — Smart Equipment Technology (S.E.T.), a wholly-owned subsidiary of Replisaurus Technologies, announced a collaboration with IMEC to develop die pick-and-place and bonding processes for 3D chip integration using S.E.T.'s flip chip bonder equipment. As part of the collaboration, S.E.T. will join IMEC's Industrial Affiliation Program (IIAP) on 3D integration.

3D Packaging Technologies Steal the Show at IMAPS

Tue, 4 Apr 2008
By Fran

Wafer Bonder for CMOS Image Sensors

Tue, 9 Sep 2008
In response to market needs for 300mm process equipment capabilities to demonstrate 3D processes, SUSS MicroTec has introduced The XBC300. The XBC300 is designed for 3D integration and 3D packaging with through silicon vias (TSVs) and is ideal for the CMOS image sensor (CIS) early adopter market.

Online Interview: Wilfried Bair, SUSS MicroTec, Talks 3D

Thu, 9 Sep 2008
(September 25, 2008) WATERBURY, VT — Things may appear to be slow right now in the semiconductor industry, but fab expanision due to the 300mm transition, the focus of resources on improving factory efficiency, and the expected adoption of through silicon vias (TSVs) bodes well for equipment manufactures in 2009. Wilfried Bair, VP business development and general manager, Bonder Division talked to AP about how SUSS MicroTec is getting ready for 300mm and 3D integration.

SMT Magazine Presents Packaging Panel at IPC Midwest

Wed, 9 Sep 2008
(September 24, 2008) SHAUMBURG, ILSMT editor-in-chief Gail Flower chaired a panel comprising equipment supplier, laboratory, EMS provider, and consultant voices at IPC Midwest in Schaumburg, Ill. David Geiger, Flextronics International; Jacques Coderre, Unovis Solutions; Vern Solberg, STI - Madison; and Gene Dunn, Panasonic Factory Solutions of America spoke about emerging packaging technologies.

3D Technology and Beyond: 3D All Silicon System Module

Tue, 9 Sep 2008
By Ritwik Chatterjee, Ph.D., and Rao R. Tummala, Ph.D, Packaging Research Center—Georgia Institute of Technology
There is a need for miniaturization at the IC, module, and system levels. There is stil research and development required to bring this hetero-integration technology to cost-effective implementation with required reliability and performance needs. In addition to the module level, we must focus on performance, form factor, cost, and reliability of the entire system.

EV Group and Brewer Science Establish Ultra-thin Wafer Bonding Lab

Wed, 1 Jan 2009
(January 7, 2009) ST. FLORIAN, Austria and ROLLA, MO— In response to a call for localized support and increased demand of 3D IC process development in Asia Pacific, EV Group (EVG) and Brewer Science, Inc. have set out to outfit an ultra-thin wafer bonding lab in Taiwan. To this end, the companies announced the installation of an EVG 500 series wafer-bonding system at Brewer Science's Taiwan applications lab in Hsinchu Science Park.

EVG, AMAT pair for 3D thin-wafer bonding

Fri, 7 Jul 2009
EV Group and Applied Materials say they will jointly develop wafer bonding processes for making through-silicon vias (TSV) in 3D IC packaging applications, working as members within the Semiconductor 3D Equipment and Materials Consortium (EMC-3D).

Stepping up to the 3D challenge

Wed, 7 Jul 2009
Soitec's president and CEO, André-Jacques Auberton-Hervé, discusses the three pillars of 3D integration at the wafer level, as well as bonding at room temperature. Also noted is Soitec's partnership with IBM, announced during SEMICON West.

SEMICON West: Jan Vardaman and Paul Siblerud Analysis

Fri, 7 Jul 2009
Paul Siblerud, SEMITOOL, discusses the role of the EMC-3D consortium in developing new packaging technologies, such as through silicon vias (TSV). Jan Vardaman, TechSearch International, examines the barriers, and breakthroughs, around 3D integration.

3D integration: A status report

Tue, 7 Jul 2009
3D IC technology, an alternative approach to wire-bonded chip stacking utilizing interconnets with through-silicon vias (TSVs) fabricated with front-end-like processes, is a hot topic at SEMICON West, and the focus of an on-line virtual forum hosted by public relations firm MCA.

SUSS, Thin Materials Cooperate on Temporary Bonding for 3D Packaging

Wed, 7 Jul 2009
(July 8, 2009) GARCHING and MUNICH, Germany — SUSS MicroTec and Thin Materials, a semiconductor process development company, are cooperating on a temporary bonding solution to be used for challenging thin wafer handling technologies required for emerging 3D integration and packaging technologies. With this cooperation SUSS MicroTec extends its solution portfolio for temporary bonding and thin wafer handling.

AMAT Joins EMC-3D Consortium

Tue, 2 Feb 2009
Applied Materials, Inc. has joined the international EMC-3D semiconductor equipment and materials consortium, which focuses on 3D chip stacking and MEMS integration.

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Mon, 2 Feb 2009
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GLOBALFOUNDRIES, Amkor co-develop semiconductor assembly and test methods

Mon, 8 Aug 2011

GLOBALFOUNDRIES entered into a strategic partnership with Amkor (NASDAQ:AMKR) to develop integrated semiconductor assembly and test processes for advanced silicon nodes. The aim is integrated fab-bump-probe-assembly-test steps that can be commercialized across multiple customers and end-market applications.


Package-on-package (PoP) track at SMTAI

Wed, 8 Aug 2011

The SMTA will host conference events with Amkor, Research in Motion, and TechLead Corporation on package-on-package (PoP) 3D stacking at SMTA International (SMTAI), October 16-20 in Fort Worth, TX.


Inside the Known Good Die conference

Wed, 8 Aug 2011

The annual Known Good Die (KGD) conference, taking place Nov. 10 in Santa Clara, CA, will address semiconductor die testing, assembly, manufacturing, and business challenges, with the tagline "KGD in an Era of Multi-Die Packaging and 3D Integration."


MEMS, 3D packaging major factors in iNEMI roadmap

Tue, 8 Aug 2011

The 2011 iNEMI Roadmap, published by the International Electronics Manufacturing Initiative (iNEMI), includes a new chapter on MEMS and sensors, and an expanded chapter on packaging to include substrates discussions.


SEMI convenes system-in-package summit alongside SEMICON Taiwan

Fri, 8 Aug 2011

SEMI will hold the first-ever SiP Global Summit, September 7-9, co-located with SEMICON Taiwan. Three forums cover system in package (SiP) test, the "3D IC era," and the requirements of mobile electronics.


Lack of EDA tools, thermal issues impeding 3D packaging technology

Wed, 8 Aug 2011

Amkor's Ron Huemoeller shares his thoughts about two panels from SEMICON West, on 2.5D silicon interposer packaging technologies and its supply chain, and 3D packaging technology and its ecosystem.


TI achieves volume production with stacked clip-bonded QFN

Thu, 7 Jul 2011

Texas Instruments has shipped more than 30 million units of its PowerStack packaging technology, a combination of chip stacking and clip bonding that is designed to improve performance and chip densities in power management devices.


TSV zen comes down to wafer processing balance

Tue, 7 Jul 2011

3D semiconductor packaging processes involve various groups, and standards are important in the hand-offs between them, explains Mark Berry, sales director at Metryx. He covers how to use metrology to protect wafer yields in 3D packaging.


3D IC with TSV show significant advances in last 12 months

Tue, 7 Jul 2011

Dr. Phil Garrou summarizes the significant commercial strides made over the past 12 months in 3D IC integration -- as defined vs. other "3D" technologies -- thanks to the promised combination of low cost and high performance.


Suss MicroTec 3D IC workshop addresses thin wafer handling and testing

Mon, 7 Jul 2011

At SEMICON West, 100+ attendees gathered at the Suss MicroTec workshop "3D Integration: Are we there yet?" to hear technical experts from around the globe to present updates on the status of 3D technology.


Optomec aerosol jet printing featured as wire bond, TSV alternative at IMAPS Device Packaging

Tue, 3 Mar 2011

Optomec Aerosol Jet product manager Mike O’Reilly will give a presentation titled "Aerosol Jet Printing as an Alternative to Wire Bond and TSV Technology for 3D Interconnect Applications" at the IMAPS Device Packaging Conference on March 9.


Samsung announces wide I/O DRAM with TSVs for mobile apps

Sun, 2 Feb 2011

Weeks after announcing a 40nm 8GB DDR3 memory with 3D through-silicon vias (TSV), Samsung is showing a wide I/O 1GB DRAM also utilizing 3D TSVs, targeting mobile applications.


K&S high volume fine pitch Cu wire bonding

Wed, 2 Feb 2011

Figure. Copper transition and roadmap planning. SOURCE: Kulicke & SoffaAs gold becomes more expensive, copper wire bonding becomes more appealing for chip packaging. Reverse bonding, fine-pitch bonding, looping, second bonds, and other technologies are ramping on roadmaps, according to Kulicke & Soffa (K&S).


Advanced transmission lines replacement for TSVs

Fri, 2 Feb 2011

Jamal Izadian, co-founder & president of RFCONNEXT, makes the case for shaped membrane transmission lines (SMTL) for use in high-speed 3D packaging applications. SMTL supports and improves flip-chip, micro-bumping, wafer thinning, system-in-package (SiP), package-on-package (PoP), and other packaging processes by extending the bandwidth and high-speed limits of these technologies.


Semiconductor industry veteran takes helm at Minco Technology Labs

Fri, 1 Jan 2012

Minco Technology Labs, hi-rel semiconductor die processing, packaging and test provider, appointed board member Bill Bradford as president and CEO.


Samsung Electronics ramps embedded multi-chip packaging with memory products

Thu, 1 Jan 2012

Samsung Electronics began producing embedded multi-chip package (eMCP) memory for use in entry- to mid-level smartphones. The products use low power double-data-rate 2 (LPDDR2) 30nm DRAM and 20nm NAND flash memory.


Optomec expands aerosol jet lab for 3D semiconductor packaging, PV, other device formation

Thu, 1 Jan 2012

Optomec opened its new and expanded Advanced Applications Lab and Product Development Facility in St. Paul, MN. The facility will help Optomec grow its Aerosol Jet additive manufacturing technology for advanced printed electronics applications.


Semiconductor packaging houses gain from more device complexity

Wed, 1 Jan 2012

Increased I/O density, power/performance reqs, and other factors are increasing use of flip chip, 2.5D and 3D technologies, a boon to packaging subcontractors. But they face a challenge from foundries, and must navigate under-utilization of wire bonding capacity.


Upcoming SMTA events: IWLPC keynote named, SMTAI seeks presenters

Tue, 1 Jan 2012

The SMTA released its call for presenters for SMTA International (SMTAI) 2012, October 14-18 in Orlando, FL. The association, along with Chip Scale Review magazine, also announced the keynote for the International Wafer-level Packaging Conference (IWLPC), held November 5-8, San Jose, CA.


Teledyne Microelectronics to package Zephyr Photonics VCSELs

Tue, 1 Jan 2012

Teledyne Microelectronic Technologies will expand its optical packaging portfolio in a partnership with Zephyr Photonics, which makes a proprietary high-temp vertical-cavity surface-emitting laser (VCSEL).


Inari proposes acquisition of Amertron

Tue, 1 Jan 2012

Packaging house Inari Berhad signed an MOU to acquire Amertron Global, which operates in the Philippines and China providing microelectronics and optoelectronics manufacturing services.


JEDEC publishes wide-I/O mobile DRAM standard

Thu, 1 Jan 2012

JEDEC Solid State Technology Association released a new standard for wide I/O mobile DRAM: JESD229 Wide I/O Single Data Rate. Wide I/O mobile DRAM increases die integration -- stacking chips with TSV interconnects with a SoC -- and improves bandwidth, latency, power, weight, and form factor.


3D integration key to 22nm semiconductor devices

Mon, 1 Jan 2012

The benefits of 3D IC integration can be combined with aggressively scaled 22nm semiconductor devices, with More Moore (scaling) and More than Moore (package advances) developing in parallel but relatively independently, says Paul Lindner, EV Group (EVG).


ConFab interview: Amkor's Ron Huemoeller on 3D packaging readiness

Wed, 6 Jun 2012

Ron Huemoeller of Amkor presented in the Advanced Packaging session of Solid State Technology

@ The ConFab: Supply chain or supply web for 3D packaging?

Wed, 6 Jun 2012

With many advanced packaging processes taking place on the semiconductor wafer, the traditional supply chain of front-end fab at the foundry and back-end fab at the packaging and test house is falling apart. The ConFab session,

3D and 2.5D semiconductor packaging technologies @ The ConFab

Wed, 6 Jun 2012

As packaging has played a larger and larger role in chip performance, form factor, and capabilities, The ConFab has increased its focus on back-end processes. Cue

Xilinx relies on stacked silicon interconnect for 28Gbps FPGA

Thu, 5 May 2012

Xilinx Inc. (NASDAQ:XLNX) began shipping a 3D heterogeneous all-programmable FPGA, the Virtex-7 H580T FPGA, using its stacked silicon interconnect (SSI) technology to reach up to 16 28Gbps and 72 13.1Gbps transceiver bandwidth.


Ziptronix wafer stacking tech expands to 3D memory devices

Wed, 5 May 2012

Ziptronix Inc. is helping a 3D memory device maker replace standard die stacking with its DBI wafer-stacking technology, which has been proven in image sensor packaging.


IC package revenues outgrow unit shipments through 2016

Tue, 5 May 2012

Increased demand for product functionality is driving up IC packaging revenue faster -- a 9.8% compound annual growth rate (CAGR) -- than IC unit growth -- 7.3% CAGR 2010-2016, says New Venture Research (NVR).


Invensas debuts high-I/O PoP semiconductor packaging design

Tue, 5 May 2012

Invensas Corporation, Tessera subsidiary, debuted bond via array (BVA) technology, an ultra-high-I/O PoP semiconductor packaging alternative to wide-I/O TSV packaging.


Amkor plans semiconductor packaging and test facility in Korea

Sat, 5 May 2012

Amkor Technology Inc. (NASDAQ:AMKR) plans to build a state-of-the-art factory and global research and development center in the Incheon Free Economic Zone, which is located in the greater metropolitan area of Seoul, Korea.


"3.5D interposer technology could someday replace PCBs" -- TSMC's Doug Yu

Tue, 5 May 2012

TSMC

CEA Leti adds SPTS on 3D IC line with 300mm PVD order

Wed, 2 Feb 2011

SPP Process Technology Systems (SPTS) received a follow-on purchase order from CEA-Leti for its Sigma fxP PVD system. The 300mm system will be used for advanced TSV development at Leti's new 300mm fab extension in Grenoble.


Stacked silicon interconnect is better than 3D stacking Xilinx

Tue, 2 Feb 2011

ElectroIQ caught up with Suresh Ramalingam, director of advanced package design and development at Xilinx, at the January MEPTEC luncheon, where he gave a presentation on the company's stacked silicon interconnect technology. In an interview with Debra Vogler, Ramalingam discusses SSIT in relation to die stacking and TSV.


3D integration comes in many flavors for semiconductor industry, says CEA Leti chief scientist

Wed, 2 Feb 2011

All the major semiconductor players are embracing 3D integration, says Simon Deleonibus. The CEA-Leti scientist and IEEE Fellow wants to see TSV mature and new technologies develop based on wafer bonding. He speaks with Debra Vogler.


Silicon Si interposers aim of CEA Leti SHINKO common lab

Fri, 1 Jan 2011

CEA-Leti signed a multiyear agreement with SHINKO ELECTRIC INDUSTRIES CO. LTD. to develop advanced semiconductor packaging technology. They will focus on volume production of silicon interposers.


Gate structure and 3D stacking winners will determine semiconductor industry direction

Tue, 1 Jan 2011

Arthur W. Zafiropoulo, Ultratech, sees the 20/22nm node as a competition for gate-first and gate-last proponents to discover which will lead the semiconductor industry. Device makers that master TSV chip stacking will be the winners over the course of this decade, he says. This is an online exclusive essay in SST's Forecast for 2011: Back to Reality series.


Leti on more Moore for TSV

Mon, 1 Jan 2011

Engineered substrates and 3D integration technology based on direct bonding for future More Moore and More than Moore integrated devicesLaurent Clavelier, head of solar technologies department at Leti, discusses the significance of Leti's IEDM paper #2.6 "Engineered substrates and 3D integration technology based on direct bonding for future More Moore and More than Moore integrated devices" with Debra Vogler, senior technical editor.


Packaging, assembly changes coming in next ITRS Update

Wed, 1 Jan 2011

Dr. Phil Garrou looks ahead to a laundry list of changes coming in the next ITRS Update with respect to assembly and advanced packaging, including 3D integration, interposers, and applications from medical to automotive and embedded applications.

 


CEA Leti ramps 300mm 3D packaging integration line

Mon, 1 Jan 2011

CEA-Leti is expanding its technology offering, ramping up one of Europe’s first 300mm lines dedicated to 3D-integration applications. The new line is dedicated to R&D and prototyping and includes 3D-oriented lithography, deep etching, dielectric deposition, metallization, wet etching, and packaging tools.


Ziptronix accuses Omnivision, TSMC of patent infringement

Fri, 1 Jan 2011

Dr. Phil Garrou takes a closer look at an IP dispute lobbed by Ziptronix against Omnivision and TSMC over low-temperature oxide bonding, used in making backside-illumination CMOS image sensors.


Interposer focus at recent RTI 3D conference

Thu, 1 Jan 2011

Fresh off 3D announcements of IBM and Samsung, several industry leaders talked about the imminent use of 3D Interposers at the RTI 3-D Architectures for Semiconductor Integration and Packaging Conference in Burlingame CA, reports Dr. Phil Garrou.


IMAPS: 3D IC toolset readiness, Cu bonding, interposer failings

Tue, 3 Mar 2011

Dr. Phil Garrou reports on several talks and trends of note from the recent IMAPS meeting and Device Packaging Conference: the readiness of 3D IC toolsets, what's holding back Cu bonding; and rumors of interposers failing thermal tests.


TSV can deal with stress says Synopsys

Mon, 3 Mar 2011

Victor Moroz discusses the strong but doable effects of stress on TSVs. TSV stress ranges are comparable to the size of the TSV, and analog behaves differently than digital. Synopsys recently presented results (part of a collaboration with imec) at a SEMATECH event.


CEA Leti IPDiA partner 3D integration for passives on Si

Mon, 3 Mar 2011

CEA-Leti and IPDiA have formed a common lab to capitalize on their complementary expertise in miniaturization and 3D integration on silicon. The common lab will develop very high-end passive components that will resist harsh environments, functional sub-mounts for LEDs, and assembly technologies.


IBM to use water cooling for future 3D IC processors

Fri, 3 Mar 2011

At the recent CeBIT Fair in Hanover Germany, IBM announced that its 3D technology to appear in its Power8 processor by 2013 will incorporate microchannel cooling.


TeraView partners with HELIOS on THz semiconductor package failure analysis

Tue, 3 Mar 2011

TeraView and HELIOS are partnering to improve semiconductor package failure analysis using terahertz technology. The technology was originally developed with Intel and isolates faults in advanced 3D semiconductor packages.


SEMATECH reports die to wafer bonding progress for 3D integration

Wed, 3 Mar 2011

SEMATECH experts reported new breakthroughs in wafer bonding at the 7th Annual Device Packaging Conference (DPC), March 7-10 in Scottsdale, AZ. Low-temp die tacking has yielded faster die-to-wafer integration.


Hynix Semiconductor joins SEMATECH 3D Interconnect Program at UAlbany NanoCollege

Wed, 3 Mar 2011

Hynix Semiconductor Inc., DRAM and flash memory supplier, joined SEMATECH's 3D Interconnect program at CNSE's Albany NanoTech Complex to address industry infrastructure and technology gaps in materials, equipment, integration and product-related issues for high-volume adoption of through silicon vias (TSV).


Present at ESTC 2012 in Amsterdam

Tue, 2 Feb 2012

Electronics System Integration Technology Conference (ESTC) 2012 seeks original papers describing research in all areas of electronic packaging, including LED packaging, flexible electronics, assembly and interconnect technologies, and more.


Georgia Tech produces 130um 3D organic semiconductor package

Thu, 2 Feb 2012

Georgia Tech

X-FAB Silicon Foundries adopts SFT software

Fri, 2 Feb 2012

X-FAB Silicon Foundries, a More-than-Moore semiconductor foundry, has used SFT's R3D (Resistive 3D) software for its 0.18

CEA-Leti launches 3D semiconductor packaging platform

Tue, 1 Jan 2012

CEA-Leti launched a major new platform, Open 3D, that provides industrial and academic partners with a global offer of mature 3D packaging technologies for their advanced semiconductor products and research projects.


USPTO seeks nominees for National Medal of Technology and Innovation

Tue, 1 Jan 2012

The USPTO is looking to increase the diversity of honorees for its annual National Medal of Technology and Innovation (NMTI), honoring "this nation's creative geniuses."


Sony stacks CMOS image sensor pixel structures and chips

Mon, 1 Jan 2012

Sony has developed a backside-illuminated CMOS image sensor that layers the pixel section with back-illuminated structures over the chips containing signal processing circuits, instead of using supporting substrates.


Lifting the veil on silicon interposer pricing

Mon, 12 Dec 2012

Are we closer than we think to our needed mass production costs for silicon interposers? Phil Garrou gleans some insights from the year-ending RTI Architectures for Semiconductor Integration and Packaging conference.


Singapore IME launches 2.5D silicon interposer MPW

Wed, 12 Dec 2012

Singapore's Institute of Microelectronics (IME) has launched a new multiproject wafer service for 2.5D through-silicon interposers, to provide a cost-effective platform for R&D prototyping and proof-of-concept in the technology.


Tezzaron licenses Ziptronix's bonding tech for 3D memory

Mon, 12 Dec 2012

Tezzaron Semiconductor has licensed patents regarding Ziptronix's direct bonding technologies, "direct bond interconnect" (DBI) and "direct oxide bonding (ZiBond), for use in 3D memory.


Will the $2 interposer be silicon or glass?

Tue, 11 Nov 2012

Dr. Phil Garrou reports from the 2nd annual Georgia Tech 2.5D Interposer Conference: what's the market projection for silicon and glass interposers, what's preventing high-volume manufacturing, and is there a crossover with flat-panel display glass manufacturing?


Alchimer pursuing partners with new CEO, CTO

Tue, 11 Nov 2012

Alchimer SA says it is seeking partnerships with various semiconductor equipment and materials companies as it welcomes two top execs: Bruno Morel is the company's CEO since May of this year, and product development director Fr

Imec's via-middle TSV fab 'reveals' contacts by wafer thinning/etch

Tue, 3 Mar 2012

Imec developed a via-middle approach to through-silicon via (TSV) manufacturing for 3D packaging, using wafer thinning and a silicon etch process to reveal TSV contacts on the wafer.


Amkor (AMKR) names Taiwan leader with semiconductor packaging background

Fri, 3 Mar 2012

Amkor Technology Inc. (Nasdaq: AMKR) added Mike Liang as president of Amkor Technology Taiwan. Liang's background includes stints with Phoenix Semiconductor, Ti-Acer, UMC, and others.


Shin-Etsu Chemical joins EVG wafer bonding supply chain

Wed, 3 Mar 2012

EV Group (EVG) welcomed Shin-Etsu Chemical  into its open platform for temporary bonding/debonding materials supporting 3D semiconductor packaging.


Interposer supply/ecosystem examined at IMAPS Device Packaging

Mon, 3 Mar 2012

Dr. Phil Garrou, a contributing editor and regular blogger on Solid State Technology, shares the highlights of an Evolving 2.5D/3D Infrastructure panel he hosted at IMAPS Device Packaging. On the table: where TSVs and interposers are made, a TSV/interposer timeline and cost analysis, and the requirements of mobile electronics.


AMAT, Singapore's microelectronics institute open 3D semiconductor packaging R&D lab

Wed, 3 Mar 2012

Applied Materials Inc. (AMAT) opened the new Centre of Excellence in Advanced Packaging at Singapore

STATS ChipPAC brings FOWLP to stacked packages for <1mm profile

Tue, 3 Mar 2012

STATS ChipPAC Ltd. (SGX-ST:STATSChP) uncrated its next-generation eWLB package-on-package (PoP) technology, with a package profile height below 1.0mm.


AMAT, A*STAR Advanced Packaging Centre of Excellence plans grand opening

Thu, 3 Mar 2012

Applied Materials and Singapore's A*STAR Institute of Microelectronics will officially open the Centre of Excellence in Advanced Packaging, in Singapore

ICECool puts 3D thermal issues back in focus

Mon, 10 Oct 2012

With the approach of full commercial production of 3DIC products, Dr. Phil Garrou shifts his attention to thermal performance questions and proposed thermal solutions for the future.


SPTS Technologies, Fraunhofer IZM researching lower-temp films for TSVs

Thu, 10 Oct 2012

Fraunhofer IZM's All Silicon System Integration Dresden (ASSID) center will add SPTS' etch and PECVD process capabilities to investigate low-temperature dielectric films for through-silicon vias (TSV) in 3D IC packaging.


Why SATS consolidation needs to happen

Fri, 10 Oct 2012

The advent of leading-edge semiconductor packaging technologies dictates efficient use of capital, and only the top-tier semiconductor assembly and test services (SATS) companies will have the financial wherewithal to develop required expertise and capacity, says one analyst.


Nanium ships 200 millionth eWLB component

Wed, 10 Oct 2012

Nanium says it has shipped its 200 millionth embedded wafer-level ball grid array technology (eWLB) component, a 10% year-over-year productivity increase that reflects full conversion to the company's eWLB overmold technology that allows thinner and more robust packages.


SPTS unveils low-temp PECVD cluster tool for 3D ICs

Wed, 9 Sep 2012

SPTS' Delta fxP cluster system achieves low-temperature deposition of TEOS oxides and nitrides for via-reveal passivation in 3D IC packaging, solving two key problems of low temperatures and bonding adhesive outgassing.


EVG updates modular coater/developer with OmniSpray, NanoSpray coating options

Mon, 9 Sep 2012

EV Group's updated modular EVG150 high-volume coater/developer adds new modules for conformal coating of high topography surfaces, and coating surfaces with vertical sidewall angles, such as through-silicon vias (TSV).


Wet process technologies for scalable through silicon vias

Fri, 4 Apr 2011
Electrografting nanotechnology has been optimized for highly conformal growth of TSV films, enabling a large reduction in cost-of-ownership per wafer compared to the dry process approach. Claudio Truzzi, Alchimer S.A., Massy, France

Tessera focuses on semiconductor technologies beyond packaging

Thu, 4 Apr 2011

Tessera Technologies Inc. (Nasdaq:TSRA - News) began two corporate initiatives to expand its technologies in semiconductor microelectronics beyond packaging, and to potentially separate its Imaging & Optics business.


Present on interposer technology

Tue, 9 Sep 2011

The first annual Global Interposer Technology Workshop at Georgia Tech will convene students, academics, researchers, and industry to share information on silicon and glass interposers for semiconductor packaging.


Xilinx, Elpida highlight SEMICON Taiwan's SiP Global Summit

Mon, 9 Sep 2011

Dr. Phil Garrou takes a closer look at highlights from a SiP summit at the recent SEMICON Taiwan: Xilinx FPGAs and Elpida's low-power DDR3 memory.


Advanced semiconductor package test emphasized at new BiTS Workshop

Fri, 9 Sep 2011

The Burn-in & Test Socket Workshop (BiTS Workshop) is changing its name to The Burn-in & Test Strategies Workshop to reflect the "evolution of packaged ICs."


Multi-die face-down packaging suits existing wire bond lines

Thu, 9 Sep 2011

Invensas Corporation, a Tessera subsidiary, will demonstrate dual-face down implementation of its new multi-die face-down packaging technology at the Intel Developer's Forum. The multi-die package is wire bonded, mounting ICs upside down and staggering them in a shingle-like configuration.


3M, IBM to make 3D chip adhesives

Wed, 9 Sep 2011

Forget "3D stacking" -- the two companies say a special electronic "glue" applied to the wafer will help stack dozens of chips into a "silicon skyscraper" that will be much faster and more efficient than current chip technology.


Alchimer TSV barrier-layer film shows 100% deposition coverage

Tue, 9 Sep 2011

Alchimer's AquiVia film-deposition technology promises to cut fill deposition times and cost even with complex through-silicon via (TSV) 3D packaging structures. The product targets TSV ramp-up at production levels, according to the company.


SUSS MicroTec sends equipment to SVTC in MEMS, 3D IC dev partnership

Tue, 11 Nov 2011

Nanotechnology accelerator SVTC Technologies partnered with SUSS MicroTec on wafer-level packaging for MEMS, and 3D IC bonding technology development.


Backside-illuminated image sensors: Optimizing manufacturing for a sensitivity payoff

Fri, 11 Nov 2011

Backside-illuminated image sensors require more precise wafer processing -- uniform extreme wafer thinning, dopant control, epitaxy growth, trench manipulation, etc. -- but the payoff in image quality is significant. Researchers at imec experimented with different wafer fab technologies to make a record BSI sensor. They also consider new architectures/packaging techniques for this technology.


Thin-film chip boosts LED optical output without changing footprint

Thu, 11 Nov 2011

OSRAM Opto Semiconductors increased its IR Power Topled with lens optical output by 80% over the standard version by integrating a thin-film chip. The IR LED maintains the same surface area and drive current.


SEMATECH creates 3D packaging standards development forum

Mon, 11 Nov 2011

SEMATECH has created an online 3D Standards Dashboard, allowing 3D semiconductor and MEMS interconnect professionals to exchange standards activity information.


Thailand flood update from key semiconductor assembly and test companies

Fri, 11 Nov 2011
Numerous global semiconductor suppliers maintain assembly and test operations in Thailand. Many of these facilities have been affected by the disaster. IHS iSuppli pulled together a list of those affected, and those that have thus-far escaped damage.

SRC attacks 3DIC reliability, design tools with new effort

Thu, 5 May 2011

Semiconductor Research Corporation is leading an effort to address key roadblocks for wide-scale adoption of the emerging 3D ICs and systems. These new initiatives will address critical reliability and design tool issues and leverage partnership between researchers from universities and the semiconductor industry.


Electronics packaging leaders gathered under cherry blossoms at ICEP

Thu, 4 Apr 2011

ASE FOWLPT.Onishi, Grand Joint Tech and E.J. Vardaman, TechSearch International share the highlights on low-k dielectrics, 3D packaging, copper pillar, and other exciting work presented at the International Conference on Electronics Packaging (ICEP) in Japan.


Silicon interposer cost redux goal of GA Tech consortium

Wed, 4 Apr 2011

Georgia Tech PRC believes current silicon interposers are limited in performance by high electrical loss of silicon and high cost of wafer-based interposers. Georgia Tech PRC has undertaken silicon R&D with the potential to reduce the cost by 5-10x, in the Silicon and Glass Interposer Industry (SiGI) Consortium.


CEA Leti deploys EVG's litho, packaging tools for 300mm line

Tue, 4 Apr 2011

CEA-Leti has installed multiple EVG tools in its 300-mm cleanroom dedicated to R&D and prototyping for 3D integration applications. EVG's equipment will be used in 3D technology demonstrations for Leti's global customer base, as well as low-volume pilot production on 300mm wafers.


STATS ChipPAC expands TSV service with mid end flow

Tue, 4 Apr 2011

STATS ChipPAC Ltd. (SGX-ST: STATSChP), semiconductor test and advanced packaging service provider, is expanding its 300mm through silicon via (TSV) offering with the addition of mid-end manufacturing capabilities.


3D IC is only solution for scaling "up," says MonolithIC 3D exec

Thu, 3 Mar 2011

Transfer on top of processed wafer and replace gates (<400°C)Zvi Or-Bach, MonolithIC 3D, describes the TSV-beating monolithic IC fab process, and argues for scaling "up" rather than down. Or-Bach compares the costs of further semiconductor scaling to advanced packaging.


If wide I/O DRAM and other 3D technologies can go HVM standards are needed

Wed, 3 Mar 2011

Mechanical stresses can prevent successful implementation of 3D packaging technologies, says Larry Smith, SEMATECH. He argues for a DFM-like solution to identify and manage stress on thinned and stacked die in 3D ICs. To complicate matters, foundries, OSATs, and memory suppliers could inflict different stresses on the die, and the whole industry is too new at 3D packaging to present concrete answers.


3D CT X ray imaging fills inspection gaps says Xradia

Tue, 3 Mar 2011

Xradia microscope.Xradia has unveiled its latest micro computed tomography (CT) 3D X-ray imaging system, the VersaXRM. Kevin Fahey, PhD, VP of marketing at Xradia, discusses how the new platform uses geometrical magnification in tandem with an X-ray microscope.


TSV probe partnership Cascade Microtech imec collaborate for kgd

Thu, 3 Mar 2011

Cascade Microtech Inc. (NASDAQ: CSCD) and imec entered into a collaborative research partnership for testing and characterization of 3D integrated circuit (IC) test structures. Imec will work closely with Cascade Microtech to develop test methods and methodologies for emerging 3D through silicon via (TSV) structures, and to develop global standards.


NuPGA becomes MonolithIC 3D, expands IP in monolithic 3D semiconductor space

Thu, 3 Mar 2011

As it developed an improved FPGA technology, the NuPGA team discovered a path for practical monolithic 3D ICs. MonolithIC 3D changed its strategy to focus on monolithic 3D IC technology as a pure IP innovator organization.


Stacked semiconductor die inspection debuts from Sonix

Fri, 3 Mar 2011

Sonix SDI stacked die inspection imageSonix Inc., scanning acoustic microscope designer and manufacturer, introduced its Stacked Die Imaging (SDI) enhancement, which effectively inspects for defects in semiconductor stacked die and wafer level packages (WLP) by selectively increasing the ultrasonic signal gain for deeper interfaces of interest.


Honeywell taps Tezzaron Semiconductor to stack rad-hard die

Fri, 12 Dec 2011

Honeywell Microelectronics will use Tezzaron's 3D stacking on Honeywell

TSMC, Arteris develop silicon-interposer-based NOCs

Wed, 12 Dec 2011

Arteris Inc., network-on-chip (NoC) interconnect IP company, will incorporate its FlexNoC NoC interconnect IP into an SoC die on silicon interposer test chip with TSMC.


Silicon interposer partnership sets roadmap

Tue, 12 Dec 2011

Singapore's A*STAR IME and 3D IC developer Tezzaron Semiconductor signed a research collaboration agreement to develop and exploit advanced through silicon interposer (TSI) technology.


2.5D announcements at the Global Interposer Tech conference

Tue, 12 Dec 2011

At the recent Global Interposer Technology workshop at Georgia Tech, Xilinx and TSMC discussed 2.5D chip packaging technologies and others touted the potential of glass as an interposer substrate material, reports Dr. Phil Garrou.


IBM fabs Micron memory cube with TSV tech

Fri, 12 Dec 2011

Using the advanced through-silicon via (TSV) fabrication process at IBM (NYSE:IBM), Micron Technology Inc. (NASDAQ:MU) will begin producing its Hybrid Memory Cube. The companies claim that this is the first CMOS design to go commercial with TSV interconnects.


Leti on 3D CMOS and photonics interconnect

Mon, 11 Nov 2011

Leti

TSMC repeats call for foundry-centric 2.5/3D industry

Thu, 12 Dec 2011

The readiness of suppliers to offer 2.5D packaging technologies was in full debate at the RTI 3D ASIP event this month, with presentations and rumors questioning how soon customers will need 2.5D/3D, and whether some offerings are worth the investment.


GSA publishes 3D/2.5D packaging studies

Tue, 12 Dec 2011

The Global Semiconductor Alliance released "3D IC Architecture: A Natural Evolution," a report sponsored by Macronix International and Etron Technology. GSA also published the 2nd edition of the 3D IC Design Tools and Services Tour Guide.


Advanced package technologies' growth through 2015

Tue, 12 Dec 2011

Small, mobile, Internet-connected devices are bucking the slow economy and use advanced packaging technologies to pack an enormous amount of functionality into a very small form factor, notes New Venture Research, which provides forecasts for each advanced packaging device type.


Powertech seeks 30-51% of Greatek

Mon, 12 Dec 2011

Powertech Technology Inc. (PTI) has approved a tender offer of NT$25.28 per share for the common shares of Greatek with a minimum acquisition target of 30% of outstanding shares.


ITRI brings 3D packaging expertise to Rambus partnership

Thu, 12 Dec 2011

Licensing company Rambus Inc. (Nasdaq:RMBS) is engaging with the Industrial Technology Research Institute (ITRI) in Taiwan on the development of interconnect and 3D packaging technologies.


Silicon interposers: building blocks for 3D-ICs

Wed, 6 Jun 2011
Silicon interposers seem set to stay as a valid alternative implementation to full 3D-IC designs. Matthew Hogan, Mentor Graphics, Wilsonville, OR

3D IC prototyping process result of MENT, Tezzaron, MOSIS collaboration

Thu, 6 Jun 2011

Mentor Graphics Corporation (NASDAQ:MENT), in a cooperative effort with Tezzaron Semiconductor and MOSIS, created a process for economically developing and manufacturing 3D-IC prototypes on multi-project wafers (MPWs).


IMEC, Cadence automate 3D IC design test

Mon, 6 Jun 2011

Imec and Cadence say they have developed a design-for-test and automatic test pattern generation technology to more easily test 3D stacked ICs with through-silicon via (TSV) functionality, adding only "negligible" area costs.


Elpida, PTI, UMC finalize 3D IC partnership

Wed, 6 Jun 2011

Updating on plans announced a year ago, Elpida, Powertech, and UMC say they have finalized their partnership to develop a "one-chip" logic+DRAM 3D IC solution incorporating 28nm interface design, through-silicon via (TSV) formation, wafer thinning, testing, and chip stacking assembly.


FEI plasma FIB tool targets packaging apps

Mon, 6 Jun 2011

High-speed sectioning of TSVs with plasma FIB. The device was located, cross-sectioned, polished, and imaged with PFIB. SOURCE: FEI FEI's new Vion plasma focused ion beam (PFIB) system based on inductively-coupled plasma (ICP) source technology using a xenon ion beam generates more than a micro-amp of beam current and can remove material faster than liquid metal ion sources, says product marketing manager Peter Carleson.


More Moore & More than Moore require fabless, foundry, and packaging houses on board

Tue, 5 May 2011

Complex supply chain. SOURCE: Yu, The ConFabToday at The ConFab, John Chen (Nvidia), Jeong-ki Min (Samsung Electronics), and Abraham Yee (Nvidia) gathered foundry, OSAT, and chip maker leaders to discuss what happens beyond Moore's Law. The following are key points from "Collaboration to Strengthen the IC Supply Chain."


Asian foundry inspects micro bumps with Camtek systems

Thu, 5 May 2011

Camtek Ltd. (NASDAQ and TASE: CAMT) received repeat automatic optical inspection (AOI) orders from an Asia-based foundry doing advanced micro bump inspection and metrology. Challenges arise in measuring such small bumps used in advanced packages, including efficiently handling huge amounts of data.


STATS ChipPAC widens fan-out WLP configurations with TSVs, IPDs

Tue, 5 May 2011

STATS ChipPAC says integrating through-silicon vias with passive devices and its eWLB technology addresses complex design issues, shrinking lithography nodes, and increased performance demands for mobile and consumer applications.


3D stacked IC design flow gets boost from imec, Atrenta partnership

Wed, 5 May 2011

imec's 3D integration industrial affiliation program (IIAP) partnered with Atrenta Inc., SoC realization products provider to semiconductor and electronic systems industries, to developed an advanced planning and partitioning design flow for heterogeneous 3D stacked ICs.


Will PoP delay TSV adoption? TechSearch International analyzes the 3D technologies

Thu, 5 May 2011

PoP provides a cost/performance solution that solves business and logistics issues associated with stacking devices directly. 3D TSV, with its associated uncertainties, cannot yet meet PoP's benefits, says TechSearch International (TSI).


Alchimer wet deposition debut targets RDL, other 3D IC processes

Wed, 5 May 2011

Alchimer's wet-deposition process, AquiVantage, grows interconnect layers for interposer redistribution layers (RDLs) and significantly enhances via-last backside wafer interconnects. The process eliminates 2 costly photolithography steps.


AMKR senior notes offering draws $400M

Mon, 5 May 2011

Amkor Technology (NASDAQ:AMKR) completed its offering of $400 million aggregate principal amount of its 6.625% Senior Notes due 2021. The proceeds from the offering will be used to fund the company's tender offer for the approximately $264.3 million aggregate principal amount of its outstanding 9.25% Senior Notes due 2016, for general corporate purposes.


3D integration: Bringing it home with supply-chain buy-in

Thu, 5 May 2011

A recurring theme at this year's Confab is that 3D integration shows tremendous promise, particularly with many fabless companies, yet many barriers remain -- and the first and biggest is preparing the supply chain.


Non-planar device scaling: SEMATECH talks TSV, SoC, SiP

Thu, 5 May 2011

The semiconductor industry is moving to 3D device structures, says Raj Jammy, SEMATECH, at The ConFab 2011, discussing TSV and system-in-package (SiP) opportunities and challenges. He also summarizes logic and memory roadmaps.


3D packaging disrupts the IC supply chain -- ConFab session dedicated to the OSAT/foundry/fabless relationship

Fri, 5 May 2011

The ConFab gathers semiconductor industry leaders to discuss the biggest trends in the chip manufacturing sector. One of these major trends is 3D packaging, and Session 2 on Monday (May 16) will combine packaging house, fabless, and foundry approaches to the new supply chain, with speakers from Amkor, GLOBALFOUNDRIES, STATS ChipPAC, and Qualcomm.


Tessera receives initial Amkor payment in court award

Tue, 8 Aug 2012

Tessera received an initial payment of approximately $20 million from semiconductor packaging company Amkor, related to the interim award issued by the International Court of Arbitration of the International Chamber of Commerce (ICC).


Hybrid Memory Cube interface specification draft includes protocol, short-reach PHY interconnection

Wed, 8 Aug 2012

The Hybrid Memory Cube Consortium released the initial draft of the Hybrid Memory Cube (HMC) interface specification, with the final version planned for end of 2012.


Flooding in the Philippines threatens microelectronics facilities

Thu, 8 Aug 2012

Heavy monsoons moving through the Philippines are causing floods in and around Manila, the capital. The Philippines is a small but growing area for microelectronics manufacturing and packaging facilities.


Nanya implements 3D IC TSV technology for DDR3, future DDR4 devices

Fri, 7 Jul 2012

Dr. Phil Garrou, contributing editor, shares Nanya Technology

3D TSV Summit planned for European semiconductor industry

Wed, 7 Jul 2012

SEMI Europe will host a new event, the European 3D TSV Summit, January 22-23, 2013 in Grenoble, France. This inaugural meeting will revolve around the theme: "On the Road towards TSV Manufacturing," denoting how device designers and manufacturers are crossing from 2D packaging to 3D for more functionality in a smaller form factor.


STATS ChipPAC adds director with experience from Intel to Zarlink

Wed, 7 Jul 2012

STATS ChipPAC appointed Gary Tanner as a member to its Board of Directors. Tanner brings experience from Zarlink Semiconductor, Intel, Texas Instruments, and other semiconductor companies.


New MEMS, 3D IC packaging working group chairs at GSA

Tue, 7 Jul 2012

Global Semiconductor Alliance (GSA) recently named Jay Esfandyari, STMicroelectronics, as its MEMS Working Group chairman and Ken Potts, Cadence Design Systems, as the 3D IC Working Group chairman.


3D TSV packages outgrow semiconductor industry by 10X

Thu, 7 Jul 2012

3D TSV chips will represent 9% of the total semiconductors value in 2017, according to Yole D

Ziptronix wafer bonding technology adopted for high-volume cellphone component

Tue, 7 Jul 2012

Ziptronix Inc., which develops direct bonding technology for advanced semiconductor applications, has licensed its technology for a high-volume cellular handset application.


2012 ITRS update: Back-end packaging and MEMS

Fri, 7 Jul 2012

At SEMICON West, the working groups of the International Technology Roadmap for Semiconductors (ITRS) outlined 2012 updates to the roadmap. Check out the back-end process info here.


Video: Readiness of 3D technologies from a materials perspective

Fri, 7 Jul 2010

Mark Privett, Brewer Science, says that new technologies allow use of higher temperatures as well as room-temperature processes, such as wafer de-bonding. The 3D industry is nearly ready for high-volume, yet still without industry standards.


Insights from SEMICON: Video interview with blogger Phil Garrou

Wed, 7 Jul 2010

In this video interview, Philip Garrou, microelectronics consultant and Advanced Packaging blogger, offers information on his blog, Insights from the leading edge, and summarizes reasonable roadmaps for 3D technology and TSV in particular. 2012 mainstream adoption seems too aggressive to Garrou.


EDA in a 3D semiconductor world: Walden Rhines

Tue, 7 Jul 2010

In this video interview from SEMICON West 2010, Walden Rhines, Mentor Graphics, discusses 3D technologies. EDA tools need to be extended to meet the needs of 3D -- parasitic extraction and timing, place-and-route, and other steps are different with 3D. The tools are evolving for the various 3D technologies. He also touches on lithography evolution.


Workshop addresses simulating, measuring 3D IC stress using TSVs

Tue, 7 Jul 2010

SEMATECH and Fraunhofer IZFP hosted a follow-up meeting in conjunction with SEMICON West (Tuesday, July 13) to evaluate a design-for-manufacturing (DFM) approach to managing stress in 3D interconnects, and to drive consensus and support for these techniques across the industry.


TSV infrastructure and standardization questions with Matt Nowak

Tue, 7 Jul 2010

In this video, Matt Nowak, Qualcomm, talks about his keynote at ASMC on through silicon technologies for stacking die in advanced packaging applications.


Take the survey on PoP assembly

Fri, 7 Jul 2010

Package on package (PoP) stacking makes use of the vertical space available on electronics printed circuit boards (PCBs). It increases density, fitting more silicon into the same footprint. However, package stacking can be difficult, as fine pitches require placement accuracy, and taller stacks generally face reliability issues, especially if the stack is reflowed improperly. So where should PoP stacking take place?


SEMICON West Lesson #3: 3D and packaging are hot

Mon, 7 Jul 2010

Wrap-up of what we heard and saw at SEMICON West 2010. Lesson 3: Everything about 3D & packaging was hot, with suppliers jostling to get into this next high-growth market. But are they really prepared for what awaits them?


Lasertec joins SEMATECH 3D packaging research, installs 300mm TSV IR etch metrology tool

Thu, 7 Jul 2010

Lasertec joined SEMATECH’s 3D Interconnect program to develop robust, cost-effective process metrology technology solutions for readying high-volume via-mid through silicon via (TSV) manufacturing. This article includes a video interview with SEMATECH about the partnership.


SEMI forms 3D stacked IC standards group, seeks volunteers

Tue, 12 Dec 2010

SEMI International is forming a standards committee to evaluate and create specifications and practices for 3D stacked ICs (3DS-IC), with initial efforts targeting three areas: bonded wafers, inspection/metrology, and thin wafer handling.


Cu protrusion, keep-out zones highlight 3D talks at IEDM

Wed, 12 Dec 2010

Dr. Phil Garrou looks at 3D IC technology discussions at IEDM 2010, including details of TSMC's integration of 3D into its advanced CMOS foundry processes, and a close examination of 3D-induced stresses.


IMT-adds-TSV-geometry-point

Wed, 12 Dec 2010

Innovative Micro Technology Inc. (IMT) added a new geometry point in its technology roadmap for through silicon vias (TSVs). Joining the copper-filled 15 by 60um depth TSV configuration that has been in production for nearly 2 years, 50 by 250um copper-filled TSV is planned for production at the beginning of 2011.


AT&S-launches-SiP-substrate-technology

Sat, 12 Dec 2010

AT&S debuted a new technology to enable system-in-package (SiP) devices. AT&S’s embedded component packaging technology ECP is used to enable further miniaturiztion of electronic devices while enhancing their performance.


Why 3D-IC conversion resembles the bipolar-CMOS shift

Wed, 12 Dec 2010

3D IC technology will require significant changes across the design, tool, and manufacturing spectrum -- that sounds a lot like how the industry transitioned from bipolar to CMOS, writes Dr. Phil Garrou, reporting from themes at an IEEE 3D event in Munich.


SEMATECH, SIA, SRC pursuing 3D standards

Tue, 12 Dec 2010

SEMATECH, the SIA, and SRC have established a new 3D Enablement program targeting standards in inspection, metrology, microbumping, bonding, and thin wafer and die handling.


Logic apps for Si interposers and embedded capacitors: ALLVIA talk at 3D Packaging Forum

Mon, 12 Dec 2010

Dr. Nagesh Vodrahalli, vice president of technology and manufacturing at ALLVIA, will present a discussion on December 9 titled "Silicon Interposers with TSVs and Embedded Capacitors for Advanced Logic Applications."


Leveraging 3D packaging technologies: Tessera shares its latest work

Fri, 7 Jul 2010

In this video interview, Craig Mitchell, Tessera, comments on 3D packaging and interconnect. The chip industry is using packaging technologies to address miniaturization and density. Materials are posing a challenge.


Embedded wafer-level packages: Fan-out WLP/chip embedding in substrate 2010 report

Tue, 7 Jul 2010

This report from Research and Markets covers new and established technologies for embedded package integration. Benefits of embedded package integration include miniaturization, improvement of electrical and thermal performance, cost reduction and simplification of logistic for OEMs.  


Advanced packaging technologies: Imbedding components for increased reliability

Tue, 4 Apr 2010

Imbedded component/die technology is a method of imbedding active and passives into cavities within a multi-layer PCB to decrease the surface area required to implement the circuit design and increase the robustness of the overall assembly. Casey H. Cooper, STI, discusses the design methodology, packaging processes, and test data gathered during imbedded die/component packaging implementation in a mixed-signal prototype. The prototype was subjected to reliability testing and demonstrated in a test flight.


KGD Packaging and Test Workshop keynote, panel on TSV, and more

Wed, 9 Sep 2010

KGD (Known Good Die) Packaging and Test Workshop 2010 will focus on semiconductor die products test, assembly, manufacturing, and business issues in the microelectronics industry. Bill Bottoms will keynote, covering deep submicron and 3D integration.


3D Integration: The Challenges Ahead

Sun, 8 Aug 2010
The potential benefits of 3D integration -- where chips are thinned, stacked and electrically connected with through-silicon vias (TSVs)

3D ICs in the spotlight at IMAPS

Thu, 11 Nov 2010

Talks at the recent IMAPS annual meeting in Raleigh, NC put 3D ICs and through-silicon vias under the spotlight, reports Dr. Phil Garrou -- lowering costs, fixing test problems, developing standards, and who will eventually pay for it all (hello memory!).


SMTA announces IWLPC featured tutorials

Thu, 8 Aug 2010

Tutorials at the October event will cover 3D packaging, future interconnects, WLP, flip chip, and more.


PoP rework: Process control and using the right materials increases yield

Mon, 9 Sep 2010

POP after package rework.PoP packages present some unique rework challenges, such as how to rework an underfilled package; also, these packages are prone to warpage. Inspecting the area array devices can be a challenge. Bob Wettermann, BEST Inc., discusses rework solutions.


Focus on 3D TEST at IEEE Workshop

Wed, 12 Dec 2010

The test community is embracing 3D ICs, as evidenced by presentations at the first IEEE International Workshop on Testing 3D stacked ICs that addressed a range of test challenges and solutions, reports Dr. Phil Garrou.


TSMC-work-on-Si-interposers-TSV-die-stacking

Fri, 11 Nov 2010

TSMC packaging interviewDi Ma spoke with Debra Vogler, senior technical editor, ElectroIQ, about TSMC's work with silicon interposers, die stacking with through-silicon vias (TSV), and gate-last transistor fab.


Deep-submicron-changes-advanced-packaging-Bill-Bottoms

Wed, 11 Nov 2010

In his keynote address at the MEPTEC Semiconductor Packaging Roadmaps conference, Bill Bottoms, chairman of Third Millennium Test Solutions (3MTS), gave attendees a dose of reality as he summarized the predicament facing the industry as it pursues 3D ICs. "Everything becomes more difficult at deep sub-micron," said Bottoms.


FDSOI-to-TSV-IEDM-preview-CEA-Leti research

Tue, 11 Nov 2010

CEA-Leti will present 10 papers, including two invited papers, at the IEDM/IEEE 2010 International Electron Devices Meeting December 6-8, in San Francisco, CA. The papers will cover More than Moore, FDSOI, memory (phase-change and charge-trapping), silicon nanowires, TSVs, high-k dielectrics, and more.


Amkor-3-generations-of-3D-packaging

Mon, 11 Nov 2010

In this podcast interview, Smith discusses the three generations in the transition to 3D packaging and how the OSATs shape the development roadmap. Smith says that we need complete supply chain collaboration: EDA tool suppliers, equipment/materials suppliers, logic, memory, fabless, IDMs, and the SATs, to develop and deploy the technologies.


Flip chip PoP is perfect for mobile, if done right

Wed, 11 Nov 2010

Craig Mitchell, TesseraPackage-on-package, implemented with flip chip package assembly, is meeting requirements for next-gen mobile devices. Challenges remain: fine pitch underfill, brittleness of ultra low-k (ULK) dielectrics, and shorting between adjacent bumps. Craig Mitchell, Tessera, examines the lucrative 3D packaging step and how to face these challenges.


Package-on-package-POP-survey-Stack-packages-at-SATS

Mon, 11 Nov 2010

Advanced Packaging asked our readers where -- at the foundry, in a dedicated semiconductor assembly and test services (SATS) house, or on the SMT line -- package-on-package (POP) assembly should take place.


Rudolph-Asia-OSAT-collab-on-2D-defect-inspection-3D-solder-bump-TSV-depth-metrology-for-stacked-die

Tue, 11 Nov 2010

Rudolph’s NSX Series Macro Defect Inspection Systems Rudolph Technologies Inc. (RTEC) is partnering with a major outsourced semiconductor assembly and test (OSAT) services manufacturer to provide its inspection and metrology capability in the development of stacked packaging processes. The process uses silicon interposer technology, sometimes referred to as 2.5D IC, as an intermediate step toward full blown 3D ICs.


Alchimer-Electrografting-for-3D-TSV-apps-validated-by-RTI

Tue, 11 Nov 2010

Alchimer's Electrografting (eG) technology has been validated by scientists at RTI International (RTI). The paper confirmed that electrografting is a proven technology for depositing "insulator, barrier and seedlayer into high aspect ratio TSVs for 3D integration applications."


Allvia completes tests for stacked-semi Si interposer

Fri, 1 Jan 2010

Allvia says it has completed integration and full reliability testing of a silicon interposer between a semiconductor die and an organic or ceramic substrate.


SMTA webcasts on package on package (PoP), STACK assembly, rework, and inspection

Fri, 1 Jan 2010

The Surface Mount Technology Association (SMTA) will host two 90-minute online sessions with Bob Willis, ASKbobwillis.com, on package-on-package (PoP) applications and implementation. The Webtorials will take place February 4 and February 11, 2010 from 1:00 to 2:30 pm EST.


Henkel develops wafer backside coating for die attach

Mon, 8 Aug 2010

Henkel has extended its Wafer Backside Coating (WBC) portfolio to also include a solution for stacked-die packages. Ablestik WBC-8901UV has been designed to address the demanding requirements of multiple die stack applications for the memory market segment.


Convergence of 3D integrated packaging and 3D TSV ICs

Sun, 8 Aug 2010
As the need to integrate MEMS devices and advanced memory for sensor applications expands, work is underway to develop modules merging both mechanical and electrical devices into single, highly compact modules. Navjot Chhabra, Freescale Semiconductor, Austin, Texas, USA

Process equipment readiness for through-silicon via technologies

Sun, 8 Aug 2010
Unit processes, integration schemes, and equipment are in place to enable development and pilot production of TSV technologies and all parts of the value chain do exist today at 300mm to enable integration technology qualification, end-product samples, and limited pilot production. Sesh Ramaswami, Applied Materials, Santa Clara, CA USA

TSV: Current challenges and solutions with Novellus

Fri, 8 Aug 2010

In this video interview, Sesha Varadarajan, Novellus, says that capacitance issues must be overcome, and the PVD step must provide good enough coverage to properly apply copper. CTE mismatch can also cause issues.


Si, glass interposers for 3D packaging: analysts' takes

Tue, 8 Aug 2010

Silicon interposers for advanced packaging Yole reportYole asks if next-generation package substrates are myth, niche, or high-volume necessity? Several companies are investigating silicon interposers and there is great interest in the topic, but there is no clear consensus on apps and timing for adoption, says TSI in its forecast for Si interposers. Both analyst forecasts are summarized.


Look for TSV to take off in 2012: Jan Vardaman

Tue, 8 Aug 2010

In this video interview from SEMICON West 2010, Jan Vardaman, president/founder of TechSearch International, discusses 3D technologies in the real engineering world. Especially for 300mm, work is being done on processes and yield. She points to 2012 for widespread adoption of TSV.


Achieving cost and performance goals using 3D semiconductor packaging

Sun, 8 Aug 2010
It has been proven that SoC and 3D multiple die packaging can significantly improve performance and the function-to-area ratio, however, one must look at the tradeoffs. Vern Solberg, STC-Madison, Madison, WI USA

Fraunhofer's Ramm will open International Wafer-Level Packaging Conference

Tue, 8 Aug 2010

Peter Ramm, Fraunhofer EMFT, will be the Opening Speaker at the 7th Annual International Wafer-Level Packaging Conference (IWLPC). Ramm will present "The European 3D Technology Platform for Heterogeneous Systems" at the Kick-Off Reception.


Roadmapping More than Moore: When the application matters

Fri, 7 Jul 2012

At the ITRS 2012 update, back-end technologies session, at SEMICON West, roadmapping for More than Moore was addressed as both a philosophical and technical matter.


EVG's wafer bonder passes SEMATECH/ISMI 3D integration tool assessment

Wed, 7 Jul 2012

SEMATECH qualified EVG's GEMINI automated wafer bonding system through its Equipment Maturity Assessment implemented within SEMATECH's 3D Interconnect program and ISMI's EMA team.


STATS ChipPAC ramps advanced flip chips to HVM, adds TCB processing capability

Tue, 7 Jul 2012

STATS ChipPAC brought its fcCuBE advanced flip chip semiconductor packaging technology with copper column bumps, bond-on-lead interconnection, and enhanced assembly processes into high-volume manufacturing for multiple customers.


Xilinx boosts silicon and electronics engineering in Ireland

Thu, 7 Jul 2012

Xilinx will invest $50 million to expand its electronics engineering operations, located at the company

Tessera: Adding Vista Point Technologies, losing Powertech Technology?

Mon, 7 Jul 2012

Tessera received notice from Powertech Technology Inc. (PTI) that it will terminate its license agreement with the semiconductor packaging and optics technology company. Tessera also completed phase 1 of its acquisition of camera module technologies from Flextronics.


Unisem focuses new business model on Tier-1 customers and high-value technologies

Fri, 6 Jun 2012

UNISEM relaunched its business model with the name

Ultratech acquires IBM patents for semiconductor packaging processes

Fri, 6 Jun 2012

Ultratech acquired IBM patents on semiconductor packaging technologies, including C4 bumping, ball grid array (BGA) methods, lead-free solders, and 3D packaging.


3D and 2.5D Integration: A Status Report preview with TechSearch International

Tue, 6 Jun 2012

Solid State Technology is hosting 3D and 2.5D Integration: A Status Report, sponsored by EVG and ALLVIA, and is free for all attendees. This preview shares a sneak peek at

Xilinx speaker joins 3D packaging webcast roster

Tue, 6 Jun 2012

Solid State Technology is hosting a free webcast, 3D and 2.5D Integration: A Status Report. A fourth presenter has just been announced, Brent Przybus, Senior Director, Product Line Marketing, Xilinx Inc.


Dow Corning teams with SUSS on TSV bonding process

Mon, 6 Jun 2012

Dow Corning will collaborate with SUSS MicroTec on a temporary bonding process (materials and equipment) for through-silicon vias (TSV) in high-volume advanced semiconductor packaging.


New speaker added for 3D and 2.5D Integration webcast

Mon, 6 Jun 2012

Solid State Technology will present 3D and 2.5D Integration: A Status Report on June 27, free for all attendees. William Chen, ASE, will join speakers David McCann, GLOBALFOUNDRIES and E. Jan Vardaman, TechSearch International.


DARPA seeks microfluidic thermal management for 3D ICs

Mon, 6 Jun 2012

DARPA

ECTC

Fri, 6 Jun 2012

Attendance was high at this year's Electronic Component Technology Conference (ECTC) in San Diego. Sandra Winkler is senior industry analyst at New Venture Research and IEEE/CPMT Luncheon Program Chair, shares the key trends in ECTC's sessions, like WLP, 2.5D, LED packaging, and more.


USI process produces copper-filled vias on ceramic substrates

Tue, 6 Jun 2012

UltraSource Inc. announced CopperVia, a process that fills vias with pure copper to yield low-cost, high-conductivity, reliable electrical and thermal interconnects in ceramic thin film circuit substrates.


ESCATEC offers package-on-package stacking for low-volume designs

Tue, 6 Jun 2012

ESCATEC added package-on-package (PoP) capability at its Heerbrugg, Switzerland, facility, adding a dipping unit for ball grid array (BGA) packages on its Siplace assembly line.


ams offers foundry customers KGD with enhanced IC test

Mon, 6 Jun 2012

The Full Service Foundry business unit of ams extended its dedicated test solutions for foundry customers, offering known good die (KGD), with customers' complex analog/mixed-signal ICs 100% electrically tested according to their own test specification.


Advantest tackles 3D package test with new product line

Fri, 6 Jun 2012

Advantest is developing a line of fully automated and integrated test and handling solutions for TSV-based 2.5D and 3D packages. The concept model test cell, DIMENSION, integrates a high parallel test cluster along with singulated die and 3D die stack automated handling capabilities.


UMC developing TSV tech for BSI CMOS image sensors with A*STAR

Fri, 6 Jun 2012

Singapore

Conference report: IITC closes with talks from EUV to TSV

Thu, 6 Jun 2012

Day 3 of the 15th IITC (International Interconnect Technology Conference) opened in San Jose, CA under clear sunny skies and a pleasant breeze. The herd thinned a bit, down to ~150 hearty souls from the original 230 the prior two days.


Via-last 3D packaging and interposer metallization costs chat

Thu, 7 Jul 2011

Steve Lerner, CEO of Alchimer, discusses the company's latest suite of through silicon via (TSV) technologies, focusing on how the platform reduces costs for advanced packaging processes.


SEMICON West workshop addresses stress management for 3D ICs using TSVs

Tue, 7 Jul 2011

Speakers at a SEMATECH/Fraunhofer-hosted workshop at SEMICON West looked at stress management for 3D ICS using TSVs: the state of reliability testing, failure analysis techniques, and why an engineering paradigm shift is needed.


SEMATECH survey on 2.5D, 3D IC; gaps in the via-mid ecosystem

Thu, 7 Jul 2011

Sitaram Arkalgud, director of interconnect at SEMATECH, discusses the high-volume manufacturability issues and gaps in both 2.5D and 3D semiconductor technologies with respect to backside processing and wafer bonding, thinning, and handling. Standards are also covered.


MHI 8" wafer bonder produces 3D LSI ICs at room temp with FAB gun

Wed, 7 Jul 2011
Mitsubishi Heavy Industries Ltd. (MHI) developed a fully automated 8" wafer bonding machine that bonds large-scale integration (LSI) circuits at room temperature, creating 3D ICs.

EV Group joins Ga. Tech's 3D packaging center

Wed, 7 Jul 2011

EV Group will contribute its know-how and technology in temporary bonding and debonding, chip-to-wafer bonding, and lithography technology to the Georgia Tech's PRC's Silicon and Glass Interposer Industry (SiGI) Consortium research program.


Elpida begins sampling 8Gb DDR3 SDRAM

Tue, 7 Jul 2011

Elpida Memory is now sampling a new 8Gb TSV DRAM consisting of four 2Gb layers based on TSV stacking technology.


Advanced packaging programs at SEMICON West emphasize holistic approach

Fri, 6 Jun 2011

SEMICON West preview: This year's SEMICON West Advanced Packaging Program is taking a broad approach, encouraging participation from across the supply chain to help keep pace with a rapidly expanding electronics market -- and in markets beyond, from automotive to aerospace and medical.


NCCAVS on 3D packaging: Bring on the TSVs

Mon, 6 Jun 2011

A standing-room crowd gathered at SEMI for a special NCCAVS usergroup meeting to hear about issues relevant to 3D packaging, including CMP for through-silicon vias (TSV), a DFM methodology for 3D TSV packaging designs, and TSV process integration challenges.


Forging a TSV supply chain in a consolidated market

Fri, 10 Oct 2010
Steve Lerner, Alchimer S.A., Massy, France

Xilinx stacked silicon interconnect creates multi-die FPGA for high density, bandwidth

Wed, 10 Oct 2010

Xilinx multi-die FPGA packageXilinx (XLNX) debuted a stacked silicon interconnect technology for breakthrough capacity, bandwidth and power savings using multiple FPGA die in a single package. The stacked silicon package suits applications that require high-transistor and logic density, as well as intense computational and bandwidth performance. This article includes a podcast interview with the company about the technology.


austriamicrosystems extends beyond standard foundry offering into advanced packaging

Thu, 10 Oct 2010

austriamicrosystems Full Service Foundry introduced "More Than Silicon," a comprehensive service and technology package that goes beyond standard foundry services. Foundry customers receive access to leading-edge technology add-ons, advanced packaging services, and dedicated support engineers to enable first-time-right designs.


Nanoplas targets 200mm MEMS and 3D TSV packaging with dry processing tool

Tue, 10 Oct 2010

Nanoplas toolNanoplas introduced a fully automatic dry-processing batch system for high-volume 200mm production. The DSB 9000A is based on Nanoplas’s High Density Radical Flux (HDRF) technology.


PVD System for 3D Packaging

Mon, 6 Jun 2009
The Applied Materials' Charger UBM PVD system was designed for under-bump metallization (UBM), redistribution layer and CMOS image sensor applications. Its linear architecture is said to more than double the wafer output of other systems. In addition, its proprietary Isani wafer treatment technology allows the UBM system to process ten times more wafers between servicing.

ECTC 2009 In Review

Mon, 6 Jun 2009
In a time when R&D is at the forefront of the industry, events like ECTC 2009 become critical for showcasing research achievements, as well as providing venues for learning about the latest developments across the spectrum of device manufacturing. With 16 professional courses, 39 sessions of 6 papers each, two poster sessions, and the opportunity to mix it up with prestigious members of academia and research institutes, calling the event informative would be an understatement.

Thin Film Measurement Tool

Fri, 5 May 2009
The MetaPULSE thin film measurement tool from Rudolph Technologies is optimized specifically for copper via fill in 3D IC applications, as well as copper damascene processes at 45nm through 22nm technology nodes and copper via fill in 3D IC applications. Copper thickness and overburden measurements are critical in optimizing the CMP process that follows deposition during through-silicon via (TSV) manufacturing.

Yole Report: Memory Packaging & Integration Trends

Fri, 5 May 2009
(May 8, 2009) LYON, France — The memory semiconductor industry is about to go through major technological changes as new integration trends and disruptive packaging technologies pave the way to the future growth, reports Yole. The study presents the end applications driving the use of 3D integrated memories and their key players. It also includes an overview of the memory packaging market, its forecasted evolutions with new applications and growth in flash and DRAM.

Professor Rao Tummala to Present Keynote at 2009 International Wafer-Level Packaging Conference (IWLPC)

Fri, 5 May 2009
(May 29, 2009) MINNEAPOLIS, MN — Professor Rao Tummala, Advanced Packaging Editorial Advisory Board Member, will keynote the 6th Annual International Wafer-Level Packaging Conference (IWLPC), October 27–30, 2009 at the Santa Clara Marriott Hotel in Santa Clara, CA.

Simplicity Leads to 3D Packaging Success

Tue, 4 Apr 2009
By Francoise von Trapp, contributing editor
3D embedded technologies just got closer to volume manufacturing. We've been hearing variations on the embedding theme for quite some time, but as of yet, none have made it to high volume manufacturing. However, one embedded solution, Imbera's integrated module board (IMB) technolog appears to be on its way, after the company's announcement of successful Series B funding, which the company expects will take it into high-volume production.

3D IC Technology: Interconnect for the 21st Century

Mon, 4 Apr 2009
By Paul Enquist and Chris Sanders, Ziptronix, Inc.
In 3D IC technology, thinned, planar circuits are stacked and interconnected using through silicon vias (TSVs). 3D ICs have the potential to alleviate scaling limitations, increase performance by reducing signal delays, and reduce cost. Enabling technologies for 3D IC include TSV formation, thinning, and alignment and bonding. Realizing the full potential of this technology requires a scaleable approach to 3D IC fabrication.

The Riley Report

Tue, 4 Apr 2009
Non-traditional Applications of Jet Dispensing
by George A. Riley, Contributing Editor
While jetting is common in semiconductor packaging, it is finding new applications in emerging fields. At the recent SMTA Pan Pacific Symposium, Alec Barbiarz of Asymtek described jetting opportunities in medical analytics, high-intensity lighting, active-matrix displays, green energy, and 3D assemblies.

Behind Brewer Science's wafer bonding work

Mon, 8 Aug 2009
(August 10, 2009) SAN FRANCISCO, CA -- Karen Twillmann, executive director of corporate marketing at Brewer Science, and Dan Wallace, the company's director of 3D packaging, discusses the advances made by the company's temporary bond adhesive for wafer bond applications.

Conference on 3D Architectures for Semiconductor Integration and Packaging

Tue, 6 Jun 2009
(June 2, 2009) RESEARCH TRIANGLE PARK, NC — The 2009 3D Architectures for Semiconductor Integration and Packaging Conference and Exhibition will bring together industry leaders to examine the practical and competitive landscape on the path to implementation of 3D integration and packaging technologies, December 9 through 11, 2009, in Burlingame, CA.

Applied's new InVia lays it on thick for 3D IC packaging

Mon, 3 Mar 2010

Kedar Sapre from Applied Materials talks with SST about the company's new Producer InVia CVD system targeting via-first/via-middle through silicon vias (TSV) for 3D IC packaging.


Novellus develops copper seed PVD process for TSV packaging

Tue, 3 Mar 2010

Novellus Systems (NASDAQ: NVLS) created an advanced copper barrier-seed physical vapor deposition (PVD) process for the emerging through-silicon-via (TSV) packaging market. The process uses Novellus’ established INOVA platform with patented hollow cathode magnetron (HCM) technology to produce highly conformal copper seed films that are reportedly four times thinner than the conventional PVD seed approaches used for TSV applications. Novellus announced that the HCM TSV process delivers excellent sidewall and bottom coverage, and enables void-free copper fill during the subsequent TSV electroplating step.


Allvia touts embedded capacitors with Si interposers, 3D stacks

Wed, 3 Mar 2010

Allvia says it has integrated embedded capacitors on silicon interposers, a key interface between silicon devices and organic substrates, achieving >1500nF/cm2 capacitance.


Lithography and wafer bonding solutions for 3D integration

Mon, 3 Mar 2010

Given the advantages and technical feasibility of through-silicon vias (TSV), the major focus now is on the manufacturability and integration of all the different building blocks for TSVs and 3D interconnects. EV Group's Thorsten Matthias et al. review advances in lithography, thin wafer processing, and wafer bonding, and the integration of all these process steps.


Alchimer, KPM Tech Sign Agreement for TSV Wet Processing Tools & Materials

Mon, 2 Feb 2010

In a deal that will generate economical new process options for the 3D integration market, Alchimer S.A., a provider of nanometric deposition technology for semiconductor interconnects and through-silicon vias (TSV), and KPM Tech Co. Ltd., a manufacturer of plating materials and systems, announced a multi-level collaboration that gives KPM Tech exclusive rights to produce chemicals in Korea for Alchimer’s technology. The agreement also includes the manufacture of various configurations of wet processing tools to support the Alchimer TSV platform.


3D Jargon

Mon, 2 Feb 2009
By Yann Guillou, ST-Ericsson Wireless and Eric Saugier, STMicroelectronics
3D Integration, through silicon via (TSV), 3D packaging, 3D TSV, 3D system-in-package (SiP), 3D system-on-chip (SoC), and 3D system-on-package (SoP) are some of the hottest topics presented at conferences or read about in popular tech magazines. All of these are definitively trendy terms; no one would argue to the contrary. So it's about time to take a serious look at 3D in its broadest meaning.

Tackling the TSV Checklist

Tue, 2 Feb 2009
by Fran

Via-first or Via-last ...a Matter of Perspective

Thu, 2 Feb 2009
By Chris Sanders, Ziptronix Inc.
The momentum building around 3D IC integration technology over the past few years makes it clear that this technology is going to happen — it's just a matter of when. There are three main components to 3D IC technology: through silicon via (TSV) formation; thinning; and bonding. The numerous process flows that exist for 3D integration are all related to the sequence in which these three processes occur.

Design Platform for 3D Stacked ICs

Tue, 2 Feb 2009
The j360 Silicon PathFinder 3D Platform from Javelin Design Automations supports 3D stacked IC design using through silicon vias (TSV). The design tool reportedly extends the Javelin PathFinding methodology and j360 Silicon PathFinder platform to support virtual chip design for co-optimization of system design and 3D interconnect-packaging technologies

Burn-in Test Socket Challenges

Thu, 2 Feb 2009
By Gail Flower, Editor-at-Large This article provides a broad review of the issues affecting socket usage: lead-free challenges, finer pitch adjustments, cost control, standardization, practical customer concerns, and improvements needed for 3D packages and other innovations on the horizon. Through conversations with industry experts, we explore a few common themes from this year's Burn-in and Test Socket Workshop (March 8 -11, 2009) in Mesa, AZ.

Allvia shows off its Si interposer data

Tue, 12 Dec 2009

Nagesh Vodrahalli, VP of technology & manufacturing at Allvia, discussed some of the issues in developing through-silicon via (TSV) technologies with Solid State Technology/Advanced Packaging in conjunction with his presentation at the recent 3-D Architectures for Semiconductor Integration and Packaging conference.


Micron sampling new NAND+DRAM multichip package

Wed, 11 Nov 2009

Micron Technology says it is now sampling a multichip package combing its 34nm-based 4Gb SLC NAND flash and 50nm-based 2Gb low-power DDR DRAM memories, a combination it says offers better cost and power savings for mobile devices.


Report: "Astonishing" evolution in 3D ICs, TSVs

Sat, 11 Nov 2009

Updates to a pair of reports from Yole Developpement aim to help better identify remaining integration challenges and high-volume production implementation strategies for 3D ICs and through-silicon vias (TSV).


Alchimer: Higher-AR TSV saves $700/wafer

Wed, 11 Nov 2009

A new study suggests that through-silicon vias (TSV) with higher aspect ratios (20:1 or 10:1, vs. 5:1) offer a significant payback by saving space on a die, up to $700 per wafer.


Allvia buys old ETEC site for manufacturing ramp

Thu, 10 Oct 2009

Specialty TSV foundry Allvia is expanding its manufacturing capabilities away from high-cost Silicon Valley to a newly-purchased facility in Oregon, a site with its own chip-equipment pedigree.


IMEC: 3D challenges, integrating DRAM on logic

Tue, 10 Oct 2009

Bart Swinnen, IMEC's director of interconnect and process technology unit, discusses with SST/AP the research center's 3D program, from its annual press event in Leuven, Belgium.


Avoiding ASIC expense and risk with SiCB technology

Mon, 10 Oct 2009

Embedded computing modules employing "silicon circuit board" technology as an alternative to expensive ASIC developments offer advantages in performance and power for integrating memory and logic -- and are a practical alternative to 3D integration due to thermal and supply chain issues, explains siXis' David Blaker.


Elpida stacks 8 DRAMs with TSV

Wed, 9 Sep 2009

Elpida Memory recently pushed vertical stacking of DRAM to new heights by connecting eight 1G chips using through-silicon vias, creating what it calls the world's largest-capacity DRAM with ~8GB of storage.


IMEC sets major step towards 3D integration of DRAM on logic

Wed, 9 Sep 2009

IMEC and its 3D integration partners have taped-out Etna, a new 3D chip integrating a commercial DRAM chip on top of a logic IC. The new 3D stack resembles as close as possible to future commercial chips. It consists of a 25µm thick logic die on top of which a commercial DRAM is stacked using through-silicon vias (TSVs) and micro-bumps.


IMAPS GBC and Device Packaging Conference in Review

Tue, 3 Mar 2009
by Fran

Vertical-die-stacking-goes-3D-without-TSV

Thu, 10 Oct 2010

vertical die stack technologyAndrew Smith, Ventmark Technology Solutions, presents a 3D die stacking technology to address package miniaturization. Using bare die and vertical interconnect structures, this stacking technology permits the design of ultra-thin, near-CSP solutions without TSVs. Designers lacking custom ICs should look to new chip stacking technology.


3D architectures for semiconductor integration and packaging: Conference preview

Thu, 10 Oct 2010

The International Conference "3-D ARCHITECTURES FOR SEMICONDUCTOR INTEGRATION AND PACKAGING" will take place December 8-10, 2010 at the Hyatt Regency San Francisco Airport Hotel. Check out the planned keynotes and topics of the conference.


New 300mm TSV production processes aim of SPTS, CEA-Leti partnership

Wed, 10 Oct 2010

CEA-Leti and SPTS will develop advanced 300mm through-silicon via (TSV) 3D IC processes. The agreement defines their collaboration on a range of 3D TSV processes to optimize etch and deposition technologies used to create next-generation high aspect ratio TSVs.


3D roadmaps begin to converge

Mon, 10 Oct 2010

Last month's SEMICON Taiwan 3D Technology Forum shed some insight into what several foundries, assembly houses and customers are thinking about the timing for 3D interposers and full 3D IC, reports Phil Garrou.


Bart Swinnen, IMEC, Discusses TSVs

Fri, 8 Aug 2009

In this video interview from SEMICON West 2009, Bart Swinnen, reviews the established interconnect bonding and through-silicon via (TSV) technologies at the system-integration level. He also discusses the newer TSV possibilities and different application-specific TSVs.


PoP Device Reliability with Various Underfill Methods

Fri, 8 Aug 2009

Vicky Wang, Henkel Loctite (China) Co. Ltd. and Dan Maslyk, Henkel Corp. show how underfill type and strategy will be key to enabling highly reliable PoP devices. Few studies have evaluated the effects of the underfilling strategy — such as underfilling the bottom component only or underfilling both top and bottom components — or the effects of solder alloy choice on the reliability of PoPs. This article presents findings from a recent study on the drop test reliability of PoP devices as a function of underfill dispensing type and PoP ball alloy type.


BrightSpots 3D IC Forum: Summary of Discussions

Wed, 8 Aug 2009
The BrightSpots 3D IC Forum came to a close on Friday, July 24. Out of 3 topic areas covering technology progress, supply chain issues, and standards development, the discussions around technology progress were clearly the most active, both from a panelist and attendee perspective. What follows is a summary of each discussion. Where topics overlapped, and discussions were brief, the summaries have been combined into one.

Elpida, UMC, PTI partner for 3D IC packaging

Tue, 6 Jun 2010

Elpida Memory and Taiwanese chip firms Powertech Technology Inc. (PTI) and United Microelectronics Corp. (UMC) are banding together to push 3D IC integration for advanced semiconductor processes.


A Novel ACA for 3D Chip Stacking and Lead-free PCB Packaging

Fri, 6 Jun 2010

In a SiP chip stack, space constraints can lead to large parasitic inductances in the packaging. Planarity, processing, high-temperature exposure, and other factors also present challenges. A new anisotropic conductive adhesive technology could enable low-cost flexible packaging via a multi-layer particle structure. S. Manian Ramkumar, Ph.D., RIT, reviews the adhesives benefits to various levels of electronics interconnect.


Getting costs out, standards in for high-volume TSS

Thu, 5 May 2010

High-density through-silicon stacking (TSS) shows promise for very high-volume applications, but work still needs to be done to "tame" key issues in manufacturing, improve costs, and smooth out the supply-chain, said Matt Nowak, director of engineering in Qualcomm's VLSI technology group, in a presentation at The ConFab in Las Vegas.


imec, PVA Tepla demo 3D TSV void detection

Thu, 1 Jan 2013

Imec and PVA Tepla say they have achieved void detection in through-silicon vias at wafer level, after TSV copper plating, thanks to a nondestructive high-frequency scanning acoustic microscopy (SAM) technique.


Novati to use Ziptronix bonding tech for 3D assembly

Fri, 1 Jan 2013

Novati Technologies Inc. has licensed Ziptronix's direct bonding technologies, "direct bond interconnect" (DBI) and "direct oxide bonding (ZiBond), to offer 3D stacking services and test to customers.


Interposer consortium ready to expand at Georgia Tech PRC

Thu, 4 Apr 2012

After pioneering low-cost wafer- and panel-based glass and silicon interposers in Phase 1 of its SiGI consortium, Georgia Tech Packaging Research Center is beginning Phase 2 in June.


GLOBALFOUNDRIES installs TSV fab tools for 20nm stacked die

Thu, 4 Apr 2012

At its Fab 8, GLOBALFOUNDRIES is installing a special set of production tools to create TSV in 20nm wafers. 3D die stacking of leading-edge chips will enable mobile and consumer electronics.


STATS ChipPAC adds Pasquale Pistorio, STMicroelectronics leader, to Board

Mon, 4 Apr 2012

Semiconductor packaging service provider STATS ChipPAC Ltd. (SGX-ST:STATSChP) appointed Pasquale Pistorio as a member of the Board of Directors, effective immediately.


Georgia Tech targets thin 3D packaging with new consortium

Wed, 4 Apr 2012

Georgia Tech's Packaging Research Center proposes a new consortium on 3D semiconductor packaging called 3D ThinPack for ultra-miniaturized 3D heterogeneous, RF, digital and power modules in partnership with global companies.


Endicott Interconnect names David Van Rossum new CFO

Tue, 4 Apr 2012

Endicott Interconnect Technologies has appointed David W. Van Rossum to the position of Chief Financial Officer, effective immediately.


ALD enables 3D capacitors for CEA-Leti and IPDiA

Tue, 4 Apr 2012

CEA-Leti and passive component maker IPDiA developed an atomic layer deposition (ALD) process to apply medium-k dielectric layers on a metal-insulator-metal capacitor architecture, enabling 3D capacitors.


MOSAID multi-chip package stacks 16 NAND Flash die on 1 channel

Thu, 4 Apr 2012

MOSAID Technologies Inc. is sampling a 16-die stack NAND Flash device operating on a single high-performance channel, the 5126Gb HLNAND.


Georgia Tech increases interposer development work

Wed, 4 Apr 2012

Georgia Tech's Packaging Research Center is adding ultra-fine-pitch interconnect, thermal reliability, and more to its work on silicon and glass interposers for 2.5D semiconductor packaging.


Amkor licenses 3D packaging tech to SHINKO

Fri, 3 Mar 2012

Amkor Technology Inc. granted SHINKO ELECTRIC INDUSTRIES CO., LTD. (Tokyo:6967) a non-exclusive license to its proprietary Through Mold Via (TMV) semiconductor packaging technology.


Synopsys launches 3D packaging EDA line-up

Mon, 3 Mar 2012

Synopsys is combining several products into a 3D-IC initiative for semiconductor designers moving to stacked-die silicon systems in 3D packaging. The 3D-IC initiative will bring in leading IC design and manufacturing companies to work with Synopsys on a comprehensive EDA solution.


2011 ITRS: DRAM, 3D Flash, MEMS, nano scaling steal the show

Wed, 2 Feb 2012

The 2011 International Technology Roadmap for Semiconductors (ITRS) has been publicly released. Several areas of advancement are highlighted in the 2011 ITRS: DRAM and Flash memory, and MEMS.


Samsung, IBM and GlobalFoundries look to the future: A report from the Common Platform Technology Forum

Thu, 3 Mar 2012

Execs from Samsung, IBM, GlobalFoundries and ARM looked to the future at The Common Technology Platform Forum in Santa Clara. They focused on the innovation pipeline for 20nm and 14nm technology nodes, and the role that EUV, FinFETs, TSVs, CNTs and DSA will play.


Conference report: MRS Spring 2012, Day 2

Wed, 4 Apr 2012

Blogger Mike Fury reports from the MRS Spring 2012 meeting in San Francisco. Highlights from the second day: OLED TFT displays, single transistor DRAMs, silicon photonic wires, CNTs, 3D optical interconnects, graphene for RF and sensing, transparent ZnO, epidermal electronic systems, stretchable electronics, ultra-low-k dielectrics, patterning of electroceramics, PRAM (an alternative to NRAM), and inkjet printing of superconducting films.


European microelectronics fab database tracks major changes over past 5 years

Mon, 2 Feb 2012

Yole Developpement released "European Microelectronic Fabs Database & Report 2012," a database and report on the European microelectronics and microsystem manufacturing fabs, pilot lines, and major R&D organizations.


Apple shares list of suppliers

Fri, 1 Jan 2012

For the first time, Apple Inc. has publicly published a list of over 150 companies that the electronics giant says represent 97% of its procurement expenditures for materials, manufacturing, and assembly of products worldwide.


Will 22nm need a mid-node?

Mon, 1 Jan 2012

Art Zafiropoulo of Ultratech shares predictions for 22nm: that everyone will be using gate-last fabrication, that there may be a mid-node at 20nm, and that TSVs and 450mm wafers will play an important role at the new node.


22nm node semiconductors: Technical forecasts

Tue, 1 Jan 2012

Solid State Technology asked top analysts and technologists to provide insights on the transition to 22nm semiconductor devices. Read through the whole 10-forecast series, or check out the individual articles as you have time to see perspectives on lithography, device architecture, and more.


SEMATECH highlights from VLSI-TSA

Thu, 4 Apr 2012

SEMATECH experts reported on innovative processes for advanced CMOS logic and memory device technologies and 3D TSV manufacturing at the International VLSI Technology, System and Applications Symposium (VLSI-TSA).


ASMC will focus on productivity and technology challenges

Wed, 4 Apr 2012

The 23rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2012) will be held May 15-17 in Saratoga Springs, New York. The conference will feature presentations of more than 85 peer-reviewed manuscripts covering critical process technologies and fab productivity. This year’s event features a panel discussion on “Competing for R&D Dollars,” moderated by Solid State Technology Editor-in-Chief Pete Singer.


Conference Report: MRS Spring 2012, Day 3

Thu, 4 Apr 2012

Blogger Mike Fury reports from the MRS Spring 2012 meeting in San Francisco. Highlights from the third day: leakage and TDDB in low- κ dielectrics, flexible energy storage and conversion, Mn capping layers and diffusion barriers, hard masks for Cu interconnects, nanogenerators, Cu in RF, flexible temperature sensors, NEMS and MEMS in HDD, ZnO nanostructures, and various aspects of CMP.


Economy, fabless relationships, 450mm and more on deck at The ConFab 2012

Thu, 4 Apr 2012

The ConFab 2012, an invitation-only global conference and business meeting on semiconductor manufacturing, June 3-6 in Las Vegas, selected speakers and sessions for 2012.


Semiconductor industry expectations for 2012: Take the WWK survey

Fri, 2 Feb 2012

Wright Williams & Kelly, Inc. (WWK) opened its 2012 semiconductor industry survey on equipment and process timing. Only participants will receive the full results, free of charge.


David McCann of GLOBALFOUNDRIES to speak at The ConFab 2012

Thu, 5 May 2012

Solid State Technology is proud to announce that David McCann will speak at The ConFab 2012. David, the Senior Director for Packaging R&D at GLOBALFOUNDRIES in Malta, New York, will speak on the evolution toward silicon-based interconnect and packaging, which is having profound impact on how we think about technology development and the supply chain.


SEMICON China: Challenges and opportunities for semiconductors, emerging techs

Thu, 2 Feb 2012

SEMICON China takes place March 20-22 in Shanghai. Check out the special pavillions and events, and keynote speakers scheduled.


ISSCC round-up: 2.5D packaging for IVRs, smallest NAND flash chip, more

Wed, 2 Feb 2012

International Solid-State Circuits Conference (ISSCC) is going on now, gathering semiconductor design and device architecture presentations from research firms like imec to chip companies like IBM. Here are some highlighted presentations.


MEMS Symposium Report: Chasing 1 Trillion

Thu, 5 May 2012

The 10th Annual MEMS Technology Symposium sponsored by MEPTEC (MicroElectronics Packaging and Test Engineering Council) was held May 23 at the San Jose Holiday Inn. This year’s theme was “Sensors: A Foundation for Accelerated MEMS Market Growth to $1 Trillion.”


SEMICON Europa 2012 seeks presenters

Fri, 3 Mar 2012

SEMI is seeking papers for technical sessions and presentations at the upcoming SEMICON Europa 2012, October 9-11 in Dresden, Germany. Technical presentation abstracts are due April 30.


Apple A5X processor teardown: Bigger die, higher heat?

Thu, 3 Mar 2012

Apple’s ARM-based processors have created a point of hardware differentiation in applications processors. With the A5X, Apple is going with a much larger die at the 45nm node (shared across the 2 prior generations), shares Chipworks. It's also turned off the PoP track.


Taiwan allows higher Chinese investments in LCDs, semiconductors, fab equipment, more

Wed, 3 Mar 2012

Taiwan raised investment ceilings for Chinese investors in LCDs, semiconductors, IC assembly and test, microelectronics production equipment, and metal tool manufacturing.


Fraunhofer delivers 300mm wafer processing to North America with Axus Technology

Wed, 3 Mar 2012

Fraunhofer IZM and Fraunhofer CNT will use CMP supplier Axus Technology exclusively to provide advanced 300mm wafer process development and foundry services to North American customers.


SEMI adds session, extends abstract deadline for China chip conference

Tue, 10 Oct 2012

SEMI has extended the deadline to submit proposed papers to next spring's China Semiconductor Technology International Conference 2013, and added a new symposium on circuit design, system integration, and application.


GSA forms technology steering committee to guide working groups

Tue, 10 Oct 2012

The Global Semiconductor Alliance (GSA) says it has formed a Technology Steering Committee to help address key business and technology areas of interest to its members, and "encourage the advancement and adoption of leading technology and practices."


IEDM: Nanoelectronics provide a path beyond CMOS

Tue, 12 Dec 2012

At the International Electron Devices Meeting in San Francisco, An Chen of GLOBALFOUNDRIES presented a survey of emerging nanoelectronic devices, which he divided into two categories: Charge-based and non-charge based.


ICPT 2012: Five themes summarizing CMP work and progress

Mon, 11 Nov 2012

This year's International Conference on Planarization/CMP Technology (ICPT) encompassed five themes describing use of CMP: new device structures, equipment and methods, Cu interconnects, consumables, and new CMP methods and processes.


Advanced non-etching adhesion promoters eliminate interposer layer

Wed, 11 Nov 2012

New NEAPs are independent of the adhesion performance of various types of dielectric materials, and the new NEAP process adds surface area to the conductors.


EV Group completes cleanroom expansion, opens new R&D labs

Wed, 11 Nov 2012

EV Group has completed its expanded cleanroom IV facility at its corporate headquarters in Austria, which doubled its cleanroom space for process development and pilot production services.


STATS ChipPAC to expand in South Korea

Mon, 11 Nov 2012

STATS ChipPAC Ltd. plans to expand its semiconductor assembly and test operation in South Korea.


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IEDM 2012 slideshow: Sneak preview of 14 conference papers

Tue, 12 Dec 2012

We've scanned the entire conference program for next week's 58th annual IEEE International Electron Devices Meeting (IEDM), to present a quick sampling of some of the more intriguing papers.


Rudolph enters back-end lithography market

Thu, 12 Dec 2012

Rudolph Technologies, Inc. (Nasdaq: RTEC) has entered the back-end advanced packaging lithography market, with the acquisition of Azores Corp., and the introduction of a new 2X reduction stepper called the JetStep.


The ConFab 2012: A retrospective

Thu, 8 Aug 2012

The ConFab, Solid State Technology’s invitation-only event for the semiconductor industry, took place in June, with presenters from top companies and analyst firms. If you couldn’t be there, check out all the coverage from the event -- reports, presentations, video interviews and more.


Fabless keynote: Xilinx on programmability @ SEMICON West

Thu, 7 Jul 2012

SEMICON West’s Day 2 keynote speaker represented a fabless company: Ivo Bolsens, PhD, SVP and CTO of Xilinx presented on how programmable chips and innovative packaging can advance semiconductors.


Interviews with CEA-Leti researchers at SEMICON West

Thu, 7 Jul 2012

CEA-Leti presented research updates alongside SEMICON West this week. After the talks on device architecture, 3D and 2.5 packaging interconnects, large-scale computing and power consumption, and more, CEA-Leti’s researchers joined Solid State Technology to talk about their fields of interest.


ECTC: Focus on 3D integration and TSVs

Fri, 6 Jun 2012

A main focus of this year’s Electronic Components and Technology Conference (ECTC), held this week in San Diego, is 3D integration and through silicon vias (TSVs).


Conference Report: International Interconnect Technology Conference, IITC

Tue, 6 Jun 2012

The 15th IITC (International Interconnect Technology Conference) opened Monday, June 4 at the Doubletree Hotel in San Jose, CA. Recurring themes this year were variations on 3D and TSV, novel systems and packaging, and back end memory. Mike Fury reports.


A virtual IDM concept can unite semiconductor foundries, fabless companies, and packaging houses

Mon, 6 Jun 2012

The ConFab 2012, Solid State Technology’s invitation-only meeting of the semiconductor industry, opened today in Las Vegas with a keynote address from John Chen, PhD, VP of technology and foundry operations at Nvidia Corporation.


Chat with Intel’s Shekhar Borkar @ SEMICON West 2012: Overpowering power consumption

Wed, 7 Jul 2012

In this video interview, Intel's Shekhar Borkar shares some key topics from SEMICON West keynote: Near-threshold voltage transistor designs, 3D integration for DRAM, unconventional interconnect, and more.


Semicon West Day 1: FDSOI and TSV R&D with CEA-Leti

Wed, 7 Jul 2012

Michael A. Fury, Ph.D., reports on the opening day of SEMICON West (July 10), covering exaflop computing, FDSOI, TSV and other integration schemes, and silicon photonics with CEA-Leti.


Imec at SEMICON West: Interview with Luc Van den hove

Tue, 7 Jul 2012

Luc Van den hove, president and CEO, imec, spoke with Solid State Technology, covering imec’s major announcements and research presentations to take place during SEMICON West 2012.


Top conference reports from H1 2012

Fri, 7 Jul 2012

We at Solid State Technology have compiled the best conference reports so far this year, in the lead up to SEMICON West 2012, next week in San Francisco.


June 27th webcast on 3D integration

Wed, 6 Jun 2012

In a webcast scheduled for June 27th at 1:00 Eastern, 11:00 Pacific, David McCann of GLOBALFOUNDRIES will provide a status report on advanced packaging and 3D integration. McCann is responsible for Packaging R&D and back-end strategy and implementation at GLOBALFOUNDRIES.


A*STAR and Hitachi to collaborate on 3D ICs

Fri, 9 Sep 2012

Singapore’s A*STAR’s Institute of Microelectronics (IME), and Hitachi Chemical Co., will be collaborating on a joint research program to develop high performance material technologies for thin wafer processing for 3D IC packaging.


NIST tips "hybrid" metrology method to test chips

Thu, 9 Sep 2012

The National Institute of Standards and Technology (NIST) says it's combined scanning techniques and statistical data to both more precisely and less expensively measure features on a chip -- and two big chip firms are already on board.


Samsung breaks ground for memory manufacturing in China

Wed, 9 Sep 2012

Samsung Electronics Co., Ltd., held a groundbreaking ceremony for a major new memory fabrication line in Xi'an, China. Once completed, the new facility will make use of advanced 10-19nm technology to produce NAND flash memory chips, according to the company.


UMC, ST to develop 65nm backside CMOS image sensors

Mon, 9 Sep 2012

Singapore IME, MOSIS to offer silicon photonics wafer prototyping service

Tue, 9 Sep 2012

Singapore's Institute of Microelectronics (IME) and MOSIS have signed a memorandum of understanding (MOU) to offer a multiple-project wafer service targeting silicon integrated photonics.


Laser nanofabrication for mass production at the nanoscale

Fri, 8 Aug 2012

Laser nanofabrication can now meet the needs of submicron and nanoscale feature size manufacturing, and can operate in air, vacuum, or liquid processes. Sister publication Industrial Laser Solutions recently published Laser nanofabrication: A route toward next-generation mass production.


Supply chain readiness in an era of accelerated change

Fri, 8 Aug 2012

In this SEMI News and Views blog, Karen Savala covers EUV lithography, 450mm wafers, and 3D IC developments, based on her recent presentation at SEMICON West, “Supply Chain Readiness in an Era of Accelerated Change.”


Europe to unite research efforts in Silicon Europe cluster alliance

Mon, 10 Oct 2012

Four of the leading micro- and nanoelectronics regions in Europe are joining forces to form a cluster alliance called “Silicon Europe.”


Present on semiconductor metrology and more at ASMC 2013

Wed, 8 Aug 2012

ASMC 2013, the leading international technical conference for exploring solutions to improve collective microelectronics manufacturing expertise, has issued a call for papers.


STATS ChipPAC expands TSV work into mid-end-of-line

Wed, 8 Aug 2012

STATS ChipPAC says it has expanded its through-silicon via (TSV) capabilities with a 300mm mid-end manufacturing operation targeting mid-end-of-line semiconductor manufacturing, including microbump technology down to 40μm, temporary bond/de-bonding, backside via reveal, isolation, and metallization.


Bonding and cleaving at low temperatures

Tue, 8 Aug 2012

Brian Cronquist, MonolithIC 3D Inc.'s VP of Technology and IP reports on recent progress on low temperature (less than 400°C) bonding and cleaving processes.


Technology licensing company Rambus restructures, creates CTO role

Thu, 8 Aug 2012

Rambus Inc. (NASDAQ:RMBS), a technology licensing company, will undergo a restructuring and related cost saving measures to cut its expenses by$30-35 million annually.


Tezzaron takes over SVTC's Austin fab amid layoff reports

Mon, 10 Oct 2012

Tezzaron Semiconductor is taking over SVTC Technologies' wafer fab in Austin, TX, amid reports that the semiconductor/MEMS development organization is cutting back activities in Austin and in California.


On-board heaters can self-heal flash memories

Thu, 9 Sep 2012

At the upcoming International Electron Device Meeting, Macronix researchers will describe how they built flash memories that could heal themselves by means of tiny onboard heaters that provide thermal annealing just at the spots where it is needed.


IEDM unveils 2012 program highlights

Mon, 9 Sep 2012

The 58th annual IEDM will take place December 10-12, 2012 at the San Francisco Hilton Union Square, preceded by a full day of Short Courses on Sunday, Dec. 9 and by a program of 90-minute afternoon tutorial sessions on Saturday, Dec. 8.


Horizontal channels key to ultra-small 3D NAND

Thu, 9 Sep 2012

The first working 3D NAND flash memory at sub-40nm feature sizes will be described by Macronix researchers at this year’s International Electron Devices Meeting (IEDM).


RRAM synapses mimic the brain

Thu, 9 Sep 2012

At this year’s IEDM, a team led by Korea’s Gwangju Institute of Science and Technology will detail a high-speed pattern-recognition system comprising CMOS “neurons” and an array of resistive-RAM (RRAM)-based “synapses,” which demonstrated STDP, a brain-like function.


TSMC keynoter suggests WLSI at IITC

Fri, 6 Jun 2013

In a keynote at the IEEE International Interconnect Technology Conference (IITC), Douglas Yu from TSMC talked about Moore’s Law scaling becoming increasingly difficult.


EVG and Dynaloy develop single-wafer cleaning solution

Mon, 6 Jun 2013

Single-wafer cleaning solution is suitable for 3D-IC/TSV, advanced packaging, MEMS and compound semiconductor applications.


"Generation Mobile": Advanced Packaging Technology at SEMICON West

Thu, 6 Jun 2013

Advanced packaging technology is undergoing dramatic changes as the smart phones and new sensor technologies demand continued improvements in form and function.


GLOBALFOUNDRIES introduces certified design flows for multi-die integration using 2.5D IC technology

Fri, 5 May 2013

The foundry plans to unveil a comprehensive set of certified design flows to support 2.5D IC product development with its most advanced manufacturing processes at next week’s 50th Design Automation Conference (DAC) in Austin, Texas.


Fab equipment spending: 23% growth for 2014

Tue, 6 Jun 2013

Fab equipment spending will grow two percent year-over-year  (US$ 32.5 billion) for 2013 and about 23 to 27 percent in 2014 ($41 billion) according to the May edition of the SEMI World Fab Forecast.


Leti to present latest R&D results in MEMS at Transducers’ 2013 in Barcelona

Wed, 5 May 2013

CEA-Leti will host a workshop for industrial companies to present its latest advances in MEMS and an overview of the success of its recent MEMS startup, Wavelens, during Transducers’ 2013 and Eurosensors XXVII in Barcelona, Spain.


Dow Corning and SÜSS MicroTec report new temporary bonding solution for 2.5D and 3D IC packaging

Wed, 5 May 2013

The semiconductor industry’s march toward broader 3D IC integration marked an important milestone this week at ECTC 2013, with the report of an advanced new temporary bonding solution for 3D TSV semiconductor packaging.


Mentor and Tezzaron optimize Calibre 3DSTACK for 2.5/3D-ICs

Mon, 5 May 2013

Mentor Graphics Corp. and Tezzaron Semiconductor Corp. today announced they are collaborating to integrate the Mentor Calibre 3DSTACK product into Tezzaron’s 3D-IC offerings.


Yole Developpement conducts 2.5D, 3DIC and TSV interconnect patent investigation

Wed, 5 May 2013

Yole Développement announced its 2.5D, 3DIC and TSV Interconnect Patent Investigation report. For this analysis of 3D packaging technology patents, more than 1800 patent families have been screened.


MOSIS collaborates with imec, Tyndall and ePIXfab on silicon photonics

Thu, 5 May 2013

MOSIS, a provider of low-cost prototyping and small volume production services for custom ICs, has teamed up with imec, Ireland's Tyndall National Institute and ePIXfab, the European Silicon Photonics support center providing low-cost prototyping services for photonic ICs.


Amkor Technology appoints Steve Kelley president and CEO

Wed, 5 May 2013

Amkor Technology, Inc. today announced that Stephen D. Kelley has been appointed to serve as president and chief executive officer and as a director of the company, effective May 8, 2013.


Rudolph purchases assets from Tamar Technology

Mon, 4 Apr 2013

Rudolph Technologies, Inc. announced today that it has purchased selected assets, including a patent portfolio, relating to metrology capability from Tamar Technology, Newbury Park, Calif.


ESI acquires Semiconductor Systems business of GSI Group

Wed, 4 Apr 2013

 Electro Scientific Industries, Inc. today announced it had signed a definitive agreement to acquire the Semiconductor Systems business of GSI Group, Inc., a supplier of precision photonics, laser-based solutions and precision motion devices to the medical, industrial, scientific, and electronics markets


Global semiconductor sales outpace last year through Q1 of 2013

Tue, 5 May 2013

Sales in March 2013 were up slightly compared to February 2013 and March 2012.


2013: 450mm is the next big opportunity

Thu, 1 Jan 2013

In semiconductor manufacturing, 450mm is the next big opportunity. Issues of economic scale and complexity will force fab designers, OEMs and process integrators to investigate all open avenues in the search for solutions to the huge challenges that accompany 450mm.


2013: Continued strength in 200mm

Thu, 1 Jan 2013

80 percent of the devices used for portable and mobile applications are currently manufactured on 200mm or smaller wafers. How this plays out going forward could change who the dominant players will be.


2013: Accelerating R&D and decreasing time to yield

Thu, 1 Jan 2013

In order to maintain profitability manufacturers must increase the productivity and return from their R&D investments.


2013: Advanced packaging requirements are more complex, require new solutions

Wed, 1 Jan 2013

Advanced packaging requirements are driving the evolution of back end manufacturing to become more similar to the front end.


2013: Thriving in the transition to 450mm

Wed, 1 Jan 2013

The development of innovative technologies that solve the critical issues for the transition and adoption of 450-mm manufacturing will be the defining factor for whether a company merely survives or thrives.


2013: Building the internet of things with MEMS and 3D advances

Wed, 1 Jan 2013

It is becoming increasingly clear that new MEMS and 3D high-volume, low-cost manufacturing technologies will accelerate a radical change to society’s cyber skyline.


ISSCC 2013: Imagers, MEMS, medical and displays

Mon, 2 Feb 2013

Roland Thomas, subcommittee chair of ISSCC, writes of the substantial growth and future in key areas of technology.


Dow Corning and IBM scientists develop new materials for board-level photonics

Tue, 2 Feb 2013

Dow Corning and IBM scientists unveiled a major step in photonics yesterday at the Photonics West conference, using a new type of polymer material to transmit light instead of electrical signals within supercomputers and data centers.


Semiconductor R&D spending rises 7% despite weak market

Tue, 2 Feb 2013

Spending on research and development by semiconductor companies grew 7% in 2012 to a record-high $53.0 billion, even though the semiconductor market declined 1% to $317.6 billion.


STATS ChipPAC and UMC unveil 3D IC developed under open ecosystem

Wed, 1 Jan 2013

STATS ChipPAC and UMC announced the world's first demonstration of TSV-enabled 3D IC chip stacking technology developed under an open ecosystem collaboration.


Renesas and J-Devices sign MoU on transfer of back-end facilities

Wed, 1 Jan 2013

Renesas and J-Devices signed a memorandum of understanding regarding the transfer of the semiconductor back-end production business of three facilities operated by Renesas’ wholly owned manufacturing subsidiaries


Global 3D IC market report reveals major challenges

Mon, 2 Feb 2013

TechNavio's analysts forecast the global 3D IC market to grow at a CAGR of 19.7 percent over the period 2012-2016. However, the thermal conductivity issues could pose a challenge to the growth of this market.


ISSCC 2013: High-performance digital trends

Mon, 2 Feb 2013

Subcommittee chair Stefan Rusu of Intel in Santa Clara, CA will present on trends in high-performance digital. The relentless march of process technology, he says, brings more integration and performance.


IEDM 2012: The pivotal point for monolithic 3D ICs

Mon, 1 Jan 2013

Zvi Or-Bach, President & CEO of MonolithIC 3D Inc., blogs about the evolution of 3D technology seen at the International Electron Devices Meeting.  


Researchers create semiconductor 'nano-shish-kebabs' with potential for 3-D technologies

Wed, 2 Feb 2013

Researchers at North Carolina State University have developed a new type of nanoscale structure that resembles a “nano-shish-kebab,” consisting of multiple two-dimensional nanosheets that appear to be impaled upon a one-dimensional nanowire.


Flip-Chip expected to grow at a steady 9% pace, reaching $35 billion by 2018

Mon, 3 Mar 2013

Flip-Chip is big on value: in 2012, it was a $20B market, making it the biggest market in the middle-end area, and Yole Développement expects it to continue growing at a 9% clip, ultimately reaching $35 billion by 2018.


EV Group ships 300mm wafer bonding system to leading Chinese semiconductor foundry

Wed, 3 Mar 2013

Foundry to use wafers for 3D IC and advanced packaging volume production applications.


AGC and nMode launch subsidiary to develop advanced packaging technology

Tue, 3 Mar 2013

Tokyo-based Asahi Glass Co., Ltd. and nMode Solutions Inc. of Tucson, Arizona, have invested $2.1 million to co-found a subsidiary business, Triton Micro Technologies , to develop via-fill technology for interposers, enabling next-generation semiconductor packaging solutions using ultra-thin glass.


Blog: Dimensional scaling and the SRAM bit-cell

Thu, 3 Mar 2013

Zvi Or-Bach, President & CEO of MonolithIC 3D Inc. and Benjamin S. Louie of Zeno Semiconductor blog about dimensional scaling as it relates to EUV and future per transistor device cost.


Silex and BroadPak partnership produces 2.5D IC packaging capabilities

Tue, 4 Apr 2013

Silex Microsystems and BroadPak today announced the immediate availability of their jointly developed silicon interposer solution in high-volume manufacturing.


FlipChip International and EZconn Czech a.s. announce partnership

Mon, 3 Mar 2013

FlipChip International (FCI), a developer of flip chip bumping, Wafer Level and embedded die packaging and EZconn Czech a.s. announced a partnership agreement today.


GLOBALFOUNDRIES demonstrates 3D TSV capabilities on 20nm technology

Tue, 4 Apr 2013

GLOBALFOUNDRIES today announced the accomplishment of a key milestone in its strategy to enable 3D stacking of chips for next-generation mobile and consumer applications.


RAM-memory-research-A-RAM-RERAM-MSDRAM-MELRAM projects

Wed, 10 Oct 2010

CNRS research on memory wafer fabWhile speculation abounds about what will be the next generation of memories and their applications, CNRS, a French government-funded research organization, has 4 new concepts of memories in 2010. The organization is actively recruiting collaborators on RE-RAM, A-RAM, MS-DRAM, and MELRAM memory technologies.


ConFab video: End user choices for 3D integration still unsettled

Thu, 5 May 2010

Tony Flaim, CTO at Brewer Science, describes the work the company is doing to enable 3D integration. While progress is moving forward, he tells SST's Debra Vogler that end users are still somewhat unsettled in their choices of manufacturing technologies.


Playing the field: Qualcomm embraces GlobalFoundries, reups with TSMC

Fri, 1 Jan 2010

Fabless giant Qualcomm has made two deals to reserve leading-edge semiconductor manufacturing capacity: one with longtime partner TSMC, and the other with upstart GlobalFoundries.


IEDM Reflections, Day 1: 2Xnm NAND, 3D integration, graphene FETs, biosensors

Wed, 12 Dec 2010

Techcet's Michael A. Fury reports in-depth from sessions at IEDM 2010, looking at papers on NAND flash using airgaps, a lock-and-key method for 3D integration, RF performance of graphene FETs, and FET-built DNA biosensors.


Tegal-expands-ProNova-ICP-silicon-DRIE-reactor-family

Wed, 12 Dec 2010

Tegal Corporation (Nasdaq: TGAL) is launching a new member of its ProNova family of high-density inductively coupled plasma (ICP) reactors for the company’s DRIE series wafer processing products. The ProNova2 is targeted for fast-growing 200mm MEMS and 3D IC applications.


Research updates on EUV, mask, cleaning, etc from Leti

Fri, 7 Jul 2010

In these three video interviews from SEMICON West 2010, Leti research directors speak with senior technical editor Debra Vogler. Yannick Le Tiec discusses cleaning; Michel Brillouet speaks on 3D packaging work, and Didier Louis updates us on advanced lithography.


Gary Smith EDA market statistics 2010: Summary

Thu, 7 Jul 2010

The biggest change in 2009 was Mentor passing Cadence to become number two in product sales in EDA. This is an indication of the market shift caused by the move into the ESL Methodology. Synopsys remains a strong number one.


CEA-Leti building 300mm R&D line dedicated to 3D integration applications

Tue, 7 Jul 2010

The integration line includes lithography, metallization, deep etching, dielectric deposition, wet etching and packaging tools.


A day at Albany CNSE: Leading-edge techs, innovation vs. efficiency

Tue, 10 Oct 2010

A daylong series of presentations, facility tour, and one-on-one discussions at a recent SEMI-hosted seminar at the U. of Albany College of Nanoscale Science and Engineering (CNSE) spurred intense discussion about the state of leading-edge chipmaking technologies, including 3D ICs and new device structures, and why Wall Street and roadmaps are hampering true technology innovation.


IMEC discusses major projects at SEMICON West

Thu, 8 Aug 2011

Ludo Deferm, IMEC, came to SEMICON West with several major announcements, from the system level to the layers of semiconductors. IMEC's major interests include scaling with 3D technologies, selective epitaxy, RRAM, lithography, and more.


SEMI comments on 450mm standards collaboration

Fri, 7 Jul 2011

Jonathan Davis, SEMI, chats about standards development in 450mm and 3D IC, as well as the importance of collaboration, and how it is happening at SEMICON West.


Customers, logic reshaping supplier collaboration landscape

Tue, 5 May 2011

Harvey Frye, vice-chairman of TEL America, summarized the new supplier landscape in his Confab talk, taking both a macro point of view of trends, and how his company as a top supplier is addressing them: collaboration among suppliers, and an increasing focus on consumer needs.


Imec brings new device architecture results to SEMICON West

Mon, 7 Jul 2011

At SEMICON West, imec is demonstrating a viable implant-free quantum-well (IF-QW) pFETs with an embedded silicon-germanium (SiGe) source/drain and 3D integration of a commercial DRAM chip on top of a logic IC.


2011 Best of West award finalists announced

Wed, 7 Jul 2011

Solid State Technology and SEMI today announced the finalists for the 2011

CEA-Leti Annual Review: The heart of Europe's semiconductor industry challenges

Tue, 6 Jun 2011

At CEA-Leti's Annual Review, Leti CEO Laurent Malier noted how the important role that research and technology organizations should play in strengthening industry in Europe, and how their roles differ from groups in other regions.


Historic semiconductor industry, SEMI moments from Stanley Myers

Wed, 7 Jul 2011

Stanley T. Myers talks what moments stand out for him as "historic" advances in semiconductor fab and the evolution of SEMI. He also shares advice for young engineers entering the semiconductor industry.


IEDM 2011: Hollow copper 3D TSVs

Mon, 11 Nov 2011

DAC seeks speakers bureau experts

Wed, 11 Nov 2011

The Design Automation Conference (DAC) is soliciting semiconductor industry experts for participation in invited sessions, panels, and other events at the 49th DAC, June 3-7, 2012 in San Francisco, CA.


SEMICON West 2012: Submit an abstract today

Mon, 12 Dec 2011

SEMI is looking for presenters for technical sessions and other opportunities at SEMICON West 2012, July 10-12 in San Francisco, CA.


imec's IEDM papers reach "record number"

Wed, 12 Dec 2011

imec is presenting a record number of 17 papers at the IEEE International Electron Device Meeting (IEDM), ending today in Washington, DC.


ASMC 2011: Rain doesn't damper the spirit

Tue, 5 May 2011

Intermolecular's John Behnke offers his impressions from Day 1 of this year's SEMI/IEEE Advanced Semiconductor Manufacturing Conference (ASMC) in New York. Highlights: a keynote from a suddenly famous GlobalFoundries exec, on-the-fly edge inspection, equipment health monitoring, and a TSV overview.


ASMC 2011: Approaching device scaling, manufacturing challenges with partnerships

Wed, 5 May 2011

Another eventful (but still rainy) day at this week's SEMI/IEEE Advanced Semiconductor Manufacturing Conference (May 16-18) offered two highlights sharing a theme: how partnerships can address challenges in device scaling and manufacturing.


Tessera focuses on semiconductor technologies beyond packaging

Thu, 4 Apr 2011

Tessera Technologies Inc. (Nasdaq:TSRA - News) began two corporate initiatives to expand its technologies in semiconductor microelectronics beyond packaging, and to potentially separate its Imaging & Optics business.


Pioneering new devices and materials for future ICs

Sun, 5 May 2011
It is expected that from the 15nm node on, the industry will need to adopt new transister architectures; among the contenders: FinFETs and TunnelFETs. Thomas Hoffmann, imec, Leuven, Belguim

Day 2, 3 talks on process integration, reliability, 3Di

Wed, 5 May 2011

John Iacoponi, IITC 2011 co-chair, reviews Day 2-3 discussions at IITC/MAM, including interconnect reliability, BEOL memory, 3D integration, process integration, ultralow-k, and future-looking talks on graphene and carbon nanotubes.


3D IC is only solution for scaling "up," says MonolithIC 3D exec

Thu, 3 Mar 2011

Transfer on top of processed wafer and replace gates (<400°C)Zvi Or-Bach, MonolithIC 3D, describes the TSV-beating monolithic IC fab process, and argues for scaling "up" rather than down. Or-Bach compares the costs of further semiconductor scaling to advanced packaging.


ASICs and FPGAs could take a lesson from autos, says Xilinx

Thu, 5 May 2011

Ivo Bolsens, Xilinx, compares crossover cars -- sports car performance with station wagon utility -- to semiconductor ASICs (high-performance) and FPGAs (flexible, easy to use, less NRE). The semiconductor industry needs a programmable platform that has ASICs' capabilities.


Imec ITF: The next wave of applications, with chips designed in 3D

Wed, 5 May 2011

In an SST-exclusive series of blogs, imec reports from its International Technology Forum this week in Brussels. Here, Jan Provoost looks at Pol Marchal's presentation on 3D integration and its impact on systems design -- and why sensors that smell are coming next.


SEMI says innovation is in, expensive differentiation is out

Mon, 5 May 2011

Tom Morrow, EVP, Emerging Markets Group/Chief Marketing Officer, speaks at ConFab 2011 about the semiconductor market's rebound from March 11's Japan earthquake, emerging markets like LEDs, and the trade organization's standards program for 3D ICs.


Trade-offs and infrastructure are keys to device scaling

Wed, 5 May 2011

Raj Jammy, VP of materials and emerging technologies at SEMATECH, covered a broad swath of CMOS scaling drivers, system and device trends, and infrastructure requirements.


Failure analysis challenges at 22nm turnkey FA tools

Tue, 1 Jan 2011

Paul Kirby, FEI, provides insights on the shift to complex 3D device structures and complex interconnect methods such as TSV. In the future, 3D analysis techniques could play increasingly important roles, he says. In advanced packaging, failure analysis is more critical because multi-die stacks can fail due to one bad die. This is an online exclusive essay in SST's Forecast for 2011: Back to Reality series.


ITRS 2010: What happened during this off-year?

Wed, 1 Jan 2011

The 2010 Update to the International Technology Roadmap for Semiconductors (ITRS), while not one of the scheduled major revisions, nevertheless includes substantial changes have occurred in 2010, including boosts in the timelines for NAND flash and DRAM device rollouts, backup plans for lithography forced by EUV delay, impending device and interconnect structural changes, and progress in 3D packaging.


3D-CT-X-ray-imaging-fills-inspection-gaps-says-Xradia

Tue, 3 Mar 2011

Xradia microscope.Xradia has unveiled its latest micro computed tomography (CT) 3D X-ray imaging system, the VersaXRM. Kevin Fahey, PhD, VP of marketing at Xradia, discusses how the new platform uses geometrical magnification in tandem with an X-ray microscope.


Tabula-3D-PLD-fabless-raises-$108-million

Mon, 3 Mar 2011

Tabula will use the new capital to accelerate production of their 3PLD ABAX product family, expand customer and partner support infrastructures, and further next-generation product development in the rapidly growing programmable logic sector.


Applied-Materials-plasma-doping-tech-builds-3D-transistors

Thu, 3 Mar 2011

Applied Materials Inc. (AMAT) introduced the Applied Centura Conforma, with conformal plasma doping (CPD) targeted for 22nm and beyond logic and memory chips. The technology replaces ion beam implantation for conformal doping of complex 3D structures.


SEMATECH's Bryan Rice: Why it's time for a "refresh"

Tue, 10 Oct 2011

Bryan Rice, SEMATECH's newly appointed director of strategic initiatives, tells SST what his new job entails: what he sees as his biggest challenges, which areas will keep SEMATECH's main attention (hint: the "once and future king" of resources), and what new areas are being explored.


SEMICON Taiwan preview: Forums span key technology, markets

Tue, 8 Aug 2011

SEMICON Taiwan (Sept. 7-9) approaches, the island's most celebrated event for microelectronics manufacturing, coorganized by SEMI and the Taiwan External Trade Development Council (TAITRA), offers more than 60 programs and sessions and 550 exhibitors spanning the entire semiconductor value chain and related high-growth industries.


Inside Leti: FDSOI, 3D packaging, Si photonics work

Fri, 8 Aug 2011

Laurent Malier, CEO of Leti, described the research group's work and the outlook on fully depleted silicon on insulator (FDSOI), 3D packaging technologies, and integrated photonics on silicon.


Present at VLSI Technology and Circuits

Mon, 10 Oct 2011

The 2012 Symposia on VLSI Technology & Circuits, to be held in Hawaii, June 12-14 (Technology) and 13-15 (Circuits), will accept innovative, original work on microelectronics, ranging from gate stacks and advanced lithography to 3D packaging.


IDM economics at 32nm and beyond

Wed, 5 May 2008
by Ed Korczynski, senior technical editor, Solid State Technology
May 21, 2008 - Masaaki Kinugawa, GM of Toshiba's Oita operations, discussed the tough challenges faced by fabs developing advanced processes today in his Confab talk, including increasing complexity of process and device technologies (and proportionally rising costs) -- and an ugly truth waiting around the corner at the 32nm node.

Economics may drive push to 3D ICs, says SEMATECH's Arkalgud

Wed, 5 May 2008
by Bob Haavind, Editorial Director, Solid State Technology
May 21, 2008 - Beyond today's stacked chips in a package may come higher performance 3D stacked ICs using through-silicon vias to interconnect layers, according to Sitaram Arkalgud, who spoke on the economic implications of 3D at the ConFab in Las Vegas.

3D for microprocessors now...TSV later

Wed, 5 May 2008
by Ed Korczynski, senior technical editor, Solid State Technology
May 21, 2008 - While manufacturing of 3D ICs is today limited mostly to memory chip stacks and cell-phone camera modules, the next huge application seems to be the embedded memory in microprocessors. Subramanian Iyer, distinguished engineer and chief technologist of IBM's systems and technology group, explained the economic considerations behind 3D microprocessors at the ConFab in Las Vegas.

U. Albany's Denbeaux: EUV works, though far from what's needed

Tue, 3 Mar 2008
by Bob Haavind, Editorial Director, Solid State Technology
An insightful update on three key semiconductor technologies -- SOI, TSV/3D, and SOI -- sparked a lively Q&A following a SEMI-sponsored breakfast near Boston (Mar. 5). Here, Gregory Denbeaux, assistant professor of nanotechnology at the U. of Albany, gave an overview of progress needed in EUV to make it suitable for high volume manufacturing.

SEMATECH's Arkalgud: A 3D/TSV route to higher IC densities

Tue, 3 Mar 2008
by Bob Haavind, Editorial Director, Solid State Technology
An insightful update on three key semiconductor technologies -- SOI, TSV/3D, and SOI -- sparked a lively Q&A following a SEMI-sponsored breakfast near Boston (Mar. 5). Here, Sitaram Arkalgud, head of SEMATECH's 3D interconnect program in Albany, discusses the expected evolution of through-silicon vias (TSVs) and 3D chip stacks for future electronics.

IBM's Starkey: The case for SOI won't diminish w/ shrink

Tue, 3 Mar 2008
by Bob Haavind, Editorial Director, Solid State Technology
An insightful update on three key semiconductor technologies -- SOI, TSV/3D, and SOI -- sparked a lively Q&A following a SEMI-sponsored breakfast near Boston (Mar. 5), held at an MKS Instruments facility. Here, Gordon Starkey, a senior engineer in technical operations for IBM, explained how silicon-on-insulator (SOI) has made a transition from a niche to mainstream technology.

Tracking the future of TSV

Thu, 2 Feb 2008
by Ed Korczynski, Senior Technical Editor, Solid State Technology
A new report from TechSearch International forecasts millions of silicon wafers will be made with through-silicon vias (TSV) in the year 2014. With TSV technology now moving past the feasibility (R&D) phase and into the commercialization phase, the question isn't whether this 3D interconnect will be adopted, but how soon it will balance cost/performance vs. existing technologies to break into real mainstream use.

Ziptronix joins low-cost quest for true 3D-IC

Wed, 10 Oct 2008
Ziptronix execs reveal technical details on its direct bond interconnect technology, which the company says is key to low-cost wafer-to-wafer or chip-to-wafer bonding without high-temperature compression.

Suss swaps CEO over "differing" strategic views

Tue, 10 Oct 2008
Suss MicroTec has replaced board member and CEO Stefan Schneidewind with Christian Schubert effective immediately, citing "differing views regarding the future strategy of the company." A search for a new permanent CEO will take place.

Tegal+AMMS eyes growth in 3D packaging, MEMS

Mon, 9 Sep 2008
Tegal Corp.'s proposed acquisition of Alcatel Micro Machining Systems' (AMMS) deep reactive ion etch (DRIE) and plasma-enhanced chemical vapor deposition (PECVD) products is "a critical part of our growth strategy" to extend into higher-growth markets in 3D IC packaging and MEMS devices, the company asserts.

IMEC research energetically stacks up

Mon, 10 Oct 2008
Advanced Packaging's Gail Flower reports from presentations at IMEC's recent annual research review, centering on two areas of predicted high growth: 3D stacked ICs including through-silicon vias (TSV), and crystalline Si and organic solar cells.

IMEC, Qualcomm pushing 3D integration

Mon, 7 Jul 2008
July 14, 2008 - Wireless fabless developer Qualcomm has joined European R&D consortium IMEC's industrial affiliation program on 3D integration to understand and develop ways to use 3D wafer-level packaging and 3D stacked ICs in future wireless products.

IMEC: Fabless/fab-lite trend requires extended R&D model

Tue, 7 Jul 2008
In a pre-SEMICON West interview, Ludo Deferm, IMEC's VP of business development, discusses the changes required in R&D models to accommodate fabless/fab-lite companies, and how IMEC is helping research partners understand the impact of 3D technology and the added value of design.

AMAT accelerating TSV implementation, launches Silvia etch tool

Mon, 12 Dec 2008
Sizing up a TSV market beyond the early adopters, Applied Materials is collaborating with material and equipment suppliers (and others) to ensure the full readiness of TSV implementation. AMAT execs update SST on the firm's TSV efforts, including a new TSV process sequence developed with Semitool and a new etch tool.

Tegal seeks "DRIE" land in MEMS

Tue, 9 Sep 2008
Tom Mika, CEO of Tegal, gives SST some further insights into his company's plans behind its proposed acquisition of Alcatel Micro Machining Systems' deep reactive ion etch and other technologies -- including how the company will leverage its existing presence in MEMS, finding the balance between serving R&D and production needs, and fighting much larger competitors.

IMEC's 3D efforts: New higher-AR TSVs for thicker dies

Tue, 8 Aug 2009
Bart Swinnen, director of interconnect and packaging in IMEC's process technology unit, discusses the status of 3D technology efforts -- in particular, IMEC's work on TSV tech that will enable higher aspect ratio TSVs suitable for thicker dies.

Luc Van den hove helms IMEC, discusses strategy

Tue, 6 Jun 2009
Amid preparations for IMEC's 25th anniversary celebration, SST spoke with Luc Van den hove, now president/CEO of European R&D consortium IMEC, who discussed the research center's strategy and the keys to its success over the years.

Alchimer's new TSV process: When less really is more

Mon, 6 Jun 2009
Alchimer CEO Steve Lerner tells SST how its improved eG ViaCoat wet deposition process of copper seed metallization of through-silicon vias (TSV) can now be used on existing dry equipment -- and provides reliability test results.

NEC: Trumping conventional scaling with 3D packaging

Mon, 2 Feb 2009
In a bid to expand applications for 3D packaging, NEC has developed a 3D chip-stacked flexible memory to support large-scale high-performance systems-on-chip (SoC).

EVGroup: Ready for whatever comes with 3D integration

Wed, 8 Aug 2009
Steven Dwyer, VP & GM, North America at EV Group, provides highlights of 3D integration papers the company presented at SEMICON West. By achieving alignment accuracy down to 200nm, thin wafer handling at thicknesses <10μm, and 300mm-capable wafer bonding, he says the company is ready for whatever comes along.

SEMATECH's 3D work in Albany

Wed, 8 Aug 2009
Larry Smith, sr. member of the technical staff in SEMATECH's 3D interconnect division, discusses toolset acquisitions at the U. of Albany's CNSE, where work focuses on replacing traditional global interconnect and intermediate level processes.

Behind Brewer Science's wafer bonding work

Mon, 8 Aug 2009
Karen Twillmann, executive director of corporate marketing at Brewer Science, and Dan Wallace, the company's director of 3D packaging, discusses the advances made by the company's temporary bond adhesive for wafer bond applications.

Memory sector upended, driven by 3D packaging tech, says Yole

Fri, 5 May 2009
New integration trends and disruptive packaging technologies, notably 3D TSVs, will cause major technical changes in the memory semiconductor sector, but ultimately pave the way for future growth, according to a recent report from Yole Développement.

ITRI adds AMAT tools for 3D IC work

Fri, 10 Oct 2009

Taiwan's Industrial Technology Research Institute (ITRI) will add Applied Materials to its partners for developing 3D chip stacking technology, by placing "a full line" of AMAT processing tools in its labs.


How CMP enables innovation in memory, 3D, MEMS

Wed, 8 Aug 2009
Robert Rhoades, CTO, Entrepix, describes the nontraditional technology behind TFT-dual gate memory and how CMP enables that innovation among others -- e.g., TSVs, 3D packaging, MEMS, and engineered substrates.

EVG, AMAT pair for 3D thin-wafer bonding

Fri, 7 Jul 2009
EV Group and Applied Materials say they will jointly develop wafer bonding processes for making through-silicon vias (TSV) in 3D IC packaging applications, working as members within the Semiconductor 3D Equipment and Materials Consortium (EMC-3D).

Applying TCAD sim to PV, 3D TSVs

Thu, 7 Jul 2009
Ric Borges of Synopsys discusses the application of TCAD simulation to multijunction and CPV solar cells.

Future bright for 3D consortium

Wed, 7 Jul 2009
Paul Siblerud of Semitool discusses 3D integration challenges and announces the latest news from the EMC-3D Consortium.

Stepping up to the 3D challenge

Wed, 7 Jul 2009
Soitec's president and CEO, André-Jacques Auberton-Hervé, discusses the three pillars of 3D integration at the wafer level, as well as bonding at room temperature. Also noted is Soitec's partnership with IBM, announced during SEMICON West.

3D integration: A status report

Tue, 7 Jul 2009
3D IC technology, an alternative approach to wire-bonded chip stacking utilizing interconnets with through-silicon vias (TSVs) fabricated with front-end-like processes, is a hot topic at SEMICON West, and the focus of an on-line virtual forum hosted by public relations firm MCA.

ICOS, IMEC to develop 3D packaging metrology

Thu, 7 Jul 2006
July 27, 2006 - ICOS Vision Systems Corp. NV and European R&D center IMEC have agreed to collaborate on development of metrology methods targeting 3D packaging processes for ICs, including wafer-level packaging, flip-chip, systems-in-package, and microelectromechanical systems (MEMS).

Cookson, Microbonds combine insulated wire bonding, mold compounds

Thu, 7 Jul 2006
July 6, 2006 - Cookson Electronics Semiconductor Products and Microbonds Inc. have formed a codevelopment project to combine Microbonds' X-Wire insulated wire bonding technology with Cookson's Plaskon family of mold compounds.

SanDisk widens memory reach with Msystems deal

Mon, 7 Jul 2006
July 31, 2006 - In the latest big move to consolidate power in the memory sector, flash memory giant SanDisk Corp., Milpitas, CA, has agreed to acquire Msystems Ltd., Kfar Saba, Israel, in an all-stock deal valued at up to $1.55 billion, including stock options and convertible debt.

Samsung touts 3D methods, multilayered dielectric in new 50nm DRAM chip

Thu, 10 Oct 2006
October 19, 2006 - Samsung Electronics Co. Ltd. says it has developed a 50nm DDR2 DRAM chip utilizing 3D design and multilayered dielectrics, a process that enhances performance and data storage capabilities.

Consortium to develop cost-effective 3D interconnects

Thu, 10 Oct 2006
October 12, 2006 - A list of equipment providers, materials companies, and researchers have joined to create an international consortium to address technical and cost issues of creating of thru-silicon-via (TSV) 3D chip interconnect, for use in chip stacking and MEMS/sensor packaging.

FlipChip, Engent to make 3D packaging tech

Fri, 5 May 2006
May 26, 2006 - FlipChip International LLC and Engent Inc. are partnering to develop 3D wafer-level CSP (WLCSP) technologies, seen as a low-cost alternative to system-on-chip for highly integrated stacked die packaging applications.

STATS ChipPAC handing low-end packaging ops to China firm

Mon, 6 Jun 2006
June 26, 2006 - STATS ChipPAC Ltd., a provider of semiconductor test and packaging services, has signed a deal with China Resources Logic Ltd. to set up a JV in Wuxi, China, providing assembly and test service for STATS' lower-end leadframe package families, allowing the firm to focus on more leading-edge products such as system-in-package, flip-chip, and 3D technologies.

SEMATECH 3D project seeks interconnect answers

Thu, 2 Feb 2006
February 9, 2006 - SEMATECH has launched a new project to explore the feasibility of three-dimensional (3D) interconnect technology for the semiconductor industry.

IBM tips TSV 3D chip stacking technique

Fri, 4 Apr 2007
April 13, 2007 - IBM says it has developed a way to incorporate through-silicon vias (TSV) into its chipmaking process that shortens data-travel distances by up to 1000x and allows for 100x more pathways than 2D chips. Samples of 65nm chips using the 3D stacking technique will be shipped by year's end, with production ramping in 2008.

Ziptronix 3D interconnect tech targets multilayer CMOS ICs

Thu, 4 Apr 2007
April 5, 2007 - Ziptronix Inc. and Raytheon Vision Systems (RVS) say they have demonstrated compatibility of Ziptronix's "direct bond interconnect" (DBI) interconnect technology with multilayer CMOS IC processes, involving 3D integration of five-layer metal 0.5-micron CMOS devices with silicon PIN detector devices.

IMEC looks to the future as SEMICON West opens

Tue, 7 Jul 2007
As another SEMICON West opens, IMEC's experts discussed with WaferNEWS what they see are they major keys to the future of semiconductor industry: exploring new markets, bringing finFETs into manufacturing, mastering 3D integration, and addressing sub-32nm low-k deposition challenges.

CEA/Leti, Alcatel forge DRIE pact for 3D interconnects

Thu, 7 Jul 2007
July 18, 2007

IMEC extends 3D system integration program

Wed, 7 Jul 2007
July 18, 2007 - IMEC has expanded its 3D packaging research program to fully exploit the potential of novel 3D technologies. Besides 3D interconnection technologies developments, the program is extended with research on system design methodologies. Both the technology and design sub-programs will be based on actual system requirements and closely coupled.

Amkor, IMEC sign agreement for 3D WLP

Wed, 7 Jul 2007
July 18, 2007 - At SEMICON West, Amkor Technology Inc., a provider of advanced semiconductor assembly and test services, and IMEC, the independent nanoelectronics and nanotechnology research center based in Belgium, announced that they have entered into a 2-year collaboration agreement. They will develop cost-effective, 3D integration technology based on wafer-level processing techniques.

Qimonda's Arkalgud to head up SEMATECH's 3D program

Fri, 1 Jan 2007
January 5, 2007 - SEMATECH has appointed Sitaram Arkalgud, appointee from Qimonda/Infineon Technologies, as director of its new 3D interconnect initiative, in addition to his duties leading SEMATECH's interconnect division.

Manufacturing alliances: An expanded role for equipment suppliers

Mon, 5 May 2007
In the new consumer-driven electronics industry, where beating your competition to market with innovative technology is the surest route to success, process control equipment suppliers have an expanded role in manufacturing alliances to help dramatically shorten product-development and production-ramp times, and thus significantly improve yield and profitability, according to Brian Trafas, chief marketing officer at KLA-Tencor, in his talk at the Confab in Las Vegas.

Alcatel, Tronics join for MEMS DRIE

Thu, 6 Jun 2007
June 7, 2007 - Tronics Microsystems SA and Alcatel Micro Machining Systems (AMMS) say they will jointly develop deep reactive ion etch (DRIE) systems for "extreme-performance" MEMS.

June 2007 Exclusive Feature 2: 3D INTERCONNECTS
IITC PREVIEW: Are 3D interconnects ready for prime time?

Fri, 6 Jun 2007
By Phil LoPiccolo, Editor-in-Chief

Among the most significant developments in interconnect slated to appear at this month's International Interconnect Technology Conference (IITC, June 4-6, in Burlingame, CA) involve 3D chip architectures. Sitaram Arkalgud, director of SEMATECH's interconnect division and its newly created 3D interconnect initiative, calls 3D chip architecture his "new religion," because stacked chips allow interconnects to be much shorter than...

STATS ChipPAC readies R&D site in Singapore

Mon, 5 May 2007
May 14, 2007 - STATS ChipPAC has formally established its new R&D facility in Singapore, to develop next-generation technologies including through-silicon vias (TSV), microbump bonding methods for 3D die, silicon substrate-based system-in-package solutions, and embedded active die technology.

STATS ChipPAC offloading more lines to China

Mon, 6 Jun 2007
June 11, 2007 - STATS ChipPAC Ltd. says it will sell certain assembly and test assets for its discrete power packages to China's Ningbo Mingxin Microelectronics Co. Ltd., following a similar transaction a year ago to farm out some work to mainland China in order to pursue better growth opportunities in areas such as system-in-package, flip-chip, and 3D technologies.

PACKAGING BEAT: Industry leaders vie for memory-stacking bragging rights

Tue, 6 Jun 2007
Samsung, Hynix, and Akita Elpida have all made announcements recently about their latest achievements in memory stacking technology. There was definitely a competitive tone to these releases, but they actually appear to be pushing somewhat different agendas.

Tezzaron, Chartered working on 2D "iRAM" hybrid, 3D ICs to come

Tue, 6 Jun 2007
June 12, 2007 - Tezzaron Semiconductor says it is ramping its 2D "3T-iRAM" line of 72Mbit memory devices at Singapore foundry Chartered Semiconductor on the foundry's 0.13-micron process technology, and plans to use this SRAM drop-in replacement as the basis for its first 3D ICs. Robert Patti, Tezzaron CTO, discusses both technologies with WaferNEWS.

IITC PREVIEW: Are 3D interconnects ready for prime time?

Tue, 5 May 2007
Among the most significant developments in interconnect to look for at the upcoming International Interconnect Technology Conference (IITC, June 4-6, in Burlingame, CA) are those involving 3D chip architectures. Sitaram Arkalgud, director of SEMATECH's interconnect division, discusses the "new religion" of 3D chip architecture with WaferNEWS, and explains why it's the most promising route to eliminating the main stumbling block to higher chip speeds and lower power consumption.

Elpida joins IMEC's CMOS research platform

Wed, 3 Mar 2007
March 14, 2007 - Elpida Memory Inc., a Japanese supplier of dynamic random access memory (DRAM), has entered into a multi-year partnership with IMEC, an independent nanoelectronics research center, to perform R&D for beyond 50nm DRAM process generations, said IMEC today.

Moore's Law to head z-ward?

Mon, 10 Oct 2007
While the industry struggles to continue on the Moore's Law track, 3D approaches superior to those of systems-on-chip may provide an interim solution if the shrink slows down. A SEMATECH-organized workshop in Albany, NY earlier this month (Oct. 11-12) addressed fundamental issues about 3D, including four reasons why every chipmaker has 3D/TSVapproaches on its roadmap, and what needs to be solved before 3D can be effective beyond simple memory.

EV Group, Brewer demo ultrathin wafer bonding platform

Wed, 12 Dec 2007
December 5, 2007 - EV Group (EVG) and Brewer Science say they have demonstrated temporary wafer bonding capabilities for a wide range of backside processes, including through-silicon vias (TSVs) and backside metallization, using an approach optimized for high-temperature advanced packaging applications.

STATS ChipPAC expanding flip-chip services in China

Tue, 11 Nov 2007
November 20, 2007 - STATS ChipPAC says it will expand its flip-chip offerings to its Shanghai, China operation, encompassing wafer bump, sort, assembly and final test. Volume production is expected to start in 1H08, followed by a second phase adding electroplated wafer bumping capabilities for 200mm wafers in 1H07 and 300mm wafers in 2H08.

Trio creates Dresden center under "Nanoanalysis" R&D project

Tue, 11 Nov 2007
November 6, 2007 - AMD, Carl Zeiss SMT, and Qimonda AG are forming a 12M euro (US ~$17.4M) "innovation center" in Dresden, Germany ("Silicon Saxony"), under a larger "Nanoanalysis" project to develop new analytical and characterization methods for next-gen chip development.

Ziptronix reports first 3D SoC

Mon, 9 Sep 2005
September 26, 2005 - Ziptronix, Morrisville, NC, has made good on its efforts at creating a three-dimensional IC device to serve as an alternative to system-in-package (SiP) technology, according to a company statement.

Ziptronix appoints Phil Nyborg as new CEO

Wed, 3 Mar 2005
March 2, 2005 - Ziptronix has appointed 17-year semiconductor industry veteran Phil Nyborg as its new president and CEO. The company said that Nyborg will guide it as it more fully commercializes its proprietary bonding and interconnect processes for 3DICs.

RSL opens packaging R&D lab with Suss MicroTec

Wed, 8 Aug 2005
August 10, 2005 - RoseStreet Labs (RSL), Phoenix, AZ, has announced the opening of its 3D Research and Development laboratory for next-generation semiconductor packaging, as well as an alliance with Suss MicroTec, which will provide the lab with a full suite of lithography and 3D packaging equipment.

Amkor to expand development of 3D IC packages

Thu, 4 Apr 2001
April 5, 2001 - West Chester, PA - Amkor Technology is expanding its development and qualification of 3D IC packages in order to reduce production costs and handling time. 3D or stacked ICs also require less space, have higher reliability and better electrical performance than the combination of devices they replace, the company said.

3D Packaging — Which Way to Go?

Mon, 1 Jan 2008
adapted for print by AP editors

This article, the first in a series of three on 3D packaging technology, summarizes information presented during a November 2007 webcast produced by Advanced Packaging magazine. Participants were Jean-Christophe "J.C." Eloy, founder and GM of Yole D

Electromechanical Coating Processes

Fri, 5 May 2008
eG ViaCoat is the latest in Alchimer's eGTM series of electrochemical coating processes, for the metallization of high aspect ratio through-silicon vias (TSVs) used in advanced 3D packaging applications. It reportedly produces conformal, thin, uniform, and adherent copper seed layers, even on resistive barriers. It is said to enables significant reductions in cost of ownership (CoO) compared to dry vacuum processes.

3D Interconnection Cube

Fri, 12 Dec 2008
The 3D interconnection chip carrier from Microcertec S.A.S 3-D combines precision-grinding of ceramics with thin-film metallization and laser micromachining to create a 3D package option for chips and ICs.

Datacon Technology Joins EMC-3D Consortium

Wed, 4 Apr 2008
(April 9, 2008) Radfeld, AUSTRIA — EMC3D, an international semiconductor equipment and materials consortium dedicated to the cost-effective development of 3D through silicon via (TSV) interconnects, announced the addition of Datacon Technology to the organization. Datacon, manufacturer of die bonding & sorting equipment will provide high-precision assembly expertise to the consortium.

BiTS Workshop: A Success Story

Mon, 4 Apr 2008
By Gail Flower, editor-in-chief
The ninth annual Burn-in and Test Socket Workshop (BiTS 2008) on March 9-12, 2008 in Mesa, AZ, presented an interactive, growing, and technical successful forum for experts dedicated to sharing knowledge. BiTS brought together 350 conference attendees and 60 exhibitors worldwide from users of sockets, boards, burn-in systems, handlers, packaging engineers, and suppliers to the industry.

3D Packaging Technologies Expected to Dominate Industry

Wed, 4 Apr 2008
(April 23, 2008) Palo Alto, CA— 3D packaging is expected to emerge as a dominant performing solution in the electronic/chip packaging industry. Its performance promises to drive efforts across the entire supply chain to successfully deploy it, according to analysis reports from Frost & Sullivan's Global Trends in Electronic/Chip Packaging. Analysis indicates that the industry is moving beyond system on chip (SoC) to explore various forms of system in package (SiP).

New Study Forecasts Realistic 3D TSV Market

Wed, 2 Feb 2008
(February 13, 2008) Austin, TX — A new study reports that 3D through-silicon vias (TSV) will eventually be adopted, but the timing for mass production depends on how the cost of the new technology compares with that of existing technologies. Design, thermal, and test issues remain a barrier to TSV adoption in some applications, although progress is being made.

Cost Analysis Tool for 3D IC Manufacturing

Mon, 3 Mar 2008
This intuitive cost-of-ownership (CoO) tool model is specifically designed to evaluate the cost of a given through-silicon-via (TSV) process flow. It has been developed using Excel so as to be widely exploitable and upgradable. This CoO tool will enable evaluation of the cost/wafer level for manufacturing TSVs using user inputs or pre-defined parameters.

IEEE International Interconnect Technology Conference Goes 3D

Tue, 5 May 2008
(May 7, 2008) Burlingame, CA — When the IEEE International Interconnect Technology Conference convenes at the Hyatt Regency San Francisco Airport Hotel, Burlingame, CA, June 1-4, the focus will be squarely on 3D technologies. Attendees will have the opportunity to gain both fundamental knowledge and practical manufacturing advice from 3D experts at chip companies and universities from around the world.

SMTA's 3D/SiP Symposium Promotes Industry-wide Collaboration

Tue, 5 May 2008
Last week's 3D/SiP Symposium hosted by SMTA, and co-sponsored by Advanced Packaging magazine, turned out to be an intimate gathering of approximately 55 attendees representing not only the U.S., but Canada, France, Japan, Taiwan, United Kingdom, Austria and the Republic of Korea.

Oerlikon Esec Introduces Product Family at SEMICON Singapore

Mon, 5 May 2008
(May 5, 2008) Cham, Switzerland and Singapore — Oerlikon Esec, provider of automated chip assembly equipment and system solutions for the semiconductor industry, formally introduced the introductory platform of an entirely new product family at an official unveiling during SEMICON Singapore. The Die Bonder 2100 xP targets the high-volume epoxy die attach market.

EV Group Expands Presence in Korea

Wed, 5 May 2008
(May 14, 2008) St. Florian, AUSTRIA — EV Group, equipment manufacturer for semiconductor, MEMS, and nanotechnology applications, announced the opening of a subsidiary, EV Group Korea Ltd., in Seoul, Korea to serve as a direct-to-customer site for sales, service, and support efforts for EVG's existing and potential new customer base. The subsidiary will reportedly house sales, service, process/application and administrative capabilities.

3D Integration Tour: Are TSVs the Future of Advanced Packaging?

Thu, 5 May 2008
By Julia Goldstein, contributing editor
(May 22, 2008) San Jose, CA — The "3D Integration North American Tour" came to San Jose on May 15 after stops in Durham, NC and Dallas, TX. The event, hosted by SUSS MicroTec, Surface Technology Systems (STS) and NEXX Systems outlined the current state of the art in through silicon vias (TSVs) and related technology.

Two Routes to TSV Emerging

Fri, 7 Jul 2007
By Bob Haavind, editorial director, Solid State Technology

3D chip packaging with through-silicon vias (TSVs) will transform the industry over the next 3–5 years, say presentations and discussions at SEMICON West. Using TSVs could enable compact packaging with increased performance. Two approaches to TSV are leading the evolution.

3D Conference Looks at Successful Integration Routes

Tue, 12 Dec 2008
By Gail Flower, editor-in-chief
(December, 2, 2008) BURLINGAME, CA — On November 17

3D Packaging — How to Build 3D Packages from Design through Materials & Equipment

Mon, 2 Feb 2008
adapted for print by AP editors

This article is the second in a series on 3D packaging technology, and summarizes information presented during a December 2007 webcast produced and hosted by Advanced Packaging magazine. Participants included: Dan Schmauch and Rozalia Beica, Semitool Inc.; Jean-Marc Thevenoud, Alcatel MicroMachining Systems; and Markus Wimplinger, EV Group.

The Trouble with News

Thu, 5 May 2008
You would think that because I’m a National Public Radio junkie, news would be of vital importance to me – any type of news.

It’s About Time

Tue, 7 Jul 2008
What do you do when work doesn’t leave a moment to spare? You take a break to gain a new perspective.

Enabling Cooling Strategies for 3D packages

Tue, 7 Jul 2008
Riding on recent advances in nano-fabrication technology, thin-film thermoelectric coolers (TF-TEC) have been developed with active material as thin as 10-20

Designing Modern 3D Packages with Mixed Technology Content

Tue, 1 Jan 2008
Packaging technology has evolved over the years, transitioning into more of a revolution with the introduction of new packaging styles practically every month. Designers face designing extremely high-performance packages with mixed technology content such as high speed digital, analog, and RF.

iNEMI Takes Roadmap Workshop to Asia

Mon, 5 May 2006
Herndon, VA — The International Electronics Manufacturing Initiative (iNEMI) will hold a 2007 Roadmap workshop in Shanghai, China, in tandem with the High-density Microsystem Design and Packaging and Component Failure Analysis in Electronics Manufacturing (HDP) 2006 conference. The half-day workshop will take place June 27, 2006, on the Yan Chang Campus of Shanghai University.

Package-on-Package Trends and Technology

Sat, 7 Jul 2006
Destined for Growth

Actel Delivers 4x4 mm Package for FPGAs

Wed, 11 Nov 2007
(November 14, 2007) MOUNTAIN VIEW, CA — Actel Corp. has announced it is offering its low-power 5mW IGLOO field-programmable gate arrays (FPGAs) in a 4-mm package with a 0.4-mm ball pitch, reportedly the smallest package for any programmable logic device on the market.

Fred Roozeboom, Ph.D., of NXP Joins EMC3D Consortium as Technical Advisor

Wed, 11 Nov 2007
(November 14, 2007) EINDHOVEN, The Netherlands — Fred Roozeboom, Ph.D., research fellow at NXP Semiconductors Research and a professor at the Eindhoven University of Technology, has agreed to join the EMC3D consortium and provide technical advice and guidance in support of the EMC3D effort to quickly bring the technology of through-silicon via (TSV) chip stacking to market.

SEMICON Europa: An Editor's Perspective

Tue, 10 Oct 2007
For an editor of a semiconductor manufacturing publication, there are several sides to every trade show. On one hand are the technical sessions, where we get a glimpse of the latest and greatest technologies being developed. On the other hand, are the industry players

Viewpoint
3D Integration: Preparing a Brilliant Future

Fri, 11 Nov 2007
By Rudi Cartuyvels, IMEC

3D integration explores the possibilities to interconnect active devices in different 2D planes. These interconnects can be considered at different levels of the wiring hierarchy, from the package, over global, to local interconnect levels. The future looks bright for 3D integration, as it promises to become a Holy Grail for system integration with uses in electronics, consumer, automotive, medical, office, and networking applications.

Agilent Technologies and Multiprobe to Expand Partnership

Tue, 12 Dec 2007
(December 4, 2007) SANTA CLARA, CA — Agilent Technologies Inc. and Multiprobe Inc. today announced their intent to expand the companies' strategic partnership. As a result, Agilent will sell and support Multiprobe's Multiscan atomic force prober (AFP) to customers in Asia and Japan.

APEX EXTRAVAGANZA

Fri, 3 Mar 2003
The following companies will be exhibiting these products at APEX 2003, taking place Monday, March 31 through Wednesday, April 2 in Anaheim, Calif. Be sure to visit them to see their latest innovations, and pick up SMT's official Show Daily for more product coverage. ( March 28)
Click here for these and more product briefs.

STMicroelectronics uses TSV in high-volume MEMS devices

Tue, 10 Oct 2011

STMicroelectronics (NYSE:STM) has implemented through-silicon vias (TSV) in high-volume micro electro mechanical system (MEMS) devices. ST is using TSV in its smart sensors and multi-axis inertial modules.


Silex MEMS TSV tech licensed to Nanoshift

Wed, 11 Nov 2011

Silex Microsystems licensed its Silex Sil-Via through-silicon-via (TSV) packaging platform to Nanoshift for use in early development of complex MEMS products.


MEMS alternatives for miniature auto-focus cameras

Wed, 11 Nov 2011

Dr. Giles Humpston, Tessera, presents the free, on-demand webcast Lens Tilt in Small Auto-Focus Cameras. Dr. Humpston covers the dominant auto-focus miniature camera technology today -- VCM -- and an improved technology based on MEMS, which is being commercialized now.


Lam Research ships first 300 mm system for 3-D IC through-silicon via etch

Wed, 8 Aug 2007
Lam Research Corp. has shipped its first 300 mm 2300 Syndion etch system, designed for 3-D IC through-silicon via (TSV) etch applications.

Amkor, IMEC collaborate on 3D wafer-level packaging

Thu, 7 Jul 2007
Amkor, IMEC collaborate on 3D wafer-level packaging

RoseStreet opens new lab with Suss tools

Thu, 8 Aug 2005

Panasonic invests in Alchimer deposition tech for TSVs

Mon, 7 Jul 2010

Alchimer S.A., a provider of nanometric deposition technology for through-silicon vias (TSV), semiconductor interconnects, and other electronic applications, announced that Panasonic Corporation (NYSE: PC) has become an equity investor in the company.


Toshiba tips Si nanowires for 16nm chips

Thu, 6 Jun 2010

Presenting at the VLSI Symposium, Toshiba says it has developed a silicon nanowire transistor with vastly improved on-current levels, targeting 16nm and beyond system LSIs.


SEMATECH acquires etch system from Tokyo Electron

Thu, 10 Oct 2008
October 30, 2008: SEMATECH and the College of Nanoscale Science and Engineering (CNSE) at the U. at Albany will use TEL's Telius SP UD system in a 300mm 3D R&D center.

Tracit's circuit layer transfer tech enables e2v's next-gen image sensors

Thu, 5 May 2007
e2v, developer and manufacturer of electronic components and subsystems, has announced a new generation of high-sensitivity imaging sensors that leverage technology from Tracit Technologies, a new division of the Soitec Group.

NEXX Systems to participate in IMEC's Industrial Affiliation Program on 3D integration

Wed, 6 Jun 2008
June 18, 2008 -- NEXX Systems, a provider of process equipment for advanced wafer-level packaging applications, will participate in IMEC's Industrial Affiliation Program (IIAP) on 3D integration.

Tohoku University and imec partner to advance research

Mon, 6 Jun 2012

Tohoku University of Sendai, Japan and imec signed a collaboration agreement during the Belgian economic mission to Japan, expanding their R&D into areas such as MRAM and 3D semiconductor packaging.


X-Fab takes majority stake in MFI, widens MEMS portfolio to support growth push

Thu, 11 Nov 2012

X-Fab Silicon Foundries says it has become the majority shareholder in German MEMS Foundry Itzehoe GmbH (MFI), the latest in a series of recent moves to raise its profile as a top MEMS foundry.


GlobalFoundries to fab Sand 9's MEMS timing products

Tue, 10 Oct 2012

Sand 9 is partnering with GlobalFoundries for high-volume manufacturing of its microelectromechanical systems (MEMS) timing technology, which incorporates silicon-on-insulator (SOI) and through-silicon vias (TSV).


Silex devs wafer-level MEMS fab technologies for mobile devices

Mon, 1 Jan 2012

Silex Microsystems joined Energy-efficient Piezo-MEMS Tunable RF Front-End Antenna Systems for Mobile Devices to develop TSVs, PZT thin films, and other technologies for high-performance RF systems targeting mobile devices.


Nextreme brings thin-film on-par with bulk thermoelectrics

Mon, 2 Feb 2012

Nextreme Thermal Solutions announced that its thin-film thermoelectric technology has achieved a 60.1°C temperature difference between its cold and hot sides at an ambient temperature of 24.7°C, bringing it on par with the performance of bulk thermoelectric technology.


Applied Materials leads TSV drive for 3D ICs

Mon, 12 Dec 2008
December 1, 2008: Applied Materials Inc. says it is leading a major effort to enable the widespread adoption of through-silicon vias (TSVs) for vertically stacking integrated circuits (ICs) to boost chip performance and functionality, working internally and with other equipment suppliers to develop an integrated, high-performance on-wafer process flow to lower costs, reduce risk, and accelerate time-to-market for customers.

Inside the Hybrid Memory Cube

Wed, 9 Sep 2013
The HMC provides a breakthrough solution that delivers unmatched performance with the utmost reliability.

Ultraviolet light to the extreme

Wed, 10 Oct 2013
For the first time, researchers have mapped this EUV emission and developed a theoretical model that explains how the emission depends on the three-dimensional shape of the plasma.

Packaging at The ConFab

Wed, 9 Sep 2013
At The ConFab conference in Las Vegas in June, Mike Ma, VP of Corporate R&D at Siliconware (SPIL), announced a new business model for interposer based SiP’s, namely the “turnkey OSAT model.” In his presentation “The expanding Role of OSATS in the Era of System Integration,” Ma looked at the obstacles to 2.5/3D implementation and came up with the conclusion that cost is still a significant deterrent to all segments.

Package level integration: challenges and opportunities

Wed, 9 Sep 2013
A wide array of package level integration technologies now available to chip and system designers are reviewed.

STMicroelectronics reveals new micro-packaged device product family

Tue, 9 Sep 2013
Next-generation integrated devices for matching, filtering and protection help shrink circuit size and boost end-product performance.

Micron ships first samples of Hybrid Memory Cube

Wed, 9 Sep 2013
Micron Technology, Inc. announced today that it is shipping 2GB Hybrid Memory Cube (HMC) engineering samples.

3D and 2.5D Integration: A Status Report Live Event

Thu, 6 Jun 2012

This webcast will explore the present status of 2.5 and 3D integration, including TSV formation.


Stanford and UT Austin professors to be honored at annual SRC TECHCON

Thu, 9 Sep 2013
Semiconductor Research Corporation (SRC), a university-research consortium for semiconductors and related technologies, will honor professors from Stanford University and University of Texas at Austin with awards for chip-related research and education at SRC’s annual TECHCON conference Sept. 9-10.

GE acquires Imbera

Thu, 9 Sep 2013
GE Healthcare Finland Oy, in partnership with GE Idea Works, announced today that it has completed the acquisition of Imbera Electronics Oy.

3D-IC: Two for one

Wed, 9 Sep 2013
Zvi Or-Bach, President & CEO of MonolithIC 3D Inc. blogs about upcoming events related to 3D ICs.

Nordic Semiconductor launches world’s first concurrent ANT+ and Bluetooth low energy combo chip

Wed, 10 Oct 2013
Ultra low power (ULP) RF specialist Nordic Semiconductor ASA today announces the release of the world's first multi-protocol SoC solution offering concurrent ANT+ and Bluetooth low energy wireless communication natively in a single chip.

Monolithic 3D chip fabricated without TSVs

Fri, 10 Oct 2013
Researchers from Taiwan’s National Nano Device Laboratories avoided the use of TSVs by fabricating a monolithic sub-50nm 3D using a novel CMP technique.

Samsung starts mass producing industry’s first 3D vertical NAND flash

Tue, 8 Aug 2013

New technology represents a breakthrough in overcoming NAND scaling limit and ushers in a new 3D memory era.


Monolithic 3D is now in production: Samsung starts mass producing first 3D vertical NAND flash

Tue, 8 Aug 2013

Zvi Or-Bach, President & CEO of MonolithIC 3D Inc. blogs about Samsung's recent announcement on 3D vertical NAND.


Monolithic 3D is now on the roadmap for 2019

Thu, 8 Aug 2013

Zvi Or-Bach, President & CEO of MonolithIC 3D Inc. blogs about the appearance of 3D integration on several roadmaps.


Samsung introduces world’s first 3D V-NAND-based SSD

Wed, 8 Aug 2013

Samsung today introduced the first solid state drive (SSD) based on its recently released 3D V-NAND technology. Samsung announced its new SSD, designed for use in enterprise servers and data centers, during a keynote at the Flash Memory Summit 2013.


Entegris and imec collaborate on 3D wafer handling and shipping challenges

Wed, 8 Aug 2013

Entegris, Inc. and imec announced they are collaborating to advance the development and broaden the adoption of 3D integrated circuits.


Dow Corning joins imec for advancement of enabling technologies for 3D-IC

Tue, 7 Jul 2013

Dow Corning announced Monday that it is among the newest member organizations to join imec, a leading research center for the advancement of nano-electronics.


Alchimer signs collaboration with CEA-Leti

Tue, 7 Jul 2013

Alchimer, S.A. today announced a collaboration with the French research institute CEA-Leti to evaluate and implement Alchimer's wet deposition processes for 300mm high-volume manufacturing.


SEMICON West R&D panel discusses the future of semiconductor technology

Wed, 7 Jul 2013

Leaders of research consortia from around the world sat down to share updates and insights with SEMICON West attendees on Wednesday morning.


Getting ready for 10/100/20 – Europe’s manufacturing initiative is underway

Tue, 7 Jul 2013

Europe’s recently launched industrial strategy to reinforce micro- and nanoelectronics manufacturing is more than just a vision — it’s a major opportunity for equipment and material suppliers to participate to large-scale investment projects, increase their holding in key technologies and reach out to new customers and markets.


Hybrid Memory Cube nears engineering sample milestone

Wed, 7 Jul 2013

Engineering samples of The Hybrid Memory Cube (HMC) are expected this summer, with high volume manufacturing coming next year. It will be one of the first high volume devices employing 3D integration and through silicon vias (TSVs), employing a bottom logic layer and 4-8 stacked DRAM layers.


Brewer Science: Simpler bonding/debonding process needed

Thu, 7 Jul 2013

A variety of techniques and materials have been developed to successfully achieve bonding/debonding for 3D integration, but Tony Flaim, chief technology officer of Brewer Science (Rolla, MO) says they are still too complicated.


Rudolph announces new metrology suite for advanced packaging

Wed, 7 Jul 2013

Rudolph Technologies, Inc., a provider of process characterization, photolithography equipment and software for the semiconductor, FPD, LED and solar industries, today released three new application-specific configurations of its industry-leading NSX 320 Automated Macro Defect Inspection System.


EUV vs TSV: Which one will become production ready first?

Wed, 7 Jul 2013

Israel Beinglass, CTO of MonolithIC 3D Inc., blogs about roadmap misses and the relationship between two seemingly unrelated technologies. 


Cascade Microtech and imec successfully probe 25µm-diameter micro-bumps

Thu, 8 Aug 2013

Cascade Microtech, Inc. and imec today announced breakthroughs in probing stacked integrated circuits (3D-SICs), fueling an important growth engine for the semiconductor market.


Moore's Law Dead By 2022: Crying Wolf?

Fri, 8 Aug 2013
Zvi Or-Bach, President & CEO of MonolithIC 3D Inc. blogs about recent predictions regarding the demise of continued scaling.

Dow Corning and EV Group to collaborate on temporary bonding materials for 3D-IC

Tue, 9 Sep 2013
EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, announced today that Dow Corning has joined its network of top technology providers to support EVG's LowTemp platform for room-temperature wafer bonding and debonding processes.

EV Group unveils new via-filling process to improve reliability of 3D-IC/TSV packaging

Wed, 9 Sep 2013
EV Group, a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today unveiled a new polymer via-filling process for 3D-IC/through-silicon-via semiconductor packaging applications.

Collaboration needed on 3D-IC

Thu, 9 Sep 2013
The history of semiconductors has been a history of collaboration. Today, a similar industry-wide collaborative approach to 3D stacked ICs is needed to reach widespread 3D-IC adoption and continue the amazing progress our industry has historically achieved.

Blog Review October 14 2013

Mon, 10 Oct 2013
Recent blogs address semiconductors in healthcare (blood cell sorters), FinFETs and logic roadmaps, 450mm progress, panel level embedded tech, materials innovation, options to reduce mask write time, SOI and EUV.

IBM develops sub-20nm nanofluidic channels for lab-on-chip

Tue, 10 Oct 2013
At IEDM, IBM researchers will report on a CMOS-compatible 200 mm wafer-scale sub-20nm nanochannel fabrication method that enables stretching, translocation and real-time fluorescence microscopy imaging of single DNA molecules.

Rising demand for array IC packaging

Tue, 10 Oct 2013
Small form factor, high speed and performance, and high bandwidth capability with low battery consumption are desired traits for many packaging solutions for integrated circuits (ICs).

Laser thermal anneal to boost performance of 3D memory devices

Wed, 10 Oct 2013
Nanoelectronics research center imec and Excico have successfully demonstrated the application of laser thermal anneal (LTA) to boost the current in vertical polysilicon channel devices for 3D memory.

Scaling makes monolithic 3D IC practical

Mon, 10 Oct 2013
In the 1960s, James Early of Bell Labs proposed three-dimensional structures as a natural evolution for integrated circuits. Since then many attempts have been made to develop such a technology.

Memory materials revolution highlighted at SMC

Wed, 10 Oct 2013
While the number of materials used in semiconductor logic will increase approximately 50 percent in the transition from 32nm to 22nm production, the materials revolution in memory will be even more pronounced, challenging developers, manufacturers, equipment, and materials suppliers, according to experts speaking at the SEMI Strategic Materials Conference 2013, held in Santa Clara on October 16-17.

EU project to industrialize world record high-density capacitors

Wed, 10 Oct 2013
CEA-Leti, Fraunhofer IPMS-CNT and three European companies have launched a two-year project to industrialize 3D integrated capacitors with world-record density using atomic layer deposition.

Silicon interposers, CoWoS and microbumps

Wed, 10 Oct 2013
At the recent ECTC conference, various presentations addressed silicon interposers for 2.5D (Shinko), CoWoS reliability (TSMC) and microbumping (imec).

Three-dimensional atomic force microscopy

Wed, 10 Oct 2013
3D atomic force microscopes can measure critical dimensions, line edge roughness and sidewall roughness in a way that is highly accurate, non-destructive and cost-effective.

Are we using Moore's name in vain?

Tue, 11 Nov 2013
Clearly Moore's law is about cost, and Gordon Moore’s observation was that the optimum number of components (nowadays - transistors) to achieve minimum cost will double every year.

SUSS MicroTec installs excimer laser stepper at Fraunhofer IZM Berlin

Wed, 11 Nov 2013
SUSS MicroTec has successfully installed an ELP300 excimer laser stepper to support next generation advanced packaging and 3D IC laser debonding applications at the Fraunhofer Institute for Reliability and Microintegration (IZM), Berlin.

GLOBALFOUNDRIES demonstrates model for next-generation chip packaging technologies

Thu, 11 Nov 2013
Foundry 2.0 partnership with Open-Silicon and Amkor Technology yields successful 2.5D test vehicle project.

Can Intel beat TSMC?

Mon, 11 Nov 2013
It would seem that if Intel could scale transistor cost as they have done in the last 40 years then they could win these super high volume consumer-oriented designs where cost is extremely important. And TSMC is clearly taking this seriously.

Semiconductor industry leaders to examine the future of 3D NAND at Dec 10 event

Mon, 12 Dec 2013
Manufacturing 3D NAND designs requires overcoming formidable technical challenges to create extremely complex high-aspect-ratio structures.

Sankalp Semiconductor appoints Dan Clein into its management team

Tue, 12 Dec 2013
Sankalp Semiconductor Private Limited, a leading Analog Mixed-Signal services and solutions company from India, announced today the appointment of Mr. Dan Clein into its management team. Dan will be based out of the North America region.

Micron Technology appoints Rajan Rajgopal as VP of Quality

Wed, 12 Dec 2013
Micron Technology, Inc. today announced that the company has named Rajan Rajgopal, vice president of Quality.

Worldwide semiconductor revenue grew 5.2 percent in 2013

Wed, 12 Dec 2013
Worldwide semiconductor revenue totaled $315.4 billion in 2013, a 5.2 percent increase from 2012 revenue of $299.9 billion, according to preliminary results by Gartner, Inc.

CEA-Leti signs agreement with Qualcomm to assess sequential 3D technology

Mon, 12 Dec 2013
CEA-Leti today announced an agreement with Qualcomm Technologies, Inc., a subsidiary of Qualcomm Incorporated, to assess the feasibility and the value of Leti’s sequential 3D technology.

Micron's high-density 45nm serial NOR Flash doubles programming speed for embedded applications

Tue, 12 Dec 2013
Micron Technology, Inc. today announced the availability of 45nm Serial NOR Flash memory samples in 512Mb, 1Gb, and 2Gb densities with a standard SPI interface.

AMD and Hynix announce joint development of HBM memory stacks

Mon, 12 Dec 2013
3DIC memory, and therefore all of 2.5/3D technology, took one step closer to full commercialization last week with the HBM joint development announcement from AMD and Hynix at the RTI 3D ASIP meeting in Burlingame CA.

Micron revenue surges after Elpida deal officially closes

Mon, 12 Dec 2013
Micron Technology surged 130 percent in revenue during the third quarter as it finally closed its acquisition of bankrupt Elpida Memory of Japan, a vigorous ascent that also propelled the total market for dynamic random access memory (DRAM) to its best performance yet in 11 quarters.

Substrate impact on 2.5/3D IC costs

Thu, 1 Jan 2014
At the recent Georgia Tech Global Interposer Technology (GIT) Workshop in Atlanta, the pervasive theme appeared to be whether a change in substrate is required to lower overall costs and help drive HVM (high volume manufacturing) applications.

Imec, AlixPartners to develop model for lowering costs of advanced semiconductor tech

Mon, 1 Jan 2014
Patterning options for N10/N7 nodes, advanced packaging solutions and 3D NAND memory to be targeted.

A bilayer temporary bonding solution for 3D-IC TSV fabrication

Thu, 1 Jan 2014
New technology eliminates the need for specialized equipment for wafer pre- or post-treatment.

Imec celebrates 30 years

Tue, 1 Jan 2014
Nanotechnology research and development center imec, today announced the celebration of its 30th anniversary.

Xilinx and University of Florida honored with SEMI Award for advancements in interposers and CMOS fab process

Wed, 1 Jan 2014
SEMI today announced that two teams — from the University of Florida and Xilinx — are recipients of the 2013 SEMI Award for North America.

3DIC market to reach $7.52B by 2019

Thu, 1 Jan 2014
The market for 3DICs globally is forecast to reach USD 7.52 billion by 2019, according to a new market report published by transparency market research.

Intel vs. TSMC: An Update

Tue, 1 Jan 2014
On January 14, 2014, we read on the Investors.com headlines page - Intel Seen Gaining Huge Pricing Advantage Over TSMC. Just three days later comes the responding headline: TSMC: We're "Far Superior" to Intel and Samsung as a Partner Fab.

Besi and Imec collaborate on thermocompression technology

Tue, 1 Jan 2014
Today, at the SEMI European 3D TSV Summit, nanoelectronics research center imec and Besi, a global equipment supplier for the semiconductor and electronics industries, announced they are joining forces to develop a thermocompression bonding solution for narrow-pitch die-to-die and die-to-wafer bonding with high accuracy and high throughput.

Natural 3D counterpart to graphene discovered

Tue, 1 Jan 2014
The discovery of what is essentially a 3D version of graphene promises exciting new things to come for the high-tech industry, including much faster transistors and far more compact hard drives.

Challenges and innovations on front-end and 3D TSV

Thu, 1 Jan 2013
Looking at 2014, we see challenges and innovations in both the front-end semiconductor and 3D TSV markets.

2014 Outlook: An era of unprecedented change

Fri, 1 Jan 2014
We asked leading industry experts and analysts to give us their perspectives on what we can expect in 2014.

Paradigm shift: Semi equipment tells the future

Mon, 1 Jan 2014
Looking at the semi-equipment booking should be the first step in any attempt to assess future semiconductor trends.

The 2014 European 2.5/3DIC Summit

Thu, 2 Feb 2014
SEMI’s second annual European 3D TSV Summit was held in Grenoble in late January. Three hundred and twenty attendees met to discuss the status of 2.5/3DIC and other advanced packaging technologies.

EV Group unveils high-volume manufacturing photoresist processing system

Tue, 2 Feb 2014
EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today unveiled its most advanced 300-mm photoresist processing system for logic and memory high-volume manufacturing.

SMIC and JCET establish joint venture for 12 inch bumping and testing

Fri, 2 Feb 2014
Semiconductor Manufacturing International Corporation, China's largest and most advanced semiconductor foundry, and Jiangsu Changjiang Electronics Technology Co., Ltd., the largest packaging service provider in China, jointly announced today a joint venture for 12" bumping and related testing.

North American semiconductor equipment industry posts January 2014 book-to-bill ratio of 1.04

Fri, 2 Feb 2014
A book-to-bill of 1.04 means that $104 worth of orders were received for every $100 of product billed for the month.

Plug-and-play test strategy for 3D ICs

Tue, 3 Mar 2014
Three-dimensional (3D) ICs, chips assembled from multiple vertically stacked die, are coming. They offer better performance, reduced power, and improved yield.

Highlights from the IMAPS Device Packaging Conference

Mon, 3 Mar 2014
The annual IMAPS Device Packaging Conference in Ft McDowell AZ is always a source for the latest packaging information.