Materials experts from across the supply chain gathered at the 2012 Strategic Materials Conference 2012 in San Jose in October, discussing key materials needs for micromanufacturing outside the CMOS mainstream: OLEDs and GaN-on-silicon power semiconductors, graphene, CNTs, and self-assembling polymers.
In the fifth installment in a series called Process Watch, the authors discuss the need for proper reticle cleaning and inspection. Authored by experts at KLA-Tencor, Process Watch articles focus on novel process control solutions.
At SEMICON Europa, European government representatives, consortia, and suppliers discussed programs to support and participate in the 450mm wafer-size transition -- including a comprehensive presentation from ASML about its roadmap for 450mm EUV platforms.
In the seventh installment in a series called Process Watch, the authors discuss cycle time and the impact of inspection. Authored by experts at KLA-Tencor, Process Watch articles focus on novel process control solutions.
In news from Semicon Japan, a Nikon spokesperson said that the company plans to ship high-volume manufacturing (HVM) lithography tools in 2017, and Intel officially announced a 450mm Japan Metrology Center.
In the sixth installment in a series called Process Watch, the authors discuss the ins and outs of parametric correlation when using measurements based on reflectometry, ellipsometry, or a combination of the two. Authored by experts at KLA-Tencor, Process Watch articles focus on novel process control solutions.
In the third installment in a series called Process Watch, the authors discuss some of the challenges of 450mm wafers. Authored by experts at KLA-Tencor, Process Watch articles focus on novel process control solutions.
In this first installment of a series called "Process Watch,” experts from KLA-Tencor explain why a defect might be classified as “Not Found” or “SEM Non-visual (SNV),” and how a SNV count can disguise or hide real problems.
In the second installment in a series called Process Watch, the author provides tips on how to make sure you’re reviewing the yield killing defects and not wasting time reviewing nuisance events. Authored by experts at KLA-Tencor, Process Watch articles focus on novel process control solutions for chip manufacturing at the leading edge.
While various industry segments appear to be tapping the brakes, others are revving their engines, observes SEMI's Christian Gregor Dieseldorff -- and a 2012 stall could pave the way for a record-breaking 2013.
In this SEMI News and Views blog, Karen Savala covers EUV lithography, 450mm wafers, and 3D IC developments, based on her recent presentation at SEMICON West, “Supply Chain Readiness in an Era of Accelerated Change.”
Learn about the changes in semiconductor manufacturing as well as related markets -- photovoltaics, displays, LEDs, etc -- at the 2012 Strategic Materials Conference (SMC), to be held on October 23-24 in San Jose, CA. SEMI reports.
Even though semiconductor manufacturers in Japan are consolidating and transitioning to a "fab-lite" strategy, the region still represents a large installed fab capacity and a major market for equipment and materials suppliers.
In the fourth installment in a series called Process Watch, the authors discuss overlay registration and new capabilities to align to buried layers. Authored by experts at KLA-Tencor, Process Watch articles focus on novel process control solutions.
During sessions at this month's SEMICON Taiwan, execs from TEL, Lam Research, Applied Materials and KLA-Tencor revealed the latest developments in 450mm technology.
The 2013 SPIE Advanced Lithography EUVL Conference started with many of us looking forward to Sam Sivakumar's kickoff presentation on results from Intel’s EUVL pilot line.
Dr. Vivek Bakshi blogs about EUV Lithography (EUVL) and related topics of interest. He has edited two books on EUVL and is an internationally recognized expert on EUV Source Technology and EUV Lithography. He consults, writes, teaches and organizes EUVL related workshops. WWW.euvlitho.com
I am frequently asked by my consulting clients and colleagues when EUV sources will be ready to support high volume manufacturing (HVM) of semiconductors. It is a difficult question to answer, partly because readiness metrics have been a moving target, or the latest performance data is not very clear. For example, how many wafers per hour will make it cost-effective to adopt EUVL over the alternatives of triple or quadruple 193 nm immersion lithography for a given product at a specified feature size for 300 mm or 450 mm wafers? Is the latest data in pulse mode and integrated, and for how long an operation?
The 2012 Source Workshop was held Oct. 8-11 in Dublin, Ireland, in the Clinton Auditorium on the campus of University College Dublin. This is the industry's largest annual gathering of EUV and soft X-ray source experts, who took the opportunity to discuss the latest results from their labs.
After a functional A-sample prototype is built, it doesn't take long for a project to gain traction that has market pull. This is usually the point that a project becomes highly visible within a company and it enters the Technology Development Process (TDP).
Tim Turner, the Reliability Center Business Development Manager at the College of Nanoscale Science and Engineering (CNSE), Albany, NY, blogs about the potential of resistive memory and the reliability challenges the must be overcome.
In the second article of the MEMS new product development blog, the importance of the first prototype will be discussed.
Dr. Steffen Schulz discusses the role of a flexible platform for computational lithography in a successful business strategy.
In David DiPaola's blog, he discuss the critical factors needed for success in the early stage of new MEMS product development.
Is it time for high-brightness LED manufacturing to get serious about process control? If so, what lessons can be learned from traditional, silicon-based integrated circuit manufacturing?
Several innovations in computational lithography have been developed in order to squeeze every possible process margin out of the lithography/patterning process. In this blog, Gandharv Bhatara of Mentor Graphicsl talks about two specific advances that are currently in deployment at 20nm.
A particle as small as three microns in diameter, attached to the back side of the wafer—the dark side, if you will—can cause yield-limiting defects on the front side of the wafer during patterning of a critical layer.
Joe Kwan is the Product Marketing Manager for Calibre LFD and DFM Services at Mentor Graphics. He is also responsible for the management of Mentor’s Foundry Programs. He previously worked at VLSI Technology, COMPASS Design Automation, and Virtual Silicon. Joe received a BA in Computer Science from the University of California Berkeley and an MS in Electrical Engineering from Stanford University.
In the third article of the MEMS new product development blog, critical design and process steps that lead to successful prototypes will be discussed.
In order to bring EUVL scanners into high volume manufacturing (HVM) of computer chips, its throughput of 10 wafers per hour (WPH) needs to increase. That brings up three questions: how much do we need to increase the current throughput for HVM insertion, what needs to be done to increase throughput, and how quickly can this increase be achieved?
The fourth article of the MEMS new product development blog is Part 2 of the critical design and process steps that lead to successful prototypes. In the last article, the discussion focused on definition of the customer specification, product research, a solid model and engineering analysis to validate the design direction. The continuation of this article reviews tolerance stacks, DFMEA, manufacturing assessment and process mapping.
Steve Shen of Digitimes reports that TSMC is expected to tape out Apple's A7 processor on a 20nm process in March and then “...move the chip into risk production in May-June, which will pave the way for commercial shipments in the first quarter of 2014… TSMC will utilize 14-fab to manufacture the A7 chips for Apple.”
The long-expected demise of optical lithography for manufacturing ICs has been delayed again, even though the technology itself has reached a plateau with a numerical aperture of 1.35 and an exposure wavelength of 193nm. Immersion lithography is planned for the 20/22nm node, and with the continued delay of EUV, is now the plan of record for 14nm.
Who knew that mask process correction (MPC) would again become necessary for the manufacturing of deep ultraviolet (DUV) photomasks?
Product validation is an essential part of all successful MEMS new product developments. It is the process of testing products under various environmental, mechanical or electrical conditions to simulate life in an accelerated manner.