The 2013 SPIE Advanced Lithography EUVL Conference started with many of us looking forward to Sam Sivakumar's kickoff presentation on results from Intel’s EUVL pilot line.
Dr. Vivek Bakshi blogs about EUV Lithography (EUVL) and related topics of interest. He has edited two books on EUVL and is an internationally recognized expert on EUV Source Technology and EUV Lithography. He consults, writes, teaches and organizes EUVL related workshops. WWW.euvlitho.com
I am frequently asked by my consulting clients and colleagues when EUV sources will be ready to support high volume manufacturing (HVM) of semiconductors. It is a difficult question to answer, partly because readiness metrics have been a moving target, or the latest performance data is not very clear. For example, how many wafers per hour will make it cost-effective to adopt EUVL over the alternatives of triple or quadruple 193 nm immersion lithography for a given product at a specified feature size for 300 mm or 450 mm wafers? Is the latest data in pulse mode and integrated, and for how long an operation?
The 2012 Source Workshop was held Oct. 8-11 in Dublin, Ireland, in the Clinton Auditorium on the campus of University College Dublin. This is the industry's largest annual gathering of EUV and soft X-ray source experts, who took the opportunity to discuss the latest results from their labs.
In order to bring EUVL scanners into high volume manufacturing (HVM) of computer chips, its throughput of 10 wafers per hour (WPH) needs to increase. That brings up three questions: how much do we need to increase the current throughput for HVM insertion, what needs to be done to increase throughput, and how quickly can this increase be achieved?