Lithography

Topic Index

A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 0-9


Board-level Reliability Design

Sun, 6 Jun 2003
A chip scale package (CSP) is defined as any IC package with an area less than 1.5x in die area, a package width less than 1.2x in die width, or any fine-pitch (0.5 mm or less) area-array package.

Verdant Names Advisory Board

Mon, 8 Aug 2007
(August 13, 2007) SUNNYVALE, CA — Verdant Electronics named more than 15 members from packaging, interconnect, PCB, and related industries to its board of advisors, including Happy Holden, Werner Engelmaier, and others. These contributors helped frame the Occam package-first assembly method Verdant introduced, and will bring the process from concept to development, said Joe Fjelstad, president, Verdant.

Micro-tech R&D Facility Installs EVG Mask Aligner

Mon, 6 Jun 2007
(June 1, 2007) ST. FLORIAN, Austria and LYNGBY, Denmark — EV Group (St. Florian) installed an EVG620 precision mask and bond aligner system at repeat-customer Danish Advanced Nanotech Center for Highly Integrated Production (DANCHIP) facilities at the Technical University of Denmark (DTU — Lyngby). The machine will be used for research, education, prototyping, and small-scale production of micro- and nanotechnology.

Austrian Semiconductor Manufacturer Installs Fouth EVG Aligner

Thu, 10 Oct 2007
(October 9, 2007) ST. FLORIAN, AUSTRIA — EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology, and semiconductor markets, announced the installation of its fourth IQ Aligner System for packaging applications at a major semiconductor manufacturing facility in Austria. This purchase reportedly strengthens the customer's capacity for wafer-level packaging of MEMS and display devices.

Nano Micro Facility Installs Vistec VB6

Wed, 8 Aug 2007
(August 22, 2007) WATERVLIET, NY — The Forschungszentrum Karlsruhe independent science and research institute (Germany) began running applications on a Vistec VB6 electron beam lithography system in its Karlsruhe Nano Micro Facility. The system will allow researchers to develop new applications in nanotechnology and microsystems technologies.

JMD Launches 3D Via Processes

Wed, 8 Aug 2007
(August 22, 2007) ATLANTA — Jacket Micro Devices (JMD) patented a fabrication method for 3D, all-organic interconnect structures that uses high- and low-temperature single-sided liquid crystal polymer (LCP) structures. The technique is based on JMD's multi-layer organic (MLO) packaging portfolio.

EV Group Reports Continued Growth

Thu, 11 Nov 2008
(November 20, 2008) ST. FLORIAN, Austria,— Crediting the continued demand in the 3D interconnect interconnect/through-silicon via (TSV) an nanoimprint lithography markets, EV Group reports an increase in revenue for 2008 of more than 15%. Despite the current global economic slowdown, the company says it remains cautiously optimistic about its outlook for 2009 given the expected growth opportunities to ensue as these novel technologies gain market acceptance/penetration.

Replisaurus Unveils "Middle-end-of-Line" Metallization Technology

Tue, 6 Jun 2008
(June 10, 2008) KISTA, Sweden and ST. JEOIRE, France — Just because Replisaurus, Inc. has maintained a low profile since announcing their first round of funding in August 2006, it doesn't mean there hasn't been a lot going on for the start-up company. In fact, just the opposite is true. With last week's announcement of the company's acquisition of Smart Equipment Technologies (SET), the company is ready show the world what it's been up to.

Replisaurus Acquires S.E.T.

Thu, 6 Jun 2008
(June 5, 2008) Kista, SWEDEN— Replisaurus Technologies, Inc., pioneer in nanoscale electrodeposition of metal patterns, has acquired S.E.T. SAS to establish a production site for its integrated and fully automated high-volume manufacturing tools for its proprietary ElectroChemical Pattern Replication (ECPR) technology.

Mask Aligner for 3D Packaging

Tue, 7 Jul 2008
The second-generation SUSS MA300, from SUSS MicroTec is a highly automated mask aligner platform for 300-mm and 200-mm wafers. Specifically designed for 3D packaging, it features a dedicated alignment kit for creating 3D interconnects for applications like chip stacking and 3D image sensor packaging. It also targets wafer bumping and wafer level packaging (WLP) applications, but can be used for other technologies where geometries in the range of 5 and 100 µm must be exposed.

Nanoimprint Toolkit for Mask Aligners

Tue, 10 Oct 2008
SUSS MicroTec now offers a nanoimprint toolkit that reportedly enhances the capabilities of its manual mask aligners by enabling them to pattern large areas with repeatable sub-50nm printing capability. The technology, substrate conformal imprint lithography (SCIL)was developed by Philips Research, (Eindhoven/The Netherlands) and transferred to SUSS MicroTec in a technology license agreement.

EMC3D Consortium Achieves Cost Goal for TSV

Mon, 9 Sep 2008
(September 8, 2008) SANTA CLARA, CA — 2 years ago, the EMC3D Consortium, open consortia of equipment and materials manufacturers, established itself and set out to develop a process flow and cost model for 3D integration. Focusing on via-first TSVs as the method of interconnect, the intention was to find a solution to achieving this for $200/wafer cost of ownership (CoO) on a 3-year timeline. It appears, however, that they've beaten their own goal ahead of schedule.

Compugraphics expanding photomask sizes for WLP

Fri, 8 Aug 2011

Compugraphics International is widening its line of photomasks to include larger-area products up to 16 in2, responding to customer demand for wafer-level packaging and other semiconductor and optical applications.


Nanometrics WLP bonding metrology tool launches with logic order

Thu, 2 Feb 2011

The Unifire 7900IR provides 3D inspection of wafer-scale packaging features as well as registration for wafer-to-wafer bonding applications for use in advanced wafer scale packaging process control.


300mm bonder will demo chip to wafer direct metallic bonding tech developed at Leti

Tue, 2 Feb 2011

CEA-Leti, in a multi-partner project with SET, STMicroelectronics, ALES and CNRS-CEMES, will demonstrate high-alignment-accuracy chip-to-wafer structures made by direct metallic bonding. Such structures are required for high-performance 3D ICs, and possibly microelectronics, optoelectronics, or MEMS.


Advantest to expand beyond semiconductor test

Thu, 1 Jan 2012

Haruo Matsuno, president and CEO of Advantest Corporation (TSE:6857, NYSE:ATE) shares the company's major goals, including expansion into new measurement applications, utilization of cloud computing, and more.


3D integration comes in many flavors for semiconductor industry, says CEA Leti chief scientist

Wed, 2 Feb 2011

All the major semiconductor players are embracing 3D integration, says Simon Deleonibus. The CEA-Leti scientist and IEEE Fellow wants to see TSV mature and new technologies develop based on wafer bonding. He speaks with Debra Vogler.


Ushio 200mm litho tool suits 3D packaging steps

Wed, 9 Sep 2011

Ushio Inc. debuted a 200mm wafer full-field projection lithography tool UX4-3Di FFPL 200 for high-volume manufacturing of advanced LSI devices incorporating 3D integration technologies, such as TSVs and silicon interposers and bumps.


CEA Leti deploys EVG's litho, packaging tools for 300mm line

Tue, 4 Apr 2011

CEA-Leti has installed multiple EVG tools in its 300-mm cleanroom dedicated to R&D and prototyping for 3D integration applications. EVG's equipment will be used in 3D technology demonstrations for Leti's global customer base, as well as low-volume pilot production on 300mm wafers.


LORD underfill encapsulant designed for lower cost

Wed, 6 Jun 2011

LORD ME-555 LORD Corporation launched the ME-555 underfill encapsulant for semiconductor packaging and assembly. LORD ME-555 is a high-purity, semiconductor-grade epoxy underfill for encapsulating flip chips.


STATS ChipPAC widens fan-out WLP configurations with TSVs, IPDs

Tue, 5 May 2011

STATS ChipPAC says integrating through-silicon vias with passive devices and its eWLB technology addresses complex design issues, shrinking lithography nodes, and increased performance demands for mobile and consumer applications.


IBM-fine-pitch-substrate-bumping-skips-solder-paste-beyond-C4NP

Tue, 11 Nov 2010

IBM IMS process for substrate bumpingJae-Woong Nah, researcher at IBM's Thomas J. Watson Research Center, briefed ElectroIQ on his IMAPS conference paper: "Mask and mask-less injection molded solder (IMS) technology for fine-pitch substrate bumping." IMS is a variation of C4NP for solder deposition on fine-pitch laminates. Nah explains how the researchers injected 100% pure molten solder instead of solder paste with a reusable film mask for forming high-volume solder on fine-pitch substrates.


Double layer stencil debuts from Dek

Tue, 2 Feb 2010

The VectorGuard stencil portfolio from DEK now includes the double layer Platinum stencil, a stencil technology that is said to offer performance benefits over conventional screens. VectorGuard Double Layer Platinum stencils suit semiconductor applications and component manufacture, solar cell manufacture, low-temperature co-fired ceramic (LTCC) manufacture, as well as other production challenges requiring fine line or mixed feature sizes.


SMTA webcasts on package on package (PoP), STACK assembly, rework, and inspection

Fri, 1 Jan 2010

The Surface Mount Technology Association (SMTA) will host two 90-minute online sessions with Bob Willis, ASKbobwillis.com, on package-on-package (PoP) applications and implementation. The Webtorials will take place February 4 and February 11, 2010 from 1:00 to 2:30 pm EST.


2.5/3D interposers fabbed at 30% lower COO with USHIO

Mon, 7 Jul 2012

USHIO Inc. is introducing the large-field stepper lithography tool

Replisaurus advanced Cu metallization process nears commercialization at Leti

Fri, 7 Jul 2011

CEA-Leti and Replisaurus Technologies will begin applying Replisaurus' ElectroChemical Pattern Replication (ECPR) metallization process to customer target products, following a near-100% yield master.


Canon enters back-end packaging market with lithography tool debut

Fri, 7 Jul 2011

Canon Inc. made its first foray into the semiconductor back-end packaging equipment market with the new FPA-5510iV for through silicon via (TSV) and bump lithography.


NCCAVS on 3D packaging: Bring on the TSVs

Mon, 6 Jun 2011

A standing-room crowd gathered at SEMI for a special NCCAVS usergroup meeting to hear about issues relevant to 3D packaging, including CMP for through-silicon vias (TSV), a DFM methodology for 3D TSV packaging designs, and TSV process integration challenges.


Micronic Laser Systems Moves to Acquire MYDATA

Tue, 4 Apr 2009
(April 21, 2009) TÄBY, Sweden — Micronic Laser Systems AB intends to acquire MYDATA automation AB. In the proposed transaction, Micronic would acquire MYDATA from Skanditek Industriförvaltning and the minority shareholders against payment in the form of newly issued shares in Micronic. Combining Micronic and MYDATA will create large potential within the market for electronic packaging using Micronic's and MYDATA's complementary imaging and deposition technologies.

Suss MicroTec banks on ATM in its new 3D probe station

Mon, 9 Sep 2009

Süss MicroTec's Stojan Kanev tells SST/AP about the company's new addition to its toolset for 3D integration: a probe station targeting 300mm wafer-level 3D stacked structures.


IBM Advances DNA "Origami" Structures

Wed, 8 Aug 2009
August 19 -- IBM researchers and collaborator Paul W.K. Rothemund, of the California Institute of Technology (CalTech), have made an advancement in combining lithographic patterning with self assembly

Nature Nanotechnology: DNA Shapes on Lithographically Patterned Surfaces Increase Semiconductor Density

Mon, 8 Aug 2009
Scientists at IBM Research and the California Institute of Technology announced a method for structuring DNA shapes to help build miniaturized computer chips well beyond 22-nm processes. The research claims that chips will be more energy efficient and suited to mass production.

IGI releases WYSIWYG phototool editing, definition, viewing, and ordering product

Wed, 6 Jun 2010

Infinite Graphics Incorporated (IGI) debuted the IGI Phototooling Toolbox for niche applications with specialized requirements not addressed by traditional mainstream PCB and IC products.


New Products

Wed, 11 Nov 2000
The NXR-1510 is a new full-featured, automatic X-ray inspection and quality assurance test system

Cleaning with Aqueous TMAH: An Environmentally Friendly Alternative

Sun, 4 Apr 2007
Conductive paste screening on green sheet through a mask is a common technique to delineate desired circuitry for ceramic modules.

Software-driven wirebonding

Tue, 8 Aug 2000
New design tools promise to relieve setup bottlenecks by automating the documentation and validation work

In the News

Mon, 5 May 2000
Capitalizing on advanced intellectual property (IP) delivery and rapid silicon prototyping tools (two of the major dividends that resulted from its recent acquisition of VLSI Technology), Philips Semiconductors has launched a design methodology that will allow the vast pool of IP to be used quickly and effectively.

Ultratech brings former member back to Board

Thu, 4 Apr 2012

Ultratech, lithography and laser-processing system supplier to semiconductor manufacturers and packaging providers, added Michael C. Child to its Board of Directors. Child served on Ultratech

SUSS buys Tamarack for lithography, laser structuring lines

Fri, 3 Mar 2012

SUSS MicroTec has acquired Tamarack Scientific Co. Inc. in a share purchase of $9.34 million. Tamarack makes UV projection lithography tools and laser micro-structuring systems.


SEMICON West heralds 22nm, EUVL, 450mm, mobile electronics speakers

Mon, 4 Apr 2012

Intel, SEMATECH, and other top chip makers, suppliers, and research organizations will send speakers to SEMICON West, July 10-12 in San Francisco. The event will single out new transistor architectures, advanced lithography, 450mm wafers, and other major developments.


EVG wins repeat order from wafer-level camera maker

Tue, 3 Mar 2012

Himax Technologies placed a repeat order for an IQ Aligner UV nanoimprint lithography (UV-NIL) system from EVG.


ARM’s Segars sees changing requirements for electronics driven by mobile

Mon, 3 Mar 2012

At the recent Common Platform Technology Forum -- produced by Global Foundries, Samsung and IBM -- Simon Segars, executive vice president and general manager of the physical IP division at ARM, spoke about the impact of the internet of things and mobile computing on the way electronics are designed and used.


2011 ITRS: DRAM, 3D Flash, MEMS, nano scaling steal the show

Wed, 2 Feb 2012

The 2011 International Technology Roadmap for Semiconductors (ITRS) has been publicly released. Several areas of advancement are highlighted in the 2011 ITRS: DRAM and Flash memory, and MEMS.


Semiconductors to use most ultrapure water in 2012

Tue, 2 Feb 2012

The electronics industry will edge out coal-fired boilers as the biggest purchaser of ultrapure water systems and consumables in 2012, according to the McIlvaine report: Ultrapure Water World Markets.


EVG LED mask aligner offers COO improvement in gen-2

Tue, 2 Feb 2012

EVG uncrated the EVG620HBL Gen II fully automated mask alignment system for volume LED manufacturing. The second generation tool offers 55% higher wafer output per square meter of cleanroom space occupied, EVG reports.


Silicon wafer revenues increased, shipments tapered in 2011

Tue, 2 Feb 2012

Worldwide silicon wafer revenues improved 2% YOY, shows the SEMI Silicon Manufacturers Group. Worldwide silicon wafer area shipments, however, decreased 3%, indicating a loss of momentum in H2 2011, said Kazuyo Heinink, SEMI SMG.


Gigaphoton launches ArF excimer laser for multi-patterning immersion lithography

Mon, 2 Feb 2012

Gigaphoton uncrated the GT63A next-generation ArF excimer laser for multi-patterning immersion lithography scanners.


Tackling EUV lithography shadow distortions with OPC

Thu, 2 Feb 2012

James Word and Christian Zunia, Mentor Graphics, explore the current capabilities of model-based OPC software to model and correct for the shadowing distortions unique to extreme ultra-violet lithography (EUVL).


AMAT loses top spot in VLSIresearch semiconductor equipment supplier rankings

Fri, 3 Mar 2012

VLSIresearch released its 2011 Top Semiconductor Equipment suppliers rankings, noting important acquisitions and strong spending in lithography tools in 2011. Semiconductor equipment spending was driven by aggressive capacity expansion in the foundry and logic sectors.


Samsung, IBM and GlobalFoundries look to the future: A report from the Common Platform Technology Forum

Thu, 3 Mar 2012

Execs from Samsung, IBM, GlobalFoundries and ARM looked to the future at The Common Technology Platform Forum in Santa Clara. They focused on the innovation pipeline for 20nm and 14nm technology nodes, and the role that EUV, FinFETs, TSVs, CNTs and DSA will play.


Semiconductor manufacturing equipment sales rose 9% in 2011

Tue, 3 Mar 2012

Worldwide sales of semiconductor manufacturing equipment totaled $43.53 billion in 2011, representing a year-over-year increase of 9%, shows SEMI. North America surpassed Taiwan as the region with the highest amount of spending.


Semiconductor wafer fab equipment trends

Tue, 4 Apr 2012

Barclays Capital compiled its 2011 analysis of semiconductor wafer fab equipment (WFE) spending, with a look at the top players and underlying trends by process step.


Semiconductor wafer fab equipment trends: Lithography

Mon, 4 Apr 2012

Barclays Capital compiled its 2011 analysis of semiconductor wafer fab equipment spending, with a look at the top players and underlying trends by process step. Here, Barclays’ CJ Muse considers lithography’s current state and future.


Wafer fab equipment leaders in 2011 and expectations for 2012

Mon, 4 Apr 2012

Barclays Capital looks at wafer fab equipment trends in 2011, based on Gartner data. Top 5 takeaways? The top 5 vendors continue to gain market share, Intel is a key customer, segment-leading vendors strengthened their holds, intensity edged higher, and changes are in store in 2012.


EUV lithography optics on order at Zygo

Mon, 4 Apr 2012

The Optical Systems Division of Zygo Corporation recorded a $2+ million order from a major semiconductor manufacturer to produce EUV optics for advanced lithography.


Nanophotonics researchers install NanoInk patterning tool at Osaka U

Wed, 4 Apr 2012

Osaka University’s Photonics Advanced Research Center in Japan installed a NanoInk NanoFabrication Systems DPN 5000 System for patterning various materials with nanoscale accuracy and precision. Osaka University scientists will develop and fabricate nanoscale plasmonic and nanophotonics devices.


North American semiconductor equipment ends 2011 with another book-to-bill climb

Mon, 1 Jan 2012

North America-based manufacturers of semiconductor equipment posted $1.16 billion in orders in December 2011, $1.32 billion in billings, and a book-to-bill ratio of 0.88, according to SEMI. The book-to-bill ratio has been climbing since September 2011. In December, bookings climbed back above the $1 billion mark.


Mask writer collaboration announced: IMS Nanofabrication, DNP, Intel and Photronics

Mon, 1 Jan 2012

IMS Nanofabrication, Dai Nippon Printing Co., Ltd. (DNP), Intel Corporation, and Photronics Inc. are commencing a joint electron multi‐beam mask writer tool collaboration.


Intel, Samsung, TSMC semiconductor capex in 2012 signal market dominance

Mon, 1 Jan 2012

Intel plans $12.5 billion semiconductor capital expeditures in 2012; Samsung plans $12.2 billion. Watch for wide and growing separation between these two companies and their competition, says IC Insights.


Supramolecular researchers install NanoInk lithography system

Thu, 1 Jan 2012

Researchers at INCDTIM in Romania will use NanoInk's NanoFabrication Systems Division's DPN 5000 system for supramolecular structure fabrication, molecular recognition and self-assembling process applications.


ISS draws to a close with innovation on the mind

Wed, 1 Jan 2012

Michael A. Fury, Ph.D., Techcet Group, reports from SEMI’s International Semiconductor Strategy meeting, with a closing day focused on innovation and new applications.


Fabs in high-risk zones, 450mm, 3D IC themes of Semico's Semiconductor Fab Database

Wed, 1 Jan 2012

36% of semiconductor fabs are in high-risk zones, finds Semico, noting the industry disruptions caused by the Japan earthquake and tsunami and Thai flooding and the challenges these presented to chip makers in the regions. 


ISS day 2: Cloud computing to drive 450mm, closer collaboration

Wed, 1 Jan 2012

Day 2 of SEMI’s Industry Strategy Symposium (ISS) 2012 included talks by Mike Splinter of Applied Materials, Mark Thirsk of Linx Consulting, Tim Hendry of Intel, David Lazovsky of Intermolecular, a panel session on could computing run by Harvey Frye of TEL, Handel Jones of IBS and another panel session focused on 450mm, moderated by G. Dan Hutcheson of VLSI Research. Michael A. Fury of Techcet reports.


SPIE Advanced Lithography: Intel's, TSMC's tool roadmap takeaways

Wed, 2 Feb 2012

After attending SPIE Advanced Lithography, Barclays Capital came away with a lower lithography tool shipments forecast, more hope for EUV lithography, and expectations of a litho buying spree at Intel.


Brewer Science rolls out gen-2 OptiStack lithography patterning products

Tue, 2 Feb 2012

Brewer Science uncrated the next generation of its OptiStack system of patterning products for semiconductor manufacturing, targeting emerging and existing lithography processes.


TEL joins CEA-Leti's lithography program IMAGINE

Tue, 2 Feb 2012

Tokyo Electron Ltd. (TEL) will join research organization CEA-Leti's IMAGINE open, collaborative industrial program on advanced lithography for semiconductor manufacturing.


New RAVE division offers semiconductor makers custom lithography defect study

Mon, 2 Feb 2012

RAVE N.P. Inc. established a new division, Advanced Technical Instruments or ATI, comprising SEM, AFM, and other analysis tools, as well as custom semiconductor and photomask services such as haze generation systems.


Gigaphoton achieves EUV lithography milestone

Mon, 2 Feb 2012

Lithography light source maker Gigaphoton, Inc. achieved 7W of extreme ultra violet (EUV) power on its mass-production laser-produced plasma (LPP) light source, scheduled to be shipped in 2012.


Brewer Science, Pixelligent debut hardmask for advanced semiconductor lithography

Mon, 2 Feb 2012

Pixelligent and Brewer Science Inc. developed a spin-on hardmask technology for advanced lithography, combining nanocrystal and microelectronic coating technologies.


SPIE Advanced Lithography preview: eBeam Initiative roadmap

Mon, 2 Feb 2012

The eBeam Initiative, a forum for new IC manufacturing approaches based on electron beam (e-beam) lithography, will unveil its latest roadmap at the SPIE Advanced Lithography Symposium.


ASML's Brion combines OPC techniques for faster 2Xnm lithography mask tapeout

Mon, 2 Feb 2012

ASML's Brion Technologies debuted Tachyon Flexible Mask Optimization, which enables use of multiple OPC techniques in a single mask tapeout for 2Xnm lithography.


MAPPER Lithography tech resolves 22nm lines, spaces, contact holes in CEA-Leti work

Mon, 2 Feb 2012

CEA-Leti reports that the MAPPER Lithography massively parallel direct write technology resolves 22nm dense lines and spaces and 22nm dense contact holes in positive chemically amplified resist. The maskless lithography tech meets semiconductor requirements for 14nm and 10nm logic nodes.


imec achieves 300mm wafer-fab-compatible directed self assembly

Fri, 2 Feb 2012

imec successfully implemented a 300mm directed self-assembly (DSA) semiconductor manufacturing process line in its fab, with TEL equipment, AZ Electronic Materials consummables, and research from the University of Wisconsin.


ISS kicks off with IC industry reality talks

Tue, 1 Jan 2012

The Industry Strategy Symposium (ISS) kicked off today in Half Moon Bay, CA under blustery skies with choppy seas, an apt metaphor for the information about to be shared inside, says blogger Michael A. Fury, Techcet.


New installed wafer capacity leader: Taiwan took over in 2011

Mon, 1 Jan 2012

Taiwan became the region with the largest share of installed wafer capacity in 2011, according to IC Insights' Global Wafer Capacity 2011-12 report. This is the first time Taiwan has led the global wafer capacity rankings, with 21% of total in mid-2011.


Vistec installs first e-beam lithography EBPG5000pES in China

Mon, 1 Jan 2012

Wuhan National Laboratory for Optoelectronics at the Huazhong University of Science and Technology (Wuhan, China) has signed off its Vistec Lithography electron-beam lithography system Vistec EBPG5000pES.


Semiconductor inventory correction balancing out early in 2012

Thu, 1 Jan 2012

Semiconductor sales were weaker than expected in Q3 2011, and Q4 shows weak guidance, prompting chip makers to reduce production. Gartner expects this inventory correction to work out in early 2012.


SEMI names Stanley Myers a director emeritus

Wed, 1 Jan 2012

Former SEMI president and CEO Stanley T. Myers was named a director emeritus of the association by itsl Board of Directors. Myers led SEMI for 15 years, was a board member for 24, and has been part of the semiconductor industry for more than 50.


Semiconductor fab capex forecast for 2012

Tue, 1 Jan 2012

Key points from SEMI's 2012 semiconductor fab equipment spending forecast include a predicted decline of 11% to $35 billion, steady growth in 300mm installs, and an H1 dip/H2 surge format.


EVG integrates UV lithography from Eulitha on mask aligner

Tue, 1 Jan 2012

EV Group signed a joint-development and licensing agreement with Eulitha AG, integrating Eulitha's PHABLE mask-based UV photolithography technology with EVG's automated mask aligner platform.


20nm mask technology relies on SMO and DPT

Mon, 1 Jan 2012

20nm production will be done with 193nm ArF immersion lithography. The workhorse lithography technologies will be double-patterning, source mask optimization, or some combination of the two, says Franklin Kalk, Toppan Photomasks.


22nm node semiconductors: Technical forecasts

Tue, 1 Jan 2012

Solid State Technology asked top analysts and technologists to provide insights on the transition to 22nm semiconductor devices. Read through the whole 10-forecast series, or check out the individual articles as you have time to see perspectives on lithography, device architecture, and more.


Semiconductor industry revenue targets $323.2B in 2012

Tue, 1 Jan 2012

The global semiconductor market will see a slow 2012, reports IHS, with economic uncertainty and semiconductor inventory not moving enough to stimulate new production. Expect negative growth in Q1 2012, a nascent rebound in Q2, and strong growth in Q3 2012, IHS reports.


TI closes semiconductor fabs in TX and Japan

Fri, 1 Jan 2012

Texas Instruments (TI, NASDAQ:TXN) will close 2 older semiconductor manufacturing facilities in Hiji, Japan and Houston, TX over the course of the next 18 months. Production from these analog chip sites will be moved to more advanced TI facilities.


President Obama's Intel visit: Fab 42 update, American manufacturing themes

Fri, 1 Jan 2012

President Barack Obama visited the Intel Ocotillo campus in Chandler, AZ. The President spoke about Intel's technological innovation, and manufacturing jobs in America.


ABB intros Cleanroom ISO 5 version of multipurpose 6-axis robot

Thu, 1 Jan 2012

ABB Robotics introduced an ISO 5 (Class 100) Cleanroom version of the IRB 120, its smallest multipurpose 6-axis robot. Any source materials in the IRB 120 prone to particle generation were modified to eliminate contamination potential in the manufacturing area.


Vistec delivers electron-beam lithography system to ITME researchers in Poland

Thu, 4 Apr 2012

Vistec Electron Beam GmbH sold a Variable Shaped Beam system SB251 to the Institute of Electronic Materials Technology in Warsaw, Poland, for R&D on micro-optical and diffractive elements, new materials, and masks for optical lithography.


Major semiconductor makers order EUV lithography metrology tool from Carl Zeiss

Wed, 4 Apr 2012

Carl Zeiss won orders for its EUVL actinic aerial image metrology system, AIMS EUV, from 2 of the 4 members of SEMATECH’s EMI partnership. The tool allows chip makers to review defects in advanced masks needed for EUVL.


SEMATECH adds Inpria resists to EUV lithography work

Tue, 4 Apr 2012

Inpria, chemical materials supplier for thin-film deposition, joined the consortium SEMATECH’s Lithography Program. Inpria and SEMATECH will tackle on critical issues for resist in extreme ultraviolet (EUV) lithography.


Semiconductor subsystems see record revenues thanks to 32nm and below

Mon, 4 Apr 2012

Strong lithography spending, as well as several acquisitions and divestures in the space, brought changes to the critical subsystems of semiconductor/related markets sector, says VLSIresearch. 


North American semiconductor fab tool makers see March book-to-bill hike

Fri, 4 Apr 2012

With a book-to-bill ratio of 1.13, North America-based manufacturers of semiconductor equipment saw a sixth climb in the ratio, which has steadily improved since it hit 0.71 in September 2011, shows SEMI.


ASMC will focus on productivity and technology challenges

Wed, 4 Apr 2012

The 23rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2012) will be held May 15-17 in Saratoga Springs, New York. The conference will feature presentations of more than 85 peer-reviewed manuscripts covering critical process technologies and fab productivity. This year’s event features a panel discussion on “Competing for R&D Dollars,” moderated by Solid State Technology Editor-in-Chief Pete Singer.


Lithography tool buying increases on logic and chip foundry demand

Mon, 4 Apr 2012

Barclays Capital is raising its total lithography units forecast by more than 10 systems, from 234 to 251 in 2012. As many as 260 litho tools could be purchased, as foundries are seeing high demand for 28nm chips.


Electron-beam lithography breakthroughs at Photomask Japan

Mon, 4 Apr 2012

The eBeam Initiative will present at Photomask Japan (PMJ), through member companies, improved photomask critical dimension uniformity (CDU) and wafer yields thanks to eBeam technologies.


Entegris builds advanced filtration and contamination control R&D center for 2X, 1X semiconductor fab

Thu, 4 Apr 2012

Entegris (NASDAQ:ENTG), contamination control and handling system supplier to the semiconductor and microelectronics industries, will build the Entegris i2M Center for Advanced Materials Science in Bedford, MA, near its headquarters in Billerica. i2M denotes ideas to market.


Intel’s top suppliers in 2011

Thu, 4 Apr 2012

Intel Corporation announced its 2011 Intel Preferred Quality Supplier (PQS) awards, selecting 19 of its thousands of suppliers. Two suppliers received Intel’s Achievement Award.


Semiconductor industry expectations for 2012: Take the WWK survey

Fri, 2 Feb 2012

Wright Williams & Kelly, Inc. (WWK) opened its 2012 semiconductor industry survey on equipment and process timing. Only participants will receive the full results, free of charge.


49 semiconductor wafer fabs close 2009-2011

Wed, 2 Feb 2012

IC manufacturers closed 49 wafer fabs between 2009 and 2011, according to IC Insights. Smaller wafer fabs (≤200mm) suffered the most closures, and Japan and North America led the way.


President Obama speaks at Albany Nano-Tech Complex today

Tue, 5 May 2012

President Barack Obama toured the SUNY - Albany Nano-Tech Complex today, speaking about the economy and education in the CNSE NanoFab Extension Building.


Organic complementary logic aim of 2 European research projects

Fri, 5 May 2012

The Heterogeneous Technology Alliance in Europe is focusing on high-performance organic electronic circuits through 2 projects: COSMIC to develop p- and n-type OTFTs for complementary logic, and POLARIC for shrinking critical dimensions of OTFTs.


Gigaphoton opens Korean subsidiary for DUV, EUV lithography support

Wed, 5 May 2012

Gigaphoton Inc., lithography light source manufacturer, began operations at its wholly owned subsidiary, Gigaphoton Korea Inc. Gigaphoton points to Korea as “one of the most important regions in the global semiconductor industry.”


Semiconductor-grade flow sensor measures photoresist, solvent supply

Mon, 5 May 2012

SENSIRION introduced the SLQ-QT105 semiconductor-grade flow sensor for flow rates below 2cc/sec (120ml/min) of hydrocarbon-based liquids, such as photoresists and solvents.


Nanostructured polymer lithography platform established by CEA-Leti and Arkema

Fri, 5 May 2012

Arkema and CEA-Leti, with the help of Professor Hadziioannou’s team of LCPO, have successfully patterned a 20nm pitch and reduced the diameter of contacts down to 7nm with nanostructured polymers.


North American chip fab tool makers report 4th month of orders growth in January

Fri, 2 Feb 2012

North America-based manufacturers of semiconductor equipment posted $1.18 billion in orders, $1.24 billion in billings, and a book-to-bill of 0.95 in January 2012, according to SEMI.


450mm wafers at SEMI ISS Europe

Thu, 2 Feb 2012

SEMI’s International Strategy Symposium (ISS) meets for its Europe session February 26-28 in Munich, Germany. Following are some of the 450mm wafer presentations scheduled to take place.


SUSS brings GenISys lithography simulation software onto mask aligners

Tue, 2 Feb 2012

SUSS MicroTec will work with GenISys, provider of high-performance software solutions for nano scale fabrication, to combine the SUSS MicroTec mask aligner tools with the GenISys simulation software Layout LAB.


SPIE 2012: The Spring of EUVL

Mon, 2 Feb 2012

Dr. Vivek Bakshi, President of EUV Litho, Inc., reports on the SPIE Advanced Lithography conference. He says that this year even the loudest criticism of EUVL was not about “if” but “when,” and the predicted range of insertion for EUVL in high volume manufacturing (HVM) is now 2013-15.


GLOBALFOUNDRIES hires procurement exec to manage capex expansions

Wed, 2 Feb 2012

GLOBALFOUNDRIES appointed Magnus Matthiasson, formerly of Philips Lumileds, as chief procurement officer (CPO), reporting to CFO Dan Durn.


North American semiconductor tool makers see higher bookings in April

Wed, 5 May 2012

North America-based manufacturers of semiconductor fab equipment posted $1.60 billion in orders and $1.45 billion in billings in April 2012 for a book-to-bill ratio of 1.10, according to SEMI.


IRSC brings NanoProfessor nano-science education to southeastern US

Tue, 5 May 2012

Indian River State College in FL will be the first college in the southeastern US to offer students access to the instrumentation and curriculum provided by the NanoProfessor Nanoscience Education Program from NanoInk.


EUV lithography readiness: ConFab presentation preview

Mon, 5 May 2012

Stefan Wurm, director of lithography, SEMATECH will present “EUV Lithography Manufacturing Introduction: Infrastructure Readiness” in the session Technology Trends in Semiconductor Manufacturing at The ConFab 2012, June 3-6 in Las Vegas.


DOW opens semiconductor/display R&D center in Seoul with OLED focus

Thu, 3 Mar 2012

The Dow Chemical Company (NYSE: DOW) inaugurated its Dow Seoul Technology Center, a global R&D center with focus on technological advances in display and semiconductor applications.


Gigaphoton opens litho laser training center, regional HQ in OR

Thu, 3 Mar 2012

Lithography light source maker Gigaphoton Inc. opened its new U.S. Regional Headquarters and Training Center in Beaverton, OR.


Gudeng Precision designs EUV lithography pod with VICTREX material for low contamination

Thu, 3 Mar 2012

Gudeng Precision will use VICTREX PEEK-ESD 101 to make its first commercialized extreme ultraviolet (EUV) lithography pod. The material will help prevent contamination.


Semiconductor capex to fall 11.6% in 2012, says Gartner

Wed, 3 Mar 2012

Worldwide semiconductor manufacturing equipment spending is projected to total $38.9 billion in 2012, an 11.6% decline from 2011 spending of $44 billion, according to Gartner Inc.


CEA-Leti unveils wide-reaching silicon research scope

Wed, 5 May 2012

CEA-Leti has introduced the “LETI-3S” concept, for “Silicon Specialty Solutions.” The research is oriented to start-ups, component integrators, fabless or fablite chip companies, and equipment/consumable suppliers.


Become the Best of West at SEMICON West

Tue, 5 May 2012

Solid State Technology and SEMI will present the 2012 Best of West product awards at SEMICON West 2012, July 10-12 in San Francisco. Best of West recognizes important product and technology developments in the microelectronics industries.


Arkema enters microelectronics manufacturing research area with CEA

Tue, 5 May 2012

CEA will extend its collaboration with Arkema beyond photovoltaics into microelectronics and organic electronics, setting up two joint public-private research projects in CEA-Leti and CEA-Liten.


Photomask maker Photronics buys out Micron building

Wed, 3 Mar 2012

Photronics, Inc. (NASDAQ:PLAB) purchased its US nanoFab building from Micron Technology Inc., paying approximately $35 million. PLAB expects to save $5 million annually after the deal.


German semiconductor maker revamps DUV lithography steppers with Ventex

Wed, 3 Mar 2012

Ventex performed a major deep ultra violet (DUV) lithography stepper refurbishment and installation project for a tier-one chip manufacturer in Germany.


Semiconductor fab equipment spending to hit a record in 2013

Tue, 3 Mar 2012

Semiconductor fab equipment spending will remain flat in 2012, says SEMI. But look for a record spend from semiconductor makers in 2013, jumping from $38.85 billion spent in 2012 to $45 billion in 2013.


TSMC, Samsung foundries reconsidering 2012 capex on stronger 28nm demand

Mon, 3 Mar 2012

After only 2 months, semiconductor foundries are already considering raising their 2012 capex budgets, says Terence Whalen, Semiconductor Equipment analyst for North America at Citi.


EU partners clarify EUV optics improvements

Thu, 11 Nov 2012

A group of partners in Europe summarize results from their completed project to deliver the first EUV lithography optics, with progress in several optics components and in mask handling, cleaning, and repair.


Semi equipment demand still sinking

Mon, 10 Oct 2012

In case anyone needed a reminder or a wake-up, new data from SEMI reiterates chip tool sales are slumping badly in the latter part of this year.


Process Watch: A clean, well-lighted reticle

Fri, 10 Oct 2012

In the fifth installment in a series called Process Watch, the authors discuss the need for proper reticle cleaning and inspection. Authored by experts at KLA-Tencor, Process Watch articles focus on novel process control solutions.


European consortia, ASML, supplier network plan for 450mm transition

Thu, 10 Oct 2012

At SEMICON Europa, European government representatives, consortia, and suppliers discussed programs to support and participate in the 450mm wafer-size transition -- including a comprehensive presentation from ASML about its roadmap for 450mm EUV platforms.


ASML buying Cymer to push EUV litho development

Wed, 10 Oct 2012

Pulling Cymer's EUV source technology in-house is hoped to accelerate progress in the technology's long slow march toward production readiness.


Intel offers muted optimism in 3Q12 results, but cutting capex

Wed, 10 Oct 2012

Intel spoke of caution in end markets when discussing its 3Q12 results, but a big dip in capex and lack of 2013 visibility will likely cause concern in the semiconductor manufacturing ecosystem.


SEMI adds session, extends abstract deadline for China chip conference

Tue, 10 Oct 2012

SEMI has extended the deadline to submit proposed papers to next spring's China Semiconductor Technology International Conference 2013, and added a new symposium on circuit design, system integration, and application.


Process Watch: Cycle time’s paradoxical relationship to inspection

Tue, 12 Dec 2012

In the seventh installment in a series called Process Watch, the authors discuss cycle time and the impact of inspection. Authored by experts at KLA-Tencor, Process Watch articles focus on novel process control solutions.


IEDM 2012: Late papers on silicon photonics, large TFTs, III-V devices

Tue, 12 Dec 2012

With this week's IEEE International Electron Devices Meeting (IEDM 2012) now underway, here are four of the papers that were accepted late: on 90nm integrated silicon photonics, ZnNO for next-gen displays, and III-V TFETs for the 7nm node.


SEMI: Chip equipment slump extending into 2013, across-the-board rebound in 2014

Thu, 12 Dec 2012

Semiconductor equipment demand is persistently sluggish as the industry takes a break from a "multiyear expansion period" to digest recent investments and wrestle with a broader economic slowdown, acknowledges SEMI in its updated year-end forecast. But make no mistake: leading-edge technology investments are still happening, and growth will return in the typical cyclical pattern.


Nikon and Intel announcements highlight 450mm news from Japan

Thu, 12 Dec 2012

In news from Semicon Japan, a Nikon spokesperson said that the company plans to ship high-volume manufacturing (HVM) lithography tools in 2017, and Intel officially announced a 450mm Japan Metrology Center.


Actinic EUV source firm Adlyte details expansion plans

Wed, 11 Nov 2012

Swiss firm Adlyte, a developer of high-brightness laser-produced plasma (LPP) EUV light source for actinic mask inspection, is outlining its current expansion efforts, which includes appointing a longtime industry exec to its strategic advisory board.


EV Group completes cleanroom expansion, opens new R&D labs

Wed, 11 Nov 2012

EV Group has completed its expanded cleanroom IV facility at its corporate headquarters in Austria, which doubled its cleanroom space for process development and pilot production services.


GSA, IC Insights team on 5th edition of IC Foundry Almanac

Wed, 11 Nov 2012

A reference book from the Global Semiconductor Alliance (GSA) and IC Insights puts foundry information at the fingertips of those who need it the most.


Semiconductor equipment demand: Shades of 2009?

Fri, 11 Nov 2012

The latest monthly numbers for semiconductor manufacturing equipment demand aren't pretty: lows in both orders and sales not seen since the last major downcycle three years ago, and the short-term comparisons continue to widen.


Semi execs see a bright 2013, says survey

Fri, 12 Dec 2012

Industry watchers have been lowering their outlooks for 2013 over the past few weeks, but there's one set of opinions that still see optimism for an industry rebound in 2013 -- chip industry executives themselves.


Singapore IME, Nikon building R&D lab for sub-20nm semiconductor litho

Thu, 12 Dec 2012

Nikon and the Singapore A*STAR IME are jointly setting up a R&D lab to develop optical ArF lithography technology for semiconductor manufacturing to and below the 20nm device node.


Gartner: Fab equipment still getting softer, next upcycle starts in 2014

Thu, 12 Dec 2012

Global spending on wafer fab equipment (WFE) is now on pace to finish 2012 with a -17% annual decline, and 2013 now looks like it'll only be slightly better at a -10% dropoff, before the next cyclical spending upturn begins in 2014, according to an updated forecast from Gartner.


Samsung reaffirms plans for $4B investment in Austin fab: What it means

Mon, 12 Dec 2012

Samsung's reaffirmation of its planned $4B investments in its Austin, TX facilities don't offer much extra info, but do serve as a message to the market about its future plans -- with or without Apple.


Attend SPIE BACUS Symposium on photomasks in the deep sub-wavelength era

Mon, 8 Aug 2012

The Annual SPIE/BACUS Symposium, serving the worldwide photomask industry, will take place September 10-14, with the theme of successful integration and optimization of design, mask-making, and wafer fabrication in the deep sub-wavelength era.


TSMC takes 5% stake in ASML, joining Intel

Mon, 8 Aug 2012

TSMC took a 5% stake in ASML, worth EUR 838 million, as part of the ASML Holding N.V. Customer Co-Investment Program to accelerate development of EUV lithography and 450mm wafer processing. TSMC will also commit EUR 276 million to ASML’s R&D programs.


EUV lithography project launches for better resolution at 14nm

Fri, 8 Aug 2012

Germany has launched a new project, EUV projection optics for 14nm resolution, or ETIK, led by Carl Zeiss and 6 other German companies and research institutes. The aim is to improve extreme ultraviolet (EUV) lithography resolution to the 14nm node.


The ConFab 2012: A retrospective

Thu, 8 Aug 2012

The ConFab, Solid State Technology’s invitation-only event for the semiconductor industry, took place in June, with presenters from top companies and analyst firms. If you couldn’t be there, check out all the coverage from the event -- reports, presentations, video interviews and more.


Crossing Automation intros Spartan sorter options

Wed, 8 Aug 2012

Crossing Automation, Inc. announced three new options for the Spartan 300 that deliver an end-to-end contamination-free sorter environment. The new options target high volume manufacturing at 32nm and below.


2012 “Best of West” award finalists announced

Thu, 6 Jun 2012

Solid State Technology and SEMI today announced the finalists for the 2012 “Best of West” awards, recognizing important product and technology developments in the microelectronics supply chain.


DFMSim wins 1st metrology integration for its lithography software

Thu, 6 Jun 2012

DFMSim announced a distribution agreement with a leading US process control OEM that involves the integration of DFMSim’s SMARTlitho manufacturing software into new tools for advanced metrology.


EUV lithography update: 1st adopters and supplier support

Mon, 6 Jun 2012

Barclays Capital checks in on the EUV lithography market potential and which semiconductor manufacturers will press adoption. The analysts also update their expectations for lithography tool suppliers on the EUV front.


SEMICON West 2012 exhibits preview: Lithography focus

Wed, 6 Jun 2012

SEMICON West is taking place July 10-12 in San Francisco, CA. Following are new products for  lithography, including photoresist coaters and ashers.


North American semiconductor fab tool makers see 4th month of positive book-to-bill ratio

Fri, 6 Jun 2012

North-America-based manufacturers of semiconductor fab equipment posted $1.61 billion in orders worldwide in May 2012, $1.54 billion in billings, and a 1.05 book-to-bill ratio, shows SEMI.


SIA recognizes semiconductor researchers, policy supporters

Wed, 7 Jul 2012

The Semiconductor Industry Association (SIA) presented its 2012 University Researcher Awards to Stanford University professors Krishna Saraswat and Bruce Wooley as well as its 2012 Congressional Leadership Awards to Sen. Carl Levin, Sen. John McCain, Rep. Kevin Brady and Rep. Wally Herger.


EUVL workshop focuses on source power, timing

Mon, 7 Jul 2012

At the recently concluded 2012 EUVL Workshop (held June 4-8 in Maui, HI), attendees shared their latest technology developments and discussed ways to address the challenges of EUVL insertion into high-volume manufacturing (HVM).


Maxim plans major upgrades to US semiconductor fabs

Fri, 6 Jun 2012

Maxim is spending $200 million to upgrade and expand its US semiconductor manufacturing facilities in San Antonio and Dallas, TX; Beaverton, OR; and San Jose, CA. Maxim manufactures about 50% of its products in the US.


Productivity challenges identified during ISMI Manufacturing Week

Thu, 6 Jun 2012

Semiconductor manufacturers identified key factory productivity challenges that need to be addressed and shared effective solutions they will need to stay leading-edge and competitive amid turbulent industry transitions during the recent ISMI Manufacturing Week.


SEMICON West takeaways: Seasonality over cyclicality, lithography and test trends

Mon, 7 Jul 2012

SEMICON West kicked off with a surprise announcement regarding Intel's investment in ASML, but generally the event highlighted trends “as expected” in the fab supply chain, say Barclays analysts.


Cymer reports chipmakers’ adoption of lithography light source support products

Mon, 7 Jul 2012

Cymer is seeing adoption of its focus drilling technology for ArF immersion light sources and SmartPulse data management tool for light source performance monitoring, both introduced in 2011.


2012 ITRS stabilized for front-end, but changes loom for 2013

Fri, 7 Jul 2012

The overriding message for 2012 is that the roadmap has been largely stabilized with the significant changes that were input last year in the 2012 publication,” said Intel’s Alan Allan, speaking at Semicon West.


Newport introduces 450mm air bearing stages

Thu, 7 Jul 2012

Newport Corporation introduced a line of high-performance air bearing stages specifically designed for the 450mm semiconductor wafer initiative.


Q3 semiconductor tool capex pull-back: Seasonal, expect Q4 uptick

Thu, 7 Jul 2012

Barclays Capital is seeing various reasons for a Q3 2012 semiconductor fab order/shipment pull-back, following meetings around SEMICON West 2012. The analysts expect strong orders in Q4.


Semiconductor fab tool capex trends gleaned @ SEMICON West

Thu, 7 Jul 2012

After meeting with various semiconductor manufacturing tool suppliers -- Applied Materials, KLA-Tencor, Lam Research, Tokyo Electron, Teradyne and Cymer -- at SEMICON West, Citi analysts share impressions on foundry spending plans and tool choices.


How to cope with semiconductor fab tool obsolescence: ConFab preview

Thu, 5 May 2012

Sanjay Rajguru, director of ISMI, will present “Tool Obsolescence and the Impact on 200mm Manufacturing” at The ConFab 2012’s final session, Maximizing the Longevity of Investments.


EUVL insertion timing, readiness and scaling

Thu, 5 May 2012

Dr. Vivek Bakshi blogs about trends he expect to see at the upcoming 2012 International Workshop on EUV Lithography, in Maui Hawaii. 


Directed self-assembly lithography research yields contact holes on semiconductor wafer

Mon, 5 May 2012

Stanford University researchers, sponsored by Semiconductor Research Corporation (SRC), have created contact hole patterns for logic and memory semiconductors using a next-generation directed self-assembly (DSA) lithography process.


Conference Report: IITC, Day 2

Wed, 6 Jun 2012

Mike Fury reports on Day 2 of the 15th IITC (International Interconnect Technology Conference), from San Jose, CA.


The ConFab: Chasing Price, Power and Performance

Tue, 6 Jun 2012

At The ConFab 2012, fabless companies and foundries have a common goal: reduce power, increase performance and reduce price (not necessarily in that order).


ConFab interview: Dai Nippon Printing's Naoya Hayashi

Tue, 6 Jun 2012

Naoya Hayashi, research fellow for electronic device operations at Dai Nippon Printing, speaks with Solid State Technology chief editor Pete Singer during The ConFab 2012. Hayashi presented “NGL Mask Readiness” in The ConFab’s session on technology trends.


The ConFab: Turning the technology knobs for system scaling

Tue, 6 Jun 2012

Chip scaling will go on for the foreseeable future, enabling new product with more compute power, more memory, faster on-chip communication. That was one of the conclusions put forth by imec’s An Steegen, speaking on technology trends at The ConFab 2012.


Conference Report: International Interconnect Technology Conference, IITC

Tue, 6 Jun 2012

The 15th IITC (International Interconnect Technology Conference) opened Monday, June 4 at the Doubletree Hotel in San Jose, CA. Recurring themes this year were variations on 3D and TSV, novel systems and packaging, and back end memory. Mike Fury reports.


@ The ConFab: How to prevail over silicon cycles

Mon, 6 Jun 2012

At The ConFab’s opening session, “The Economic Outlook for the Semiconductor Industry,” capex was a major point of interest. Jackie Sturm of Intel, Dan Hutcheson of VLSIresearch, and Jim Feldhan of Semico all touched on it, with Hutcheson expanding on the idea of capex trends to present an entire ecosystem of semiconductor business management.


Cymer demos 50W EUV lithography litho source

Mon, 6 Jun 2012

Cymer presented at Barclays Capital’s TMT Conference, providing information on semiconductor makers’ transition from deep ultra violet (DUV) to extreme ultraviolet (EUV) lithography, pre-pulse technology demonstrations, and more.


ITF: The technology knobs for system scaling

Fri, 5 May 2012

At imec's International Technology Forum, An Steegen, Senior Vice President Process Technology at imec, discusses the three technology knobs that are key for a further system scaling.


ITF: Life has changed

Fri, 5 May 2012

At imec's International Technology Forum, the research consortium's CEO, Lec van den Hove, draws attention to the need for the industry to solve the world's health problems.


ITF: Winning together with strategic collaboration

Fri, 5 May 2012

At imec's International Technology Forum, Greg Bartlett, CTO of GLOBALFOUNDRIES, said the key to survival in the semiconductor industry is adaptability and collaboration.


Top suppliers of wafer processing equipment: VLSIresearch survey

Fri, 5 May 2012

THE BEST rankings from VLSIresearch identify the highest-rated suppliers of wafer processing, assembly, and test equipment. Check out the top-rated suppliers of wafer processing equipment, by company size and customer ranking.


Best semiconductor fab tool suppliers: VLSIresearch survey results

Fri, 5 May 2012

VLSIresearch polled semiconductor manufacturers about their tool suppliers, asking chipmakers to rank equipment providers on customer satisfaction. This year’s results show renewed focus on fab needs.


SEMICON West Day 2: DSA lithography and CMP meetings

Thu, 7 Jul 2012

Blogger Michael A. Fury, Ph.D., Techcet Group, reports on Day 2 of SEMICON West with insights from the Sokudo Lithography Forum and NCCAVS CMPUG meeting, and -- sadly -- none on SEMICON West’s Happy Hour.


SEMICON West Day 1: Focus on EUV lithography and 450mm

Wed, 7 Jul 2012

Barclays Capital analysts share observations from meetings with semiconductor manufacturing tool suppliers at SEMICON West, noting the enthusiasm and concrete deals around EUV lithography and transitioning to the 450mm wafer size.


Imec at SEMICON West: Interview with Luc Van den hove

Tue, 7 Jul 2012

Luc Van den hove, president and CEO, imec, spoke with Solid State Technology, covering imec’s major announcements and research presentations to take place during SEMICON West 2012.


ATMI aims for safer, cleaner liquid containment during semiconductor and related fab

Tue, 7 Jul 2012

ATMI introduced BrightPak, its next-generation liquid containment and delivery system for high-value liquid material transfers during advanced photolithography processes in semiconductor, FPD, and LED manufacturing.


Semiconductor equipment spending to contract 2.6% in 2012, grow in 2013

Tue, 7 Jul 2012

Semiconductor equipment sales will reach $42.4 billion in 2012, according to the mid-year edition of the SEMI Capital Equipment Forecast, released at SEMICON West 2012.


Semicon West 2012 opens with semiconductor revenue forecasts, high-level perspectives

Tue, 7 Jul 2012

Michael A. Fury, Ph.D., reports from the pre-opening day (July 9) of SEMICON West at the Moscone Center in San Francisco, CA. The first day hosts SEMI’s press conference on semiconductor revenues and the SEMI/Gartner Market Symposium.


Intel takes 15% stake in ASML, part of EUV, 450mm development push

Tue, 7 Jul 2012

ASML established a program to enable its largest customers to make minority equity investments in the semiconductor manufacturing tool maker. The program includes commitments to fund ASML's R&D spending, accelerating development of EUVL and 450mm technology for 2015-2020 timeframe.


More SEMICON West exhibit previews

Sun, 7 Jul 2012

Following are some of the new and flagship products that will appear this week at SEMICON West, July 10-12 in the Moscone Center of San Francisco, CA.


Gigaphoton intros ArF excimer laser improvement tools

Mon, 7 Jul 2012

Gigaphoton Inc. will uncrate “s” series hardware and software products in Q3 2012, enhancing lithography exposure performance and reducing operating costs and downtime of the GT6xA ArF excimer laser series for multi-pattern immersion lithography scanners.


Top conference reports from H1 2012

Fri, 7 Jul 2012

We at Solid State Technology have compiled the best conference reports so far this year, in the lead up to SEMICON West 2012, next week in San Francisco.


Gigaphoton EUV lithography conversion efficiency tops semiconductor fab sector target

Thu, 7 Jul 2012

Gigaphoton Inc. reached a maximum of 5.2% EUV coversion efficiency (CE), beating the semiconductor manufacturing industry’s target of 5.0% for a first-generation EUV lithography scanner. These data show an average of 4.7% CE.


SPIE -JM3 Journal publishes special issue on EUV lithography sources

Mon, 6 Jun 2012

Dr. Vivek Bakshi blogs about an upcoming SPIE journal, the Journal of Micro/Nanolithography, MEMS, and MOEMS (JM3), which has a focus on EUV sources.


Process Watch: Skewing the defect pareto

Mon, 6 Jun 2012

In the second installment in a series called Process Watch, the author provides tips on how to make sure you’re reviewing the yield killing defects and not wasting time reviewing nuisance events. Authored by experts at KLA-Tencor, Process Watch articles focus on novel process control solutions for chip manufacturing at the leading edge.


ISMI addresses tool obsolescence

Wed, 6 Jun 2012

Speaking at The ConFab 2012, Sanjay Rajguru, director of ISMI, pointed out that more than half the current fab capacity today comes from facilities that are more than ten years old, which is creating a problem with equipment obsolescence.


ConFab interview: G450 Consortium's Tom Jefferson on 450mm timeline

Wed, 6 Jun 2012

Tom Jefferson, G450 Consortium, shares an update on 450mm wafers for semiconductor manufacturing. The consortium is adding staff and ramping its silicon supply, and getting ready for equipment selection.


ConFab interview: Bill Tobey on EUV lithography

Wed, 6 Jun 2012

Bill Tobey, president of ACT International Consulting, speaks about the evolution of extreme ultra violet (EUV) lithography at The ConFab 2012.


ConFab interview: ISMI’s Bill Ross on managing legacy fabs and supply obsolescence

Wed, 6 Jun 2012

Bill Ross, ISMI, is moderating a session today at The ConFab 2012 on managing legacy semiconductor fabs and dealing with tool and materials obsolescence at 200mm and smaller. He speaks with Pete Singer about coping with these changes.


Record semiconductor fab spending on tap for 2013

Wed, 6 Jun 2012

Fab equipment spending has improved in 2012, breaking the barrier into positive growth for the year, shows SEMI. Semiconductor makers will invest $39.5 billion in fabs, up 2% from 2011 spending. Fab capex will hit a record in 2013, $46.3 billion or 17% above 2012.


Printed electronics researchers in Europe install Optomec jet deposition tools

Fri, 7 Jul 2012

Optomec’s Aerosol Jet deposition tools are being used for printed sensor, display, solar cell, CMOS and passive devices, and other development areas, with new installations at CEA Liten (France), Innovation Lab (Germany) and the University of Sheffield (UK).


Majority of semiconductor manufacturing suppliers experience IP challenges

Tue, 7 Jul 2012

SEMI recently conducted a survey of semiconductor fab equipment and materials suppliers, finding that 60+% of respondents say that IP challenges have had an adverse impact on their companies.


Secondary semiconductor equipment: Turnkey services offer a fab-centric approach

Mon, 7 Jul 2012

RED Equipment’s Carl McMahon suggests a different model for handling secondary semiconductor equipment for greater efficiency, cost reduction and quality control: full turnkey services engineered to the fab’s needs without the expense of customization.


Rudolph buys NanoPhotonics to bolster advanced packaging inspection offering

Thu, 6 Jun 2012

Rudolph Technologies Inc. (NASDAQ:RTEC) acquired the assets of NanoPhotonics GmbH, adding inspection technology and an intellectual property (IP) portfolio to serve its advanced package inspection tool customers.


Conference Report: TechConnect 2012, Day 1

Wed, 6 Jun 2012

The 2012 TechConnect World Summit, Expo & Showcase opened Tuesday, June 19, 2012 at the Santa Clara Convention Center. The event serves as host to the National Innovation Showcase, whose mission is to accelerate the commercialization of “the world’s top innovations.”


Canon DUV stepping scanner promises 60% higher lithography throughput

Fri, 6 Jun 2012

Canon U.S.A. Inc. introduced the FPA-6300ES6a DUV stepping scanner, a lithography tool with a KrF excimer laser light source for the high-volume production of memory, logic and image-processing devices.


Legacy semiconductor fab issues @ The ConFab 2012

Wed, 6 Jun 2012

Older production facilities face equipment obsolescence; skills obsolescence; scarce availability of parts, software, and support; and equipment capability extension and tool re-use. At the ConFab 2012 Executive Roundtable, representatives from Sematech/ISMI, IDMs, OEMs, equipment dealers, and industry consultants gathered to have an open discussion on concerns, roadblocks, and possible solutions.


Semiconductor fab tool makers see sequential increase in Q1

Wed, 6 Jun 2012

Semiconductor manufacturing equipment billings and bookings were virtually tied in Q1 2012, reports SEMI, with $10.61 billion in billings and $10.07 in bookings. This is a 13-14% improvement sequentially, and 9% below the same quarter last year.


iPhone 5: Which semiconductor suppliers are the big winners?

Fri, 9 Sep 2012

As the dust settles after the launch of the iPhone 5, analysts tally which suppliers in the semiconductor ecosphere are most likely to gain the most.


Chip tool demand slumps in 2Q12, though Taiwan shines

Wed, 9 Sep 2012

Global demand for semiconductor manufacturing equipment slipped -4% in 2Q12 with softness in just about every region -- except Taiwan which stepped on the pedal during the quarter, according to updated data from SEMI and SEAJ.


Scotch tape induces high-temp superconductivity

Wed, 9 Sep 2012

A team led by University of Toronto physicists has developed a simple new technique using Scotch poster tape that has enabled them to induce high-temperature superconductivity in a semiconducto.


SRC honors professors from UC Berkeley and MIT

Wed, 9 Sep 2012

Semiconductor Research Corporation (SRC) recognized two outstanding professors in SRC-supported, chip-related research and education for 2012.


Intel lowers 3Q outlook: What's the real driving factor?

Fri, 9 Sep 2012

Analysts weigh the reasons behind Intel's downwardly-revised 3Q12 results, from macroeconomic sluggishness to tablet-PC cannibalization -- and whether its pullback in 2012 capex plans spells trouble for the market overall.


Intel lowers 3Q outlook: What's the real driving factor?

Fri, 9 Sep 2012

Analysts weigh the reasons behind Intel's downwardly-revised 3Q12 results, from macroeconomic sluggishness to tablet-PC cannibalization -- and whether its pullback in 2012 capex plans spells trouble for the market overall.


Waiting for the next "golden year"

Fri, 9 Sep 2012

While various industry segments appear to be tapping the brakes, others are revving their engines, observes SEMI's Christian Gregor Dieseldorff -- and a 2012 stall could pave the way for a record-breaking 2013.


Semiconductor R&D spending rising 10% in 2012 to meet design, process challenges

Thu, 9 Sep 2012

Spending on R&D by semiconductor companies worldwide is expected to grow 10% in 2012 to a record $53.4 billion, as companies all across the ecosystem try to keep up with more complex IC designs and new process technologies, according to data from IC Insights.


Laser nanofabrication for mass production at the nanoscale

Fri, 8 Aug 2012

Laser nanofabrication can now meet the needs of submicron and nanoscale feature size manufacturing, and can operate in air, vacuum, or liquid processes. Sister publication Industrial Laser Solutions recently published Laser nanofabrication: A route toward next-generation mass production.


Supply chain readiness in an era of accelerated change

Fri, 8 Aug 2012

In this SEMI News and Views blog, Karen Savala covers EUV lithography, 450mm wafers, and 3D IC developments, based on her recent presentation at SEMICON West, “Supply Chain Readiness in an Era of Accelerated Change.”


EUV Symposium takeaways: Slow and steady progress, much improvement expected in early 2013

Tue, 10 Oct 2012

EUV Symposium host imec and a pair of industry analysts gauge the pace of improvements in EUV lithography and its long march toward production readiness.


Europe to unite research efforts in Silicon Europe cluster alliance

Mon, 10 Oct 2012

Four of the leading micro- and nanoelectronics regions in Europe are joining forces to form a cluster alliance called “Silicon Europe.”


imec to begin 450mm cleanroom construction in 2013

Sun, 10 Oct 2012

Imec, the research consortium in Leuven, Belgium, plans to start construction of a 450mm pilot line next year, with early production focused on sub-10nm devices starting at the end of 2016. 


Dynamic changes impacting advanced electronic materials industry

Wed, 8 Aug 2012

Learn about the changes in semiconductor manufacturing as well as related markets -- photovoltaics, displays, LEDs, etc -- at the 2012 Strategic Materials Conference (SMC), to be held on October 23-24 in San Jose, CA. SEMI reports.


Present on semiconductor metrology and more at ASMC 2013

Wed, 8 Aug 2012

ASMC 2013, the leading international technical conference for exploring solutions to improve collective microelectronics manufacturing expertise, has issued a call for papers.


North American semiconductor fab tool orders tracked flat Y/Y in July

Fri, 8 Aug 2012

"Bookings and billings for North American semiconductor equipment in July are close to values reported exactly one year ago," said Denny McGuirk, SEMI, noting seasonally slow investment activity.


SRC to host TECHCON conference in September

Wed, 8 Aug 2012

Semiconductor Research Corporation (SRC), a university-research consortium for semiconductors and related technologies, is poised to celebrate its 30th anniversary at its annual TECHCON conference Sept. 10-11.


SEMI builds portal for 450mm info

Mon, 8 Aug 2012

SEMI's new "450 Central" information portal offers news and perspectives about the 450mm wafer-size transition.


ASML adds Samsung as third chipmaker investor, closes funding plan

Mon, 8 Aug 2012

Lithography leader ASML completes its Co-Investment Program, tallying €3.85 billion in equity funds and €1.38B to support R&D into EUV and 450mm.


TSMC joins <10nm lithography mask writer project

Fri, 8 Aug 2012

TSMC joined IMS’s multibeam mask writer development collaboration to develop an electron multi-beam mask writer for use in advanced mask lithography applications, joining founding members DNP, Intel, and Photronics.


SEMATECH reports EUV lithography mask defect and cleaning breakthroughs

Tue, 8 Aug 2012

SEMATECH researchers have deposited EUV multi-layers with as few as 8 defects per lithography mask, at 50nm sensitivity. The milestone shows that tool-generated defects during multi-layer deposition of mask blanks used for EUV lithography can be reduced enough to enable high-volume manufacturing.


Analyst: Fab spending softness 2012 extending into 2013

Thu, 10 Oct 2012

Fab equipment spending continues to soften in 2012, and hopes for a reprieve in 2013 are waning, warns one analyst.


Japan's semiconductor industry: Fabs, equipment, and materials

Wed, 10 Oct 2012

Even though semiconductor manufacturers in Japan are consolidating and transitioning to a "fab-lite" strategy,  the region still represents a large installed fab capacity and a major market for equipment and materials suppliers.


New method monitors, catalyzes semiconductor etch in real time

Tue, 10 Oct 2012

Researchers at the U. of Illinois have devised a method to monitor a semiconductor surface as it is etched, in real time, with nanometer precision.


Laser spike anneal for photoresists outperforms hotplate bake

Mon, 10 Oct 2012

Researchers at Cornell have developed a new laser-based method for ultra-fast anneal of thin photoresist films. The research, sponsored by Semiconductor Research Corporation (SRC), has shown that the new anneal outperforms state-of-art hotplate bake for both 193nm and EUV lithography applications.


Molybdenum sulfide: the new graphene?

Thu, 9 Sep 2012

Researchers have begun to investigate a new 2D material—molybdenum sulfide (MoS)—which has similar characteristics but offers something graphene doesn’t: a wide energy bandgap, enabling transistors and circuits to be built from it directly.


On-board heaters can self-heal flash memories

Thu, 9 Sep 2012

At the upcoming International Electron Device Meeting, Macronix researchers will describe how they built flash memories that could heal themselves by means of tiny onboard heaters that provide thermal annealing just at the spots where it is needed.


Everspin to unveil highest-density ST-MRAM

Thu, 9 Sep 2012

In an invited paper at the International Electron Devices Meeting, researchers from Everspin Technologies will describe how they built the largest functional ST-MRAM circuit ever built, a 64-Mb device with good electrical characteristics.


Better than FinFETs: Hybrid-Channel SOI

Thu, 9 Sep 2012

At the International Electron Devices Meeting (IEDM) in December, a team led by IBM will report on the world’s first high-performance hybrid-channel ETSOI CMOS device.The researchers built a ring oscillator circuit to benchmark performance that worked even better than FinFETs.


Process Watch: Taming the overlay beast

Tue, 9 Sep 2012

In the fourth installment in a series called Process Watch, the authors discuss overlay registration and new capabilities to align to buried layers. Authored by experts at KLA-Tencor, Process Watch articles focus on novel process control solutions.


NanoYield: new design for yield software released

Thu, 9 Sep 2012

ProPlus Design Solutions, Inc. unveiled NanoYield, yield prediction and optimization software for memory, logic, analog and digital circuit design.


TSMC's schedule for 450mm mass production -- and lithography is the key

Wed, 9 Sep 2012

During sessions at this month's SEMICON Taiwan, execs from TEL, Lam Research, Applied Materials and KLA-Tencor revealed the latest developments in 450mm technology.


Chip demand still sliding, hopes for soft 3Q landing and recovery

Fri, 9 Sep 2012

Demand for chip tools fell again in August and is off by -30% from its peak in early summer, fulfilling fears that the second half of 2012 will be sluggish for chipmaking investments, according to the latest data from SEMI.


Hynix joins SEMATECH's EUV mask group

Fri, 9 Sep 2012

SK Hynix has joined SEMATCH's EUV Mask Infrastructure (EMI) partnership to help develop metrology tools for reviewing defects in advanced masks needed for extreme ultraviolet lithography (EUVL).


TSMC integrates Ge on Si in p-type FinFETs

Thu, 9 Sep 2012

At this year’s International Electron Devices Meeting (IEDM), foundry TSMC will describe a heterogeneous epitaxial growth process which for the first time enables Ge to be directly grown on Si.


Horizontal channels key to ultra-small 3D NAND

Thu, 9 Sep 2012

The first working 3D NAND flash memory at sub-40nm feature sizes will be described by Macronix researchers at this year’s International Electron Devices Meeting (IEDM).


RRAM synapses mimic the brain

Thu, 9 Sep 2012

At this year’s IEDM, a team led by Korea’s Gwangju Institute of Science and Technology will detail a high-speed pattern-recognition system comprising CMOS “neurons” and an array of resistive-RAM (RRAM)-based “synapses,” which demonstrated STDP, a brain-like function.


North American semiconductor equipment industry posts May 2013 book-to-bill ratio

Fri, 6 Jun 2013

A book-to-bill of 1.08 means that $108 worth of orders were received for every $100 of product billed for the month.


Global semiconductor manufacturing equipment spending to decline in 2013, says Gartner

Thu, 6 Jun 2013

Outlook for semiconductor equipment market improves, but remains soft in the short term.


SEMATECH to address critical supply chain challenges and more at SEMICON West 2013

Mon, 6 Jun 2013

Through a series of lectures and workshops, SEMATECH will address R&D challenges and closing key infrastructure technology gaps from July 8–12 at SEMICON West in San Francisco, CA.


SEMATECH names William R. Rozich chairman of the board

Mon, 6 Jun 2013

Rozich, who previously was a member of the company’s board, succeeds Michael R. Polcari, who served as chairman since November 2009.


Semiconductor inventory falls in Q1 as outlook for electronics demand rises

Thu, 6 Jun 2013

Total inventory held by semiconductor suppliers declined significantly in the first quarter as excess stockpiles created during the global economic malaise of 2012 were cleared away, done in anticipation of a resurgence in consumer demand for electronic products expected by the second half of 2013.


Producing cheaper and more flexible multiple thin crystalline silicon wafers

Wed, 6 Jun 2013

A team of researchers has found a way to make the manufacture of crystalline silicon materials faster and more affordable.


UMC joins IBM chip alliance for 10nm process development

Thu, 6 Jun 2013

IBM and United Microelectronics Corporation, a global semiconductor foundry, today announced that UMC will join the IBM Technology Development Alliances as a participant in the group's development of 10nm CMOS process technology.


450mm – It’s bigger than you think

Thu, 6 Jun 2013

Much has been said of the 450mm transition.  But the description of this inflection is something of a misnomer.


GLOBALFOUNDRIES unveils plans to accelerate adoption of 20nm-LPM and 14nm-XM FinFET processes

Fri, 5 May 2013

At next week's 50th Design Automation Conference in Austin, Texas, GLOBALFOUNDRIES will unveil a comprehensive set of certified design flows to support its most advanced manufacturing processes.


Precision is key to scaling below 14nm

Mon, 6 Jun 2013

In advance of the 2013 SEMICON West TechXPOTs on lithography and nonplanar transistors beyond 20nm, SEMI asked some of the speakers and industry experts to comment on the challenges they wanted to highlight. Many of the inputs focused on the need for precision in the processes used to form transistors, as well as how EDA can contribute to mitigating variability.


Fab equipment spending: 23% growth for 2014

Tue, 6 Jun 2013

Fab equipment spending will grow two percent year-over-year  (US$ 32.5 billion) for 2013 and about 23 to 27 percent in 2014 ($41 billion) according to the May edition of the SEMI World Fab Forecast.


Extending optical lithography; outlook for DSA

Mon, 5 May 2013

This year’s SEMICON West front-end processing TechXPOTs on lithography and transistors below 20nm will provide critical updates on how technologists are coping with the next scaling challenges.


Silicon Valley foundry Noel Technologies adds advanced lithography services

Thu, 5 May 2013

Foundry hires former ASML’s Keith Best as director of photolithography; tasked with driving roadmap to 0.15 microns


Confronting sub-20nm front-end challenges with the “duck and weave”

Wed, 4 Apr 2013

Just as a boxer avoids a surprise shot to the head or torso by using a “duck and weave” maneuver, so to must front-end technologists confront the challenges associated with extending optical lithography while planning for EUV lithography’s eventual high-productivity solution.


Critical updates on EUV, 3D transistors and 450mm manufacturing at SEMICON West 2013

Tue, 4 Apr 2013

The critical processes and technologies necessary to continue Moore’s Law are currently more uncertain than ever before in the history of advanced semiconductor manufacturing.


Strategic approach to R&D is goal at National Photonics Initiative Event

Thu, 3 Mar 2013

More than 100 representatives from government and the photonics industry convened in Washington, D.C., on February 28 to identify focus areas for a national photonics initiative (NPI), engaging academia, industry, and government in a collaboration to address barriers to continued U.S. leadership in photonics.


'Key' EUV milestone, DSA progress, more reported at SPIE Advanced Lithography

Thu, 3 Mar 2013

Over 2,000 industry professionals attended last week’s SPIE Advanced Lithography, where important progress reports were revealed on extreme ultraviolet (EUV), lithography, directed self-assembly (DSA), metrology, and related topics. The event ran February 24-28 in San Jose, California.


STMicroelectronics makes analog 130nm H9A CMOS process available through CMP

Thu, 3 Mar 2013

Semiconductor technology leaders ST and CMP help universities, research labs and companies prototype next generation of Systems-on-Chip.


Car infotainment semiconductor market hits speed bump in 2013

Wed, 3 Mar 2013

Following a healthy expansion in 2012, the growth of the global automotive semiconductor market will decelerate slightly this year because of a slowdown in the aftermarket and portable navigation device (PND) segments.


North American Semiconductor Industry: Continuing with high levels of investments

Thu, 5 May 2013

While investments and capital spending in Asia-Pacific garner much of the attention regarding semiconductor manufacturing, spending on equipment and materials in North America has totaled more than $100 billion over the past decade as leading device manufacturers expand capacity and invest in new facilities.


Second phase of Nanoelectronics Research Initiative to focus on post-CMOS electronics

Wed, 5 May 2013

SRC and NIST will provide a combined $5 million in annual funding for three multi-university research centers tasked with demonstrating non-conventional, low-energy technologies that outperform current technologies on critical applications in 10 years and beyond.


Intel launches low-power, high-performance microarchitecture

Tue, 5 May 2013

Intel Corporation today took the wraps off its brand new, low-power, high-performance microarchitecture named Silvermont.


Eleven companies move up in Q1’13 top 20 semi supplier ranking

Tue, 5 May 2013

Qualcomm, TSMC, and SK Hynix each register greater than 20 percent year-over-year growth.


Samsung now producing 4Gb LPDDR3 mobile DRAM at 20nm

Tue, 4 Apr 2013

Samsung Electronics Co., Ltd. today announced the industry’s first production of ultra-high-speed four gigabit (Gb) low power double data rate 3 (LPDDR3) mobile DRAM, which is being produced at a 20nm-class process node.


Semiconductor industry to recognize Philip Yeo and Lee Kok Choy at SEMICON Singapore 2013

Mon, 4 Apr 2013

SEMI today announced that Philip Yeo, chairman of SPRING Singapore, and Lee Kok Choy, country manager of Micron Technology Inc. Singapore, have been voted by the SEMI Singapore Regional Advisory Board as recipients of two prestigious awards recognizing their contributions to the development and success of the Southeast Asian semiconductor industry.


Cadence and GLOBALFOUNDRIES to improve DFM signoff for 20 and 14nm nodes

Mon, 4 Apr 2013

Cadence Design Systems, Inc. announced today that GLOBALFOUNDRIES has collaborated with Cadence to provide pattern classification data for manufacturing processes of 20 and 14 nanometers.


Morgan Advanced Materials joins SEMATECH to develop process solutions

Mon, 4 Apr 2013

Morgan Advanced Materials has joined SEMATECH’s International SEMATECH Manufacturing Initiative (ISMI), a program designed to improve semiconductor equipment manufacturing productivity, yield, and cost.


Infineon and GLOBALFOUNDRIES announce collaboration for 40nm embedded flash process

Mon, 4 Apr 2013

Infineon Technologies and GLOBALFOUNDRIES Inc. today announced a joint technology development and production agreement for 40nm embedded flash (eFlash) process technology.


Global semiconductor industry to witness a CAGR of 4.3% over next five years

Fri, 4 Apr 2013

Global macroeconomic developments and technological advances, personal computers, and memory markets are expected to drive demand over the forecast period, Research and Markets predicts in their report, “Global Semiconductor Industry 2012-2017: Trend, Profit and Forecast Analysis.”


Global semiconductor sales outpace last year through Q1 of 2013

Tue, 5 May 2013

Sales in March 2013 were up slightly compared to February 2013 and March 2012.


Reinventing Intel

Fri, 4 Apr 2013

The semiconductor chip giant revealed plans to branch out beyond PCs. Will it work?


SEMI reports March book-to-bill ratio of 1.14

Fri, 4 Apr 2013

North America-based manufacturers of semiconductor equipment posted $1.14 billion in orders worldwide in March 2013 (three-month average basis) and a book-to-bill ratio of 1.14, according to the March Book-to-Bill Report published today by SEMI.


IRPS 2013: New insight into erratic bits

Tue, 4 Apr 2013

Error correction code and redundant addresses are both techniques well-known in memories as a way of optimizing yield. But new data from the University of Ferrara shows that these common techniques may be overused. By classifying erratic bits more carefully, it’s possible to use less ECC and up to 35 percent less redundancy.


IRPS 2013: Oxygen interstitials can impact RRAM retention time

Tue, 4 Apr 2013

The ability of a resistive RAM device to maintain its resistance state, otherwise known as retention time, can be impacted by the electrode materials used.


IRPS 2013: Discrete trapping and detrapping seen in flash memories

Tue, 4 Apr 2013

New flash memory chips are replacing the floating gate with thin layers of material that "trap the charge." The charge trap is a sandwich of materials such as silicon-oxide-nitride-oxide-silicon (SONOS), metal-oxide-nitride-oxide-silicon (MONOS) and tantalum-aluminum oxide-nitride-oxide-silicon (TANOS), all of which are substantially smaller than the floating gate.


IRPS 2013: Breakdown voltage dependent on polarity

Tue, 4 Apr 2013

At the International Reliability Physics Symposium (IRPS), being held April 14-18, 2013 at the Hyatt Regency Monterey Resort & Spa in Monterey, CA, imec will present new research focused on the stress induced breakdown between the tungsten trench local interconnects (M1, M2) and metal gate in a 28nm CMOS technology. Imec’s Thomas Kauerauf will present a paper titled “Reliability of MOL local interconnects.”


IRPS 2013: High-k oxides pose new reliability challenges

Tue, 4 Apr 2013

New finFETs feature high-k dielectrics, which are better than conventional silicon nitride dielectrics in that they can be thinner, yet still enable good control of the transistor’s channel region from the gate.


IRPS 2013: Self-heating to accelerate aging in FinFETs

Tue, 4 Apr 2013

It’s well-known that transistors generate heat when they’re operating, and that can have a significant impact on the chip’s reliability and longterm longevity. A small increase of 10°C–15°C in the junction temperature may result in ∼ 2× reduction in the lifespan of the device.


IRPS 2013: NBTI worsens with FinFET scaling

Tue, 4 Apr 2013

FinFETs offer several advantages compared to traditional planar transistors, but it’s not yet clear what kind of new reliability problems might arise as FinFETs are scaled to smaller dimensions.


Semiconductor R&D: A state of transition

Thu, 4 Apr 2013

Several years ago when the challenges to 450mm wafer processing, EUV development and novel transistor designs were first being discussed, SEMI commissioned a study that predicted the industry could face an R&D funding gap that could exceed $9 billion if current technology and economic trends continue.


2013: 450mm is the next big opportunity

Thu, 1 Jan 2013

In semiconductor manufacturing, 450mm is the next big opportunity. Issues of economic scale and complexity will force fab designers, OEMs and process integrators to investigate all open avenues in the search for solutions to the huge challenges that accompany 450mm.


2013: Thriving in the transition to 450mm

Wed, 1 Jan 2013

The development of innovative technologies that solve the critical issues for the transition and adoption of 450-mm manufacturing will be the defining factor for whether a company merely survives or thrives.


2013: Building the internet of things with MEMS and 3D advances

Wed, 1 Jan 2013

It is becoming increasingly clear that new MEMS and 3D high-volume, low-cost manufacturing technologies will accelerate a radical change to society’s cyber skyline.


2013: Fab Equipment Spending Shrinks Back to Flat

Wed, 1 Jan 2013

The SEMI Consensus Forecast and the SEMI World Fab Forecast, with data collected from two different methodologies, point to the same conclusion: 0% growth for 2013.


MEMS devices shape medical industry, microsystem devices to reach $6.6 billion in 2018

Wed, 2 Feb 2013

Microelectromechanical (MEMS) devices are shaping the competitive landscape in the global medical device industry.


Silicon wafer revenues decline in 2012

Tue, 2 Feb 2013

Worldwide silicon wafer revenues declined by 12 percent in 2012 compared to 2011, according to the SEMI Silicon Manufacturers Group (SMG) in its year-end analysis of the silicon wafer industry.


ISSCC 2013: Large-area flexible electronics

Mon, 2 Feb 2013

Hoi-Jun Yoo, subcommittee chair of ISSCC 2013, writes on the focus of technology directions in the field of large-area and low-temperature electronics.


Econometric Forecast: Semiconductor growth should recover by 2014

Fri, 2 Feb 2013

In the second of two installments, Linx Consulting reports a steady growth in semiconductor production, as released in The Econometric Semiconductor Forecast.


Econometric Forecast: Regional developments to affect growth of semiconductor industry

Thu, 2 Feb 2013

In the first of two installments, we examine the global issues facing the semiconductor industry, as released by Linx Consulting in The Econometric Semiconductor Forecast.


Econometric forecasting service predicts 6% growth in semiconductor wafers in 2013

Thu, 2 Feb 2013

A new econometric semiconductor industry forecast predicts semiconductor wafer area production to grow slightly less than 6% in 2013, according to Linx Consulting.


Looking for an integrated post-tapeout flow

Wed, 2 Feb 2013

Dr. Steffen Schulz discusses the role of a flexible platform for computational lithography in a successful business strategy.


Semiconductor R&D spending rises 7% despite weak market

Tue, 2 Feb 2013

Spending on research and development by semiconductor companies grew 7% in 2012 to a record-high $53.0 billion, even though the semiconductor market declined 1% to $317.6 billion.


New research to improve efficiency, fabrication of optoelectronics

Fri, 2 Feb 2013

Scientists at RTI International are advancing the state of science in electronic devices for optical systems by using superlattice structures to optimize the performance of germanium optical detectors on silicon chips.


Japan Prize awarded for chemically amplified resists

Thu, 1 Jan 2013

C. Grant Willson and Jean M.J. Fréchet won the Japan Prize, an international award similar to the Nobel Prize, for their work on chemically amplified resists. 


Gigaphoton achieves maximum 20W EUV light source output

Mon, 2 Feb 2013

Gigaphoton, Inc., a major lithography light source manufacturer, announced today that the company has achieved EUV light output equivalent to maximum of 20W for its laser-produced plasma, or LPP light sources for EUV lithography scanners.


ISS 2013: Semiconductor leaders see massive industry transformation

Tue, 1 Jan 2013

The rise in mobile computing, changes to the fabless-foundry model, uncertainties in technical innovation, and global macroeconomic trends are becoming the dominant forces in 2013 and beyond, according to industry leaders speaking at this week's SEMI Industry Strategy Symposium (ISS).


GlobalFoundries adding R&D facility to NY fab campus

Fri, 1 Jan 2013

GlobalFoundries says it plans to build a $2 billion "Technology Development Center" R&D facility at its Fab 8 campus in Saratoga County, NY, for semiconductor technology development and manufacturing:  EUV lithography photomasks to new interconnect and packaging technologies enabling 3D chip stacking, "and everything in between."


Innovations in computational lithography for 20nm

Tue, 1 Jan 2013

Several innovations in computational lithography have been developed in order to squeeze every possible process margin out of the lithography/patterning process.  In this blog, Gandharv Bhatara of Mentor Graphicsl talks about two specific advances that are currently in deployment at 20nm.


Cymer hires AMAT roadmap exec to lead EUV development

Tue, 1 Jan 2013

Klaus Schuegraf, former exec at Applied Materials responsible for the company's semiconductor products technology roadmap, will now lead Cymer's EUV engineering and development programs.


2013: Advanced chemistry moves center stage

Fri, 1 Jan 2013

We are in an age where chemistry is center stage in the race to advance Moore’s Law and More Than Moore.


IDC: Semiconductor revenues will grow 4.9% in 2013

Fri, 1 Jan 2013

The International Data Corporation is forecasting that semiconductor revenues worldwide will improve by 4.9% to $319 billion in 2013 and log a compound annual growth rate (CAGR) of 4.1% from 2011-2016.


2013: Healthy revenue growth, but capex likely flat

Fri, 1 Jan 2013

Based on current indications, capital spending would seem to be flat in 2013.  However, Semico predicts healthy revenue growth this year, which may encourage more spending, particularly in the second half of the year.  This may bring total capex for 2013 into the positive range.


2013: An economic outlook for the global IC market

Thu, 1 Jan 2013

Predictions for 2013 show several notable trends: overall silicon area growth for 2013 should average approximately 6%; the first quarter and the second half are likely to show slower growth than the second quarter; and the modest growth forecast for 2013 is predominantly demand driven.


Newport introduces long-lived deep UV excimer laser mirrors

Tue, 1 Jan 2013

Newport Corporation introduced long-lived deep ultraviolet (UV) excimer laser mirrors with projected lifetimes greater than 30 billion pulses.


Process Watch: Exploring the dark side

Fri, 1 Jan 2013

A particle as small as three microns in diameter, attached to the back side of the wafer—the dark side, if you will—can cause yield-limiting defects on the front side of the wafer during patterning of a critical layer.


Production process doubles speed and efficiency of flexible electronics

Wed, 2 Feb 2013

Stretched-out clothing might not be a great practice for laundry day, but in the case of microprocessor manufacture, stretching out the atomic structure of the silicon in the critical components of a device can be a good way to increase a processor's performance.


SPIE Advanced Lithography will bring industry focus to next-generation tools and systems

Tue, 2 Feb 2013

SPIE Advanced Lithography, the annual forum for discussions on state-of-the-art lithographic tools, resists, metrology, materials characterization, and design and process integration, will bring the community together in San Jose, California, next week to address those challenges.


SEMATECH to demonstrate advances and technical breakthroughs at SPIE 2013

Tue, 2 Feb 2013

Papers showcase EUV extendibility and metrology techniques for defect inspection and 3D TSVs.


New Product: KLA-Tencor announces two new litho/etch process control tools

Tue, 2 Feb 2013

New metrology and inspection products facilitate advanced patterning techniques for manufacturing sub-20nm memory and microprocessor chips.


Molecular Imprints’ advanced lithography platform uses Xaar printheads to pattern 450mm wafers

Tue, 2 Feb 2013

Molecular Imprints, Inc. (MII), a developer of advanced semiconductor lithography, has announced the delivery of an advanced lithography platform which uses Xaar 1001 inkjet printheads to pattern 450mm silicon wafer substrates.


SEMATECH’s Bryan Rice named 2013 SPIE Fellow

Tue, 2 Feb 2013
SEMATECH announced today that Dr. Bryan J. Rice, on assignment from Intel Corporation as SEMATECH’s director of Strategic Initiatives, was inducted as a 2013 Fellow by SPIE, the international society for optics and photonics, during its annual SPIE Advanced Lithography conferences in San Francisco, CA.


DNP and Luminescent Technologies achieve milestone in development of metrology and inspection program

Mon, 2 Feb 2013

Luminescent Technologies Inc., a provider of computational metrology and inspection solutions for the global semiconductor manufacturing industry, and Dai Nippon Printing Company, Ltd. announced today the successful completion of the first phase of a three-year joint development program for computational metrology and inspection using Luminescent’s Automated Image Processing Hub (LAIPH) platform.


EV Group to develop equipment to enable covalent bonds at room temperature

Tue, 3 Mar 2013

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today announced that it is developing equipment and process technology to enable covalent bonds at room temperature.


Deposition Sciences increases photolithography patterning capacity

Mon, 3 Mar 2013

New 200 mm diameter wafer enhances photolithography capability.


Semiconductor sales rose in January

Mon, 3 Mar 2013

Worldwide sales of semiconductors were $24.05 billion the month of January, up 3.8% from January 2012 and down 2.8% from December 2012, according to the Semiconductor Industry Association (SIA).


Intel leads unexpectedly large decline in semiconductor market inventory

Wed, 3 Mar 2013

After reaching a worrisome high in the third quarter of 2012, global semiconductor inventories held by chip suppliers fell at a surprisingly fast rate in the fourth quarter, led by dramatic reductions for market leader Intel Corp.


A single European semiconductor strategy is on its way

Thu, 2 Feb 2013

STM, Imec, CEA-LETI, ASML, Soitec and EU representatives discussed directions at ISS Europe 2013 in Italy.


DFM Services in the Cloud

Wed, 2 Feb 2013

Joe Kwan is the Product Marketing Manager for Calibre LFD and DFM Services at Mentor Graphics. He is also responsible for the management of Mentor’s Foundry Programs. He previously worked at VLSI Technology, COMPASS Design Automation, and Virtual Silicon. Joe received a BA in Computer Science from the University of California Berkeley and an MS in Electrical Engineering from Stanford University.


Demand for exports will allow semiconductor industry to maintain modest revenue growth

Fri, 3 Mar 2013

Over the past five years, revenue dipped and spiked from the impact of the global recession; in the five years to come, increased offshoring will detract from the growth in global demand from an improved economy.


SRC, UCLA and ERC utilize atomic layer etch analysis to accelerate development of green chemistries

Thu, 3 Mar 2013

Researchers sponsored by Semiconductor Research Corporation (SRC), a university-research consortium for semiconductors and related technologies, today announced development of a modeling process designed to simulate atomic-level etching with chemicals that are effective alternatives to widely used perfluorocarbon (PFC) gases.


Blog: Dimensional scaling and the SRAM bit-cell

Thu, 3 Mar 2013

Zvi Or-Bach, President & CEO of MonolithIC 3D Inc. and Benjamin S. Louie of Zeno Semiconductor blog about dimensional scaling as it relates to EUV and future per transistor device cost.


Design for reliability of multi-layer thin film stretchable interconnects to be presented at ECTC

Thu, 3 Mar 2013

Most electronic systems that power our digital life are inflexible and flat. Rigid electronic designs work for our computers and phones but not for our bodies. Humans are soft and curved. Electronic systems capable of bending, twisting, and stretching have great potential for applications in which conventional, stiff semiconductor microelectronics would not suffice.


GLOBALFOUNDRIES partners with ASML for chip tape-outs

Wed, 3 Mar 2013

Brion Technologies, a division of ASML, announced a major milestone today in its partnership with GLOBALFOUNDRIES. The companies are collaborating to deliver high-volume computational lithography capabilities for 28 nm and 20 nm tapeouts, while also accelerating the development of future nodes, including extreme ultraviolet (EUV) lithography.


Critical process technologies and fab productivity addressed at ASMC 2013

Wed, 3 Mar 2013

Semiconductor manufacturers, suppliers and academia to collaborate on real-world issues at SEMI event.


SEMATECH and Intermolecular partner to accelerate EUV lithography

Tue, 4 Apr 2013

In an effort that will accelerate commercialization of extreme ultraviolet (EUV) lithography technology and the development of next-generation transistors, SEMATECH announced today that Intermolecular, Inc. has joined SEMATECH’s Lithography and Front End Processes (FEP) programs.


Implementation of next-generation device technology to be discussed at The ConFab 2013

Fri, 4 Apr 2013

Solid State Technology is excited to announce that Mark Thirsk, managing partner at Linx Consulting, will be discussing the cost and technology needed to implement next-generation device technology at The ConFab 2013. Thirsk has over 20 years of experience in the chemical industry, working with a variety of materials and processes utilized in wafer fabrication.


Gigaphoton starts business operations in Singapore branch

Fri, 4 Apr 2013

Gigaphoton, Inc., a lithography light source manufacturer, announced today that as of April 2013, it has started business operations at the Gigaphoton Singapore Branch, its newly established branch in that country.


ARM and Cadence to partner to implement 64-bit processor on TSMC 16nm FinFET process

Thu, 4 Apr 2013

Fulfilling the promise of performance and power scaling at 16nm, ARM and Cadence today announced details behind their collaboration to implement the first ARM Cortex-A57 processor on TSMC's 16nm FinFET manufacturing process.


Kotura establishes fabless semiconductor model

Tue, 3 Mar 2013

Kotura inks fab agreement; announces relationships with Mindspeed and BinOptics.


EU-funded SYNAPTIC project delivers design-synthesis tool flow

Mon, 3 Mar 2013

A joint industry/academia consortium, supported by the European Union's Seventh Framework Programme, has reported the successful conclusion of a three-year project and the release of its design-synthesis tool flow and related litho-friendly cell libraries and evaluation metrics.


Mentor Graphics User Conference 2013 to feature former TSMC CTO

Fri, 3 Mar 2013

Mentor Graphics User Conference 2013 speaker line-up boasts a host of industry bigwigs, including former foundry CTO, Dr. Chenming Hu.  Hu will give the keynote address on April 25 in San Jose, California, addressing the future of FinFET.


Nanoplas introduces a new class of dry-etching technology

Thu, 3 Mar 2013

Nanoplas, a global supplier of plasma processing equipment to the semiconductor industry, today announced a new dry-etch process offering virtually unlimited etch selectivity for removing dielectric films on microprocessors and memories at high throughput.


SEMATECH executive joins Intermolecular to head semiconductor group

Mon, 4 Apr 2013

Intermolecular, Inc. today announced that Dr. Raj Jammy has joined the company as senior vice president and general manager of the semiconductor group.


The secrets of 14nm lithography

Thu, 3 Mar 2013

The long-expected demise of optical lithography for manufacturing ICs has been delayed again, even though the technology itself has reached a plateau with a numerical aperture of 1.35 and an exposure wavelength of 193nm. Immersion lithography is planned for the 20/22nm node, and with the continued delay of EUV, is now the plan of record for 14nm.


ProPlus Design Solutions launches SPICE simulator for giga-scale simulations

Wed, 4 Apr 2013

ProPlus Design Solutions, Inc. yesterday launched NanoSpice, the next-generation high-capacity, high-performance parallel SPICE simulator for giga-scale circuit simulation.


"Veeco MOCVD chosen for CEA-Leti"

Tue, 4 Apr 2013

ARM and TSMC today announced the first tape-out of an ARM Cortex-A57 processor on FinFET process technology.  The Cortex-A57 processor is ARM's highest performing processor, designed to further extend the capabilities of future mobile and enterprise computing, including compute intensive applications such as high-end computer, tablet and server products.


Global semiconductor sales remain ahead of 2012 pace in February

Mon, 4 Apr 2013

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing and design, today announced that worldwide sales of semiconductors reached $23.25 billion for the month of February 2013, an increase of 1.4 percent from February 2012 when sales were $22.93 billion. Effective government policies needed to spur stronger growth.


Analysts' take: Intel's $8B push to 22nm stays in the US

Tue, 10 Oct 2010

Analysts break down Intel's $6B-$8B pledge to build and expand its US facilities to accommodate 22nm process technologies: what sites get new tools (and who gets the old ones), and why the new R&D fab's name isn't logical.


TSMC approves $1.6B for new fabs, upgrades

Tue, 5 May 2010

Chip foundry giant Taiwan Semiconductor Manufacturing Co. (TSMC) has greenlighted investments in fab infrastructure, including a new 300mm gigafab -- but there may not be any immediate capex adjustment for it, and that may be a good thing.


ConFab: A maskmaker's perspective on NGL options

Wed, 5 May 2010

Hashing out the complexity of both extending optical lithography and preparing multiple next-generation alternatives for high-volume manufacturing was the focus of a Confab talk (Tues. 5/18) by Naoya Hayashi, electronic device operations, Dai Nippon Printing Co.


SEMATECH outlines maskless issues, proposes consortium

Mon, 5 May 2010

Among key takeaways from SEMATECH's Litho Forum last week in NYC was a proposal to create a consortium to support multibeam mask writing efforts, similar to what's being done for EUV.


Improving 22nm design space with source/design optimization

Tue, 5 May 2010

Execs from Texas Instruments and Luminescent Technologies describe a "source/design optimization" technique that blends source/mask optimization (SMO) techniques with design rules, and realizes significant improvements in overall die area.


SEMI tool demand surging; B:B highest in years

Tue, 2 Feb 2010

Demand for semiconductor manufacturing equipment continues to surge as the industry emerges from its slumber, with some measurements showing strength not seen in several years, according to the latest monthly data from SEMI and SEAJ.


Analysts: Samsung, TSMC comments calm capex peak fears

Tue, 2 Feb 2010

Breaking down the quarterly numbers and forecasts from top chip spenders TSMC and Samsung, analysts determine the main thrust is that the anticipated spending cycle isn't peaking in 1H10 after all, and could instead become heavier in 2H10 and spill into 2011.


15nm-nodes-Applied-Materials development work

Fri, 11 Nov 2010

15nm Applied Materials workChristopher Bencher, member of the technical staff at Applied Materials, gave a presentation at the IEEE Bay Area Nanotechnology Council’s Half-day Symposium on process and integration-based scaling for 15nm nodes. In an interview with Debra Vogler, senior technical editor, Bencher discussed the company’s development work at 15nm.


IITC Day 3: Sub-30nm SoG gapfill, 22nm airgaps...and enforcing Zafiropoulo's Law

Tue, 6 Jun 2010

Techcet's Michael A. Fury concludes his observations from this year's IEEE International Interconnect Technology Conference (IITC) meeting near San Francisco. From Day 3: Intel's airgaps for 32-22nm, Si nanowires, more on 3D bonding and TSV schemes, electromigration in Au nano-junctions -- and enforcing "Zafiropoulo's Law."


SEMI/SEAJ May numbers: Slowing at a peak?

Mon, 6 Jun 2010

The latest monthly sales & order data for US-based and Japanese semiconductor manufacturing equipment shows growth slowing down -- and possibly because except for some pockets, it may be time for things to pull back a little bit.


ICPT 2010: CMP, new materials support push for smaller, faster, cheaper, greener ICs

Fri, 11 Nov 2010

A talk by Intel's Fab 11X manager kicking off this week's the International Conference on Planarization Technology about "challenges of manufacturing" rang true for many sectors of the chipmaking ecosystem, reports Techcet's Karey Holland.


Rigaku-EUV-lithography-optical-components-push

Wed, 11 Nov 2010

Rigaku Innovative Technologies announced further expansion into the optics market for extreme ultraviolet (EUV) lithography. RIT plans to continue supporting the industry by supplying Osmic Coatings, a line of multilayer coated optics that are essential to EUVL.


TSMC-anneal-for-gate-last-HKMG-IEDM-preview

Thu, 11 Nov 2010

TSMC anneal for gate-last HKMG process: IEDM previewLaura Peters, contributing editor, discusses TSMC's HfZrO/TiN stack, fabricated by a novel multi-deposition, multi-anneal process. TSMC will present the results at the upcoming International Electron Devices Meeting (IEDM, San Francisco, CA, December 6-8, 2010) with researchers from the Nanyang Technological University (Singapore).


Gate-first says Globalfoundries

Mon, 11 Nov 2010

Globalfoundries gate-first approach to HK+MG processingNick Kepler, Globalfoundries presenter at the IEEE Bay Area Nanotechnology Council’s Half-day Symposium, described the company’s rationale for selecting the gate-first approach to HK+MG processing. Kepler also discusses EUV lithography (EUVL) use at 20nm.


IMEC Tech Forum roundup: Expansion, germanium TPV, "electronic nose"

Tue, 6 Jun 2010

A slew of announcements and developments out of this week's IMEC Technology Forum (June 7-8, Leuven, Belgium) span the gamut from facilities expansion to GE photovoltaics and gas sensor devices.


EUVL workshop touts progress in scanners, sources, mask defects

Tue, 6 Jun 2010

Touting extreme ultraviolet (EUV) lithography as the industry's best bet to extend Moore's Law below the 2Xnm generation, experts gathered at a recent event in Hawaii described "steady progress" in source power, resist performance, mask defect reduction, and other major EUVL challenges.


Deconstructing Samsung's capex splurge

Fri, 5 May 2010

Samsung says it will spend nearly $10B in capex just for semiconductor manufacturing, and $B overall -- nearly double its initial plans, and two-thirds higher than in 2009. Analysts tell SST what's significant inside the numbers (foundry), and what it means for the rest of the industry -- and why 2011-2012 might now look a lot different.


ConFab video: Consensus, collab are key to industry progress

Thu, 5 May 2010

SEMATECH's Dan Armbrust underscores the need to determine up-front what areas are truly important to keep pushing scaling and cost-effectiveness in the semiconductor industry.


Taming the runaway computational demands of advanced lithography

Tue, 1 Jan 2010

Because of the limitations of 193nm lithography, much of the shrink capability comes from computational lithography, with software-driven advancements in optical proximity correction (OPC) and resolution enhancement technology (RET). James Word and Xima Zhang from Mentor Graphics discuss solving the computational load challenges that arise from the industry's increasing complex lithography roadmap.


Toshiba's 25nm trial ups ante for NAND scaling, next-gen litho

Tue, 4 Apr 2010

Toshiba reportedly is prepping a ¥15B (US $157M) investment in a <25nm NAND flash test line, eyeing mass production in 2012, a move that not only tightens the NAND flash scaling wars, but also could narrow the insertion point for a next-generation lithography set.


EU group takes stride toward optical interconnects

Mon, 4 Apr 2010

An EU-funded project has come one step closer to its goal of building silicon photonics circuits, with the creation of a fully CMOS-compatible laser source coupled to a silicon waveguide.


DARPA asks industry for affordable, low-volume integrated circuit manufacturing

Wed, 1 Jan 2010

Scientists at the US Defense Advanced Research Projects Agency (DARPA) are asking industry to come up with new ways of designing integrated circuits for affordable, low-volume nanofabrication for US Department of Defense (DOD) applications.


Carl-Zeiss-Synopsys-collaborate-in-die-registration-metrology-photomask manufacturing

Thu, 10 Oct 2010

carl zeiss proveCarl Zeiss SMS and Synopsys will collaborate to support in–die metrology solutions for the 32nm technology node and below. Using CATS as a data preparation engine, mask engineers using PROVE can benefit from improved efficiency and usability of a registration metrology system that meets stringent overlay accuracy requirements.


ISMI and IMEC summarize 450mm semiconductor equipment transition activities

Fri, 10 Oct 2010

In two exclusive interviews, Lode Lauwers, senior director of business development at IMEC, and Tom Jefferson, ISMI 450mm program manager, speak with Debra Vogler, senior technical editor, in advance of the SEMICON Europa 450mm session.


Crocus MRAM begins integration into TowerJazz 13um CMOC foundry process

Mon, 10 Oct 2010

TowerJazz and Crocus Technology completed the first stage of integration of Crocus’ Thermally Assisted Switching (TAS)-based MRAM technology into TowerJazz’s 0.13-µm CMOS process. As a result of the collaboration, a special low temperature back-end process technology was developed.


EUV players hit 100W output with LPP source

Tue, 4 Apr 2010

The Extreme Ultraviolet Lithography System Development Association (EUVA) says it has surpassed 100W output at intermediate focus for an EUV light source, another big step to address a big hurdle facing EUV lithography as a production-viable candidate for next-generation semiconductor manufacturing.


KLA-Tencor brings stochastic modeling to virtual tool for EUV, DPL

Mon, 2 Feb 2010

Sanjay Kapasi from KLA-Tencor tells SST how the latest-generation PROLITH virtual lithography tool, PROLITH X3.1, takes aim at the skyrocketing R&D expenses being incurred at the 1X and 2Xnm nodes, by leveraging simulations rather than printed test wafers.


SPIE Preview: EUV vs. optical battle, "alternatives" get attention

Mon, 2 Feb 2010

The SPIE Advanced Lithography Conference is where experts come to tell their advances in lithography, resists, metrology and design, and this week it appears to be heating up as a battle between optical and surging EUV, with other litho technologies offering a "sanity check," writes Griff Resor.


Status of EUV lithography for the 22nm half-pitch

Fri, 2 Feb 2010

Progress has been made on double-patterning lithography and EUV, but in the end, chipmakers must decide which technology to use based on availability, cost, and product roadmap requirements, notes Stefan Wurm from SEMATECH.


Atomic layer deposition goes mainstream in 22nm logic technologies

Mon, 11 Nov 2010
Cost-of-ownership (COO) will be a main driver for ALD equipment selection in cost-sensitive markets; and in foundry or other logic applications, equipment choice is more a mix between COO, turn-around time and process performance considerations. M. Verghese, ASM, Phoenix, AZ USA; J. W. Maes, ASM, Leuven, Belgium; N. Kobayashi, ASM, Tokyo, Japan

CD-SEM-metrology-tool-from-Advantest debuts for next-gen photomasks

Fri, 11 Nov 2010

Advantest Corporation released a SEM-based critical dimension (CD) measurement system for next-generation photomasks and patterned media. The E3630 is fully compatible with Advantest’s existing E3610/E3620 CD-SEM measurement systems and software, and boasts 30% improved linewidth repeatability.


EUVL pattern distortions allow no holiday

Tue, 11 Nov 2010

EUVL pattern distortions allow no holidayEUVL introduces new challenges to the software used to correct pattern distortions introduced by exposure, resist, and etching processes. While the low k1 of EUVL would seem to provide a bit of an OPC vendor’s holiday, it’s shaping up to be quite the opposite situation. James Word, Mentor Graphics, shows us what next-gen litho pattern distortions are, and how to correct them.


Cost-effective advanced copper metallization using ECPR

Fri, 10 Oct 2010
Electrochemical pattern replication enables fine pitch, >2:1 aspect ratio plating of near vertical sidewall copper metal features without advanced lithography; its uniformity will prove to be very attractive for both front-end of line and back-end of line metallization processes. M. Thompson, P. Möller, M Fredenberg, D. Hays, W. Van den Hoek, D. Carl, Replisaurus, Kista, Sweden

Northeastern Surface Prep 2010: EUV masks, CMP, solar cell texturing, nano-chopsticks

Fri, 10 Oct 2010

Techcet's Michael A. Fury reports from the 7th International Surface Cleaning and Preparation Workshop put on by Northeastern and Hanyang universities in Boston, with early talks involving various themes: EUV mask cleaning and chemical mechanical planarization (CMP), crystalline silicon solar cell texturing, and even nano-chopsticks.


New photolithography technology for photonics patterning from Eulitha

Wed, 10 Oct 2010

Eulitha developed a proprietary photolithography technology for low-cost and high-throughput fabrication of photonic nanostructures. Eulitha developed a proprietary photolithography technology for low-cost and high-throughput fabrication of photonic nanostructures. The patented technology enables the formation of periodic nanostructures over large areas for such applications as LEDs, solar cells, and flat-screen displays.


IEDM Reflections, Day 2: SRO for 11nm multigate CMOS, memory updates

Thu, 12 Dec 2010

Michael A. Fury continues with observations from IEDM 2010, looking at 2nd-day papers on a 90nm CMOS image sensor; an 11nm planar multi-gate CMOS design with self-assembled gates; SiC/GaN power electronics for auto systems; an update on future memory technologies; and a transparent photosensor array with triple oxide TFTs as both switches and sensor elements.


EUV litho gets boost from ASML Brion software

Tue, 9 Sep 2010

Brion Technologies, a division of ASML, debuted the Tachyon NXE software to optimize predictive modeling for ASML EUV scanners. EUV scanners enable smaller, faster, cheaper and more energy-efficient semiconductors. This article includes a podcast interview on the technology.


Accurate EUV lithography simulation enabled by calibrated physical resist models

Mon, 9 Sep 2010

Authors from Synopsys and IMEC assess the readiness of rigorous physical resist model calibration for accurate EUV lithography simulation. They discuss pattern selection for calibration, illustrate the speed and robustness of model building, and examine model validation results. Predictability of the resist model is demonstrated across various flare levels, pitches and critical-dimension ranges.Authors from Synopsys and IMEC assess the readiness of rigorous physical resist model calibration for accurate EUV lithography simulation. They discuss pattern selection for calibration, illustrate the speed and robustness of model building, and examine model validation results. Predictability of the resist model is demonstrated across various flare levels, pitches and critical-dimension ranges.


Anti-fuse memory cell patent granted to Sidense

Mon, 8 Aug 2010

Sidense, developer of logic non-volatile memory (LNVM) IP cores, announced that the USPTO granted Sidense Patent Number 7,755,162, "Anti-fuse Memory Cell." The '162 patent adds to the Company's patent portfolio covering its 1T-Fuse memory technology.


Avoid throwing darts at a black hole by using diagnosis-driven yield analysis

Thu, 7 Jul 2010
Layout-aware scan diagnosis combined with dedicated statistical analysis is an effective diagnosis-driven yield analysis flow. Geir Eide, Mentor Graphics Corp.

DUV inspection and defect origin analysis for 22nm spacer self-aligned double-patterning

Thu, 7 Jul 2010
Tracing defects from the lithography step through the SADP process flow to the spacer open step can significantly increase the capture rate of critical defects at the earlier steps. Ofir Montal, et al, Applied Materials Inc.

Research updates on EUV, mask, cleaning, etc from Leti

Fri, 7 Jul 2010

In these three video interviews from SEMICON West 2010, Leti research directors speak with senior technical editor Debra Vogler. Yannick Le Tiec discusses cleaning; Michel Brillouet speaks on 3D packaging work, and Didier Louis updates us on advanced lithography.


ASML: Exposure tool development for EUV

Thu, 7 Jul 2010

In this video, Hans Meiling, ASML, touches on EUV's three required three components: process (resist), mask infrastructure and metrology, and exposure tool.


Imec EUV mask cleaning program on track towards EUV mass manufacturing

Wed, 7 Jul 2010

Imec reports promising results in its extreme ultraviolet lithography (EUV) mask cleaning program for defect-free EUV masks that are crucial in achieving high chip manufacturing yield.


EUV news from SEMICON West with Toppan Photomasks

Tue, 7 Jul 2010

In this video interview, Franklin Kalk, Toppan Photomasks, comments on the big EUV news annouced at SEMICON West. Technical challenges of EUV remain defect management -- finding and fixing defects in masks. Pattern mask inspection may not be ready until 2016.


SEMICON West: Lithography trends at Sokudo breakfast forum

Thu, 7 Jul 2010

CEA-Leti's Laurent Pain and Didier Louis report from Sokudo's annual Lithography Breakfast at SEMICON West, where this year's forum addressed challenges and development needs for the 22nm node, and updates on 193nm and potential successors EUV and maskless.


Imec and ASML demonstrate potential of 193nm immersion lithography with freeform illumination

Wed, 7 Jul 2010

Imec and ASML collaborated to qualify ASML’s Tachyon Source Mask Optimization and programmable illuminator system FlexRay, proving its potential with the demonstration of a 22nm SRAM memory cell. In October 2010, the ASML XT:1900i lithography scanner at imec will be equipped with FlexRay, enabling imec to explore the ultimate frontiers of immersion lithography.


New method creates super-thin, high integrity, continuous metal lines that surpass semiconductor industry requirements

Thu, 7 Jul 2010

Scientists from Singapore A*STAR’s Institute of Materials Research and Engineering, University of Cambridge, and Sungkyunkwan University created thin metallic lines with line width roughness below the 2010 targets. The researchers used an organometallic material and a combination of electron beam lithography and subsequent gas treatment to easily chip away the organic portions in a uniform manner, leaving the desired metallic patterns.


SPIE 2010: Litho future getting too close to call

Mon, 3 Mar 2010

Based on talks and presentations from the SPIE Advanced Lithography Conference, the future for IC manufacturing is still very much unclear, writes Griff Resor. How close is optical litho to finally reaching its limits? Has the time has come to switch to a replacement technology like EUV, and what still needs to be accomplished?


SPIE 2010: Spring training for litho

Wed, 3 Mar 2010

Toppan Photomask's Franklin Kalk handicaps the litho field, mapping their abilities and potential to professional baseball teams as the new season approaches. (And yes, it comes down to the Red Sox and Yankees.)


SPIE takeaway: Updated litho shipments, and EUV-delay misinterpretations

Tue, 3 Mar 2010

Barclays Capital's CJ Muse came away from SPIE with the message that litho demand is strong, with a "heightened focus on EUV" due to increased costs associated with double patterning -- and why rumors about a delay in EUV adoption may not be accurate after all.


SPIE Roundup: EUV/EBMI demo, 11nm NIL, ASML's EUV roadmap, the skinny on DOE...

Tue, 3 Mar 2010

Several discussions and presentations at last week's SPIE Advanced Lithography Conference deserve special note -- from work with e-beam EUV mask inspection, to nanoimprint achievements (11nm!), an EUV tool platform roadmap, mask productivity and cost issues at 22nm, and more on SMO and tunable DOEs.


Entegris details progress on microbridging defects, lens haze

Tue, 3 Mar 2010

Entegris execs summarize two poster papers from the SPIE Advanced Lithography Conference that covered the company's methods to detect ppt levels of trimethylsilanol (TMS), and evaluating microbridging defects in which 5nm filtration was compared to 3nm filtration levels.


Video interview with Entegris: Contamination control at 22nm and below

Fri, 7 Jul 2010

Christopher Wargo, Entegris, talks contamination control at 22nm and below. Lithography presents a suite of issues for contamination control. While the technology exists to confront new contaminants, commercialization is key.


In a challenging year, 26 suppliers earn Intel kudos

Wed, 3 Mar 2010

Intel has given its nod to two dozen key partners from its roster of thousands of supply-chain contributors as the 2009 winners of its annual supply chain awards -- and within the listings is a interesting nugget about the chipmaker's lithography strategy.


Analyst: More evidence in KR, TW supports extended chip capex

Fri, 3 Mar 2010

Checks into key chipmakers in Korea and Taiwan suggest current demand for equipment is still on the rise, with planned capex increases imminent and capacities set to increase into 2011, according to one industry analyst.


ASMC: Inside yield enhancement & methodologies

Wed, 7 Jul 2010

Gary Green, co-chair of the yield enhancement/methodologies sessions at this week’s Advanced Semiconductor Manufacturing Conference (colocated with SEMICON West), reviews key themes discussed, including techniques aimed at faster root cause analysis, new methods in analyzing contact failures using e-beam and TEM tools, and increasing test coverage while reducing the number of test wafers.


Chip makers adopt ASML Holistic Lithography

Tue, 7 Jul 2010

ASML Holding NV (ASML) announced broad customer adoption of holistic lithography products that optimize semiconductor scanner performance and provide a faster start to chip production. All of ASML’s leading-edge scanners are now sold with one or more holistic lithography components.


Etch pushes limits of physics and chemistry

Thu, 7 Jul 2010
Richard A. Gottscho, Lam Research Corp.,

SEMICON West Lesson #4: Supply chain challenges

Mon, 7 Jul 2010

Wrap-up of what we heard and saw at SEMICON West 2010. Lesson 4: The semiconductor/equipment/component supply-chain went from ice-cold to red-hot in a matter of months, which brings its own unique challenges to the industry.


IBM's Meyerson: Finding where (our) innovation matters

Tue, 7 Jul 2010

 Innovation drives everything -- and innovation spawned from the semiconductor and related industries is poised to do nothing less than change the world, or at least help everyone adapt better to it, as related by SEMICON West kickoff keynoter Bernie Meyerson of IBM.


Analysts' take: AMAT 3Q10 numbers, marketshare gains and flash dreams

Fri, 8 Aug 2010

Analysts break down some of the more important points of Applied Materials' 3Q10 numbers and discussions. Key takeaways: A few key marketshare wins, NAND flash is about to explode, and any macro sluggishness hasn't materialized yet in chip tool demand.


Analyst: DRAM growth hinges on litho readiness, 4Xnm migration

Fri, 8 Aug 2010

DRAM memory "turbulence" might rear its head in 2H10 with supplies falling short of demand, because of manufacturers' problems in migration to newer processes and unable to obtain key pieces of leading-edge equipment, according to iSuppli.


SEMICON Europa lithography session preview with speakers

Mon, 9 Sep 2010

In a series of podcasts, 3 of the presenters at the SEMICON Europa Lithography session speak with senior technical editor Debra Vogler. Interviewees include consultant Wolfgang Arden, Rolf Seltmann of Globalfoundries, and IMEC's Roel Gronheid.


SEMICON Europa plans more than 40 programs/events: Peruse the semiconductor track

Fri, 9 Sep 2010

The Semiconductor front-end track of SEMICON Europa includes the 14th Fab Managers Forum; and sessions on lithography, automation and process control, metrology, new materials, secondary equipment/services, and a progress review of 450mm.


Terabit HDD recording goal of new Toshiba bit patterning

Thu, 9 Sep 2010

Toshiba details its use of bit-patterned media to fabricate a hard disk with an areal density of 2.5 terabits per-square-inch and a practical servo pattern. According to the company, BPM technology is a leading candidate to achieve terabit-class high density HDD recording. This article includes a podcast interview on the technology.


Multiple E-Beam lithography project gains SOKUDO as member

Thu, 9 Sep 2010

Dainippon/AMAT JV SOKUDO Co. Ltd., lithography coat/develop track, and process equipment company, will join the new industry/research multi-partner program IMAGINE (led by CEA-Leti), developing maskless lithography for IC manufacturing.


eBeam Initiative plans BACUS talk on DFEB mask, announces new members

Wed, 9 Sep 2010

The eBeam Initiative has several members jointly presenting the latest breakthroughs in DFEB mask technology at the SPIE/BACUS Symposium. The collaborative results demonstrate the effectiveness of DFEB mask technology on advanced photomasks at the 22-nm node and beyond. The eBeam Initiative has several members jointly presenting the latest breakthroughs in DFEB mask technology at the SPIE/BACUS Symposium. The collaborative results demonstrate the effectiveness of DFEB mask technology on advanced photomasks at the 22-nm node and beyond. This article includes a podcast interview with the presenters.


Which-transistor-path-FinFET-tri-gate-FDSOI-Ge/III-V-bulk-CMOS

Tue, 12 Dec 2010

podcast interviewWhich transistor structures and materials will garner the most support at 16nm and below? In this podcast interview, Dean Freeman, VP of research, Gartner, provides his perspective on the various paths: FinFETS, tri-gates, fully-depleted SOI (FDSOI), Ge/III-V, bulk CMOS, and so on.


DRAM-pricing-collapse-update-from-iSuppli

Tue, 12 Dec 2010

DRAM pricing. Source: iSuppliPC makers are jamming cheap DRAM into systems, as pricing reaches critical levels. Watch for DRAM makers at 6x-nm and 5x-nm nodes to become inefficient, warns iSuppli. DRAM prices are expected to remain critical until at least H2 2011.


Dai Nippon, SEMATECH semiconductor lithography printing collaboration will to develop advanced processes at UAlbany NanoCollege

Fri, 8 Aug 2010

Under the agreement, a team of mask cleaning experts from Dai Nippon will work with experts from SEMATECH’s Mask Clean program at CNSE’s Albany NanoTech Complex to improve the cleaning yield on extreme ultraviolet (EUV) lithography patterned, non-patterned substrates and nanoimprint lithography (NIL) templates.


Overlay error components in double-patterning lithography

Sun, 8 Aug 2010
Wafer selection at the beginning of a process could help minimize the effects of shape changes during the wafer processing that may affect overlay error. Venkat R. Nagaswami, et al, KLA-Tencor Corp., Milpitas, CA

Reticle haze control: Global update and technology roadmap

Tue, 8 Aug 2010

Oleg Kishkovich, Tom Kielbaso, David Halbmaier, Entegris Inc., present analysis of a method for controlling AS haze, maintaining 193nm reticles in low-humidity lithography environments in HVM fabs. Critical reticle haze control elements and limiting factors are delineated.


Mask and template inspection: Production-worthy mask inspection for emerging nodes

Wed, 8 Aug 2010

EUV KLA-Tencor Lithography actinic mask inspection technical feature.Actinic EUV inspection preserves the production paradigm with acceptable cost-per-inspection despite higher capital costs. Its development path is clear and achievable in time to meet technical and economic requirements for 16nm-hp production in 2015. Brian Haas, Gregg Inderhees, KLA-Tencor Corp., explain key elements of mask inspection and what actinic EUV inspection provides.


Video interview with SEMATECH: EUV on center stage

Fri, 8 Aug 2010

In this video interview, Bryan Rice, SEMATECH, discusses the readiness of EUV. SEMATECH is partnering with Carl Zeiss for EUV process development. The next phase will be a blank inspection phase, beginning a few months after SEMICON West.


Six takeaways from GlobalFoundries sitdown

Wed, 9 Sep 2010

Accelerated capital spending, process technology roadmaps, and customer adoptions were among several key trends gleaned by Credit Suisse analyst Satya Kumar from GlobalFoundries' recent technology conference.


Applied-Materials-photomask-etch-tech-for-22nm-lithography

Mon, 9 Sep 2010

Applied Materials (AMAT) launched its new Applied Centura Tetra X Advanced Reticle Etch system capable of etching photomasks needed for challenging device layers at 22nm and beyond.Applied Materials (AMAT) launched its new Applied Centura Tetra X Advanced Reticle Etch system capable of etching photomasks needed for challenging device layers at 22nm and beyond. Expanding the capabilities of AMAT's Tetra III platform, the Tetra X breaks the 2nm critical dimension uniformity (CDU) barrier across all feature sizes.


Photomask for wafer fab: A look at the industry's structure

Fri, 9 Sep 2010

Franklin Kalk, Toppan Photomask, examined the photomask industry structure and how it determines industry profitability. Consider: the threat of new entrants (that is, other firms entering the market to compete against the incumbents), the bargaining power of suppliers and of customers, the threat of substitutes (that is, products that might replace photomasks), and rivalry among the existing lithography firms. This article includes an in-depth podcast about the photomask industry.


Nanoimprint collaboration from AMO and SUSS MicroTec leads to UV-SCIL breakthroughs

Wed, 10 Oct 2010

SCIL Suss Amo nanoimprint silicon master.AMO GmbH and SUSS MicroTec AG are developing applications for substrate conformal imprint lithography (SCIL) with UV curing material. Due to unique sequential contacting and separation technology, a distortion-free replication of a stamp at high throughput is now possible with UV-SCIL.


Lithography materials infrastructure benefits from a collaborative research approach

Fri, 10 Oct 2010

SEMATECH's lithography tool and process development from Solid State TechnologyAdvances in lithographic patterning critically depend on the timely availability of enabling resists and materials, say Warren Montgomery and Stefan Wurm, SEMATECH. They detail the toolset and collaborative approach of SEMATECH, which helps bridge the lapse between basic research and wafer fab production processes to keep lithography moving forward. What has the research organization's attention in 2010?


Enhanced particle detection unit goes down to 5um defects

Thu, 10 Oct 2010

Enhanced particle detection unit goes down to 5um defectsAnswering the growing demand for a high resolution, Dr. Schenk has developed an enhanced version of the Pollux Particle Detection System for Photomasks. Pollux-Enhanced automated particle detection system enables fabs to perform a complete inspection on each reticle prior to its use.


The end of DRAM manufacturing cost gains?

Thu, 9 Sep 2010

DRAM manufacturing costs are on the rise for the first time in four years, raising questions about production expenses in the memory industry, but things should improve in a few quarters, according to a new report from research firm iSuppli.


GLOBALFOUNDRIES 28nm analog/mixed-signal production design flow kit out soon

Wed, 9 Sep 2010

GLOBALFOUNDRIES teamed with Cadence Design Systems to create an open-access 28nm Analog/Mixed-Signal (AMS) production design flow development kit.


IMEC discusses major projects at SEMICON West

Thu, 8 Aug 2011

Ludo Deferm, IMEC, came to SEMICON West with several major announcements, from the system level to the layers of semiconductors. IMEC's major interests include scaling with 3D technologies, selective epitaxy, RRAM, lithography, and more.


SEMICON West 2011: New product roundup

Wed, 7 Jul 2011

SEMICON West may not be the big-iron displayfest it once was, but there are still plenty of new product introductions to go around. Here's just a brief rundown of some of the ones we tracked from this year's show.


How EVG accomplished the 1st 450mm printed wafer; HVM expected 2015-2017

Mon, 7 Jul 2011

SEMATECH announced a 450mm imprinted wafer, accomplished by EV Group (EVG). Markus Wimplinger, EVG, described the timeline for the 450mm effort and how the company decided to make a strategic move.


Gigaphoton's EUV debris mitigation tech acheives 93% Sn removal

Fri, 7 Jul 2011

Lithography light source maker Gigaphoton Inc. verified its original technology for mitigating debris with magnetic fields for laser-produced plasma (LPP) light sources, clearing a hurdle for mass-production use.


A lithography-rich Day 2 at SEMICON West

Thu, 7 Jul 2011

Intermolecular's George Mirth reports on interesting keynote speeches and comments from the Sokudo Lithography Breakfast at SEMICON West, in talks from ASML, Nikon, Mapper, Xtreme, and imec.


Imec ITF: 2011 is "the year for EUV to prove its readiness"

Wed, 5 May 2011

In an SST-exclusive series of blogs, imec reports from its International Technology Forum this week in Brussels. Geert Vandenberghe talks about how EUV lithography is at a readiness crossroads, but he feels "fairly secure" about its current capabilities.


Connecting investments to industry trends

Tue, 5 May 2011

Bob Krakauer, CFO of GlobalFoundries, summarized industry trends in manufacturing and end-applications, a changing foundry landscape, and his company's own long-term investments in semiconductor manufacturing, in his Confab presentation.


Bring lithography <11nm with materials, not new steppers, says Brewer Science

Tue, 5 May 2011

New innovative processes and materials could be the least costly way to get to <10nm lithography, says Lori Nye, Brewer Science, at The ConFab. With the right use of materials, one can go 2 or 3 nodes beyond currently accepted lithography limits on exposure tools.


Customers, logic reshaping supplier collaboration landscape

Tue, 5 May 2011

Harvey Frye, vice-chairman of TEL America, summarized the new supplier landscape in his Confab talk, taking both a macro point of view of trends, and how his company as a top supplier is addressing them: collaboration among suppliers, and an increasing focus on consumer needs.


Photoresist market snapshot for semiconductor fab

Thu, 6 Jun 2011

Photoresist revenues will grow at about 5% for the next several years, says Techcet Group. Consolidation is long overdue among resist suppliers, and EUV may be the last straw. For materials, supply is abundant.


KLAC joins SEMATECH EUV efforts

Tue, 6 Jun 2011

KLA-Tencor will join SEMATECH-led efforts to identify and eliminate defects in EUV lithography, including mask metrology infrastructure and metrology source development.


High-productivity materials development for post-via etch residue removers

Wed, 6 Jun 2011
Utilizing a high-productivity combinatorial technique, the best formulation and process window for post-via etch residue removers was determined. Rekha Rajaram, et al., Intermolecular Inc.; Barry Chen, et al.,ATMI, Inc., Danbury, CT and Round Rock, TX

IBM builds IC with graphene transistor

Mon, 6 Jun 2011

IBM researchers built an integrated circuit (IC) fabricated from wafer-scale graphene on SiC, integrating a graphene transistor with other electronics circuits.


Extending optical lithography with complementary e-beam lithography

Mon, 7 Jul 2011

David Lam summarizes how the industry does not have to "throw out" optical lithography as it proceeds to more advanced nodes -- complementary e-beam lithography (CEBL) is part of the overall solution, "complementary lithography," that can overcome the resolution limitations of 193i technology.


SEMICON West keynotes cover research, chip design, packaging

Tue, 6 Jun 2011

Tien Wu, ASE; Rama K. Shukla, Intel; and Luc Van den hove, imec, are the honored presenters for SEMICON West 2011.


CEA-Leti Annual Review: IDMs' top 3 challenges

Tue, 6 Jun 2011

At CEA-Leti's Annual Review, STMicroelectronics CTO Jean-Marc Chery reviewed the challenges facing IDM companies focused on SoC markets, and the three primary challenges for IDMs: FinFETs, EUV lithography, and 450mm.


CEA-Leti Annual Review: Update on maskless litho work

Tue, 6 Jun 2011

At CEA-Leti's Annual Review, Leti lithography program manager Serge Tedesco described the IMAGINE industrywide project to assess maskless multi e-beam technology, including the system's expected capabilities within two years.


Lithography cost-of-ownership considerations

Mon, 6 Jun 2011

The semi industry faces major cost challenges in patterning advanced ICs in high volumes. A cost-effective solution remains elusive. David K. Lam, Multibeam Corporation, addresses lithography cost-of-ownership.


Heidelburg Instruments options circuit-shrinking lithography tech

Fri, 6 Jun 2011

Heidelberg Instruments optioned University of Colorado Boulder's technique for shrinking copper circuits by zapping a substrate with two separate colors of light beams.


New architectures, litho schemes take the stage at SEMICON West

Fri, 6 Jun 2011

Two TechXPOT sessions at SEMICON West will address the new architectures needed to continue scaling both logic and memory devices, as well as the major challenges facing lithography both for EUV and options for extending 193nm immersion.


Trigate transistors vs FDSOI

Thu, 7 Jul 2011

Dick James, ChipWorks, speaks about Intel's presentations on strain engineering and lithography masks for trigate transistors, and the industry split between FDSOI and trigates.


SUSS EUV lithography mask management system debuts with imec install

Wed, 7 Jul 2011

SUSS MicroTec unveiled MaskTrack Pro InSync, a holistic in-fab EUVL mask management product that synchronizes mask cleaning, handling, inspection, and storage.


Cymer talks EUV, TCZ, light source monitoring upgrade

Wed, 7 Jul 2011

Nigel Farrar, Cymer, provides a status report on EUV lithography source technology, extensions to ArF lithography, the laser crystallization process from the company's TCZ display equipment product division, and Cymer's newest DUV source product the OnPulse Plus data monitoring system.


EUV lithography infrastructure update from SEMATECH

Wed, 7 Jul 2011

Stefan Wurm, SEMATECH, discusses EUV lithography's infrastructure. Want milestones? The first EUV litho beta tools have been delivered, and now the motivation is increasing throughput and reducing defects.


Top semiconductor metrology challenges from SEMATECH POV

Wed, 7 Jul 2011

At SEMICON West 2011, Phil Bryson, SEMATECH, covers the top challenges in semiconductor metrology at advanced nodes.


ASML tweaks immersion tool to improve imaging, overlay

Wed, 7 Jul 2011

ASML has added three extensions to its Twinscan NXT 1950i tool, to improve imaging, overlay, and system throughput.


Novellus uncrates conformal films for sub-2Xnm

Wed, 7 Jul 2011

The Conformal Film Deposition (CFD) suite of dielectric films consists of oxide, doped oxide and nitride films that are deposited below 450

Suss joins imec's EUV mask integrity work

Tue, 7 Jul 2011

Suss Microtec and imec are expanding a research collaboration in mask cleaning to develop an in-fab approach to EUV lithography mask integrity, aiming to develop a sophisticated approach to preserving mask integrity prior to exposure.


ASM covers FinFET precursor needs from epitaxy to HKMG ALD

Fri, 7 Jul 2011

ASM International's Bob Hollands discusses the challenges of making FinFET structures using both epitaxial and high-k/metal gate (HKMG) atomic layer deposition (ALD) processes.


Sokudo litho breakfast: Challenges for the 2Xnm node

Wed, 7 Jul 2011

CEA-Leti's Serge Tedesco and Didier Louis summarize key themes from the Sokudo lithography breakfast forum held last week at SEMICON West.


Litho readiness for next-gen logic, flash, and DRAM

Tue, 7 Jul 2011

Franklin Kalk, Toppan Photomasks, covers the major lithography demands of distinct semiconductor technologies: Logic, Flash, and DRAM. He also gives an update on fabless/foundry options, and Japan's earthquake recovery.


Mask-wafer double simulation: A new lithography requirement at 22nm

Fri, 12 Dec 2011

Accurate mask-wafer double simulation is a new, required step for lithography at the 20nm node and beyond because corner rounding becomes the dominant effect, explains Aki Fujimura, D2S.


IEST cleanroom apparel doc update includes measurement guide

Thu, 12 Dec 2011

The updated "Garment System Considerations for Cleanrooms and Other Controlled Environments" document includes new sections on measuring footwear, frocks and other garments, as well as a new subsection for tracking system use, such as RFID chips and barcodes.


EVG installs UV-lithography system at Asahi Kasei

Tue, 12 Dec 2011

Asahi Kasei E-Materials Corporation purchased an IQ Aligner UV nanoimprint lithography (UV-NIL) system from EV Group (EVG).


TEL, ASML develop EUV and other advanced lithography tech

Wed, 11 Nov 2011

Tokyo Electron Limited (TEL) and ASML Holding NV (ASML) will accelerate joint development activities in extreme ultraviolet (EUV) and argon fluoride (ArF) immersion lithography clusters.


GLOBALFOUNDRIES names CFO from ATIC

Wed, 11 Nov 2011

Under new CEO Ajit Monocha's realignment plan, GLOBALFOUNDRIES named new CFO, CTO, and customer engineering and quality leaders. The CTO position is a new one at the semiconductor foundry. The moves are meant to separate technology strategy from technology development.


Nvidia's ConFab keynote will portray "the virtual IDM"

Tue, 11 Nov 2011

Dr. John Chen, VP of technology and foundry operations at Nvidia, and Thomas Jefferson, ISMI's 450mm project manager, are among the updated speaking roster of ConFab 2012, which will address the economics of semiconductor manufacturing and associated industries (LEDs, MEMS, displays).


Cymer's ArF lithography gas control ups productivity, drops fluorine gas consumption

Tue, 11 Nov 2011

Cymer Inc. (Nasdaq:CYMI) revealed the third-generation Gas Lifetime eXtension (iGLX) control system for argon fluoride (ArF) immersion light sources used in semiconductor lithography.


MENT, JEOL optimize multi-resolution IC mask writing process

Thu, 11 Nov 2011

Mentor Graphics and JEOL will collaborate on multi-resolution mask writing for shot count reduction of up to 30% compared to the conventional writing technique for IC lithography masks.


Chip fab tool book-to-bill holds steady for North American makers

Fri, 11 Nov 2011

"The recent period

Intermolecular (IMI) prices IPO

Fri, 11 Nov 2011

Intermolecular Inc. (Nasdaq:IMI) priced its initial public offering of 9,650,000 shares of common stock at a public offering price of $10.00 per share.


North American chip fab tool book-to-bill up in November

Fri, 12 Dec 2011

North America-based manufacturers of semiconductor equipment posted $973.3 million in orders in November 2011, $1.17 billion in billings, and a book-to-bill ratio of 0.83, according to the November Book-to-Bill Report from SEMI.


Worldwide semiconductor equipment bookings decline in Q3

Tue, 12 Dec 2011

SEMI reports worldwide semiconductor manufacturing equipment bookings fell 38% year-over-year in Q3 2011; billings dropped 5% for the same quarter.


Nikon ArF lithography tool boasts 2x throughput

Thu, 12 Dec 2011

Nikon Corporation released its NSR-S320F argon fluoride (ArF) lithography scanner for advanced 20nm node semiconductor device manufacturing. It boast high productivity and high accuracy, with stable operation in the field, Nikon reports.


Frontend process, materials firms get high marks from TSMC

Wed, 12 Dec 2011

A number of big-name frontend equipment firms highlight TSMC's annual supplier awards in 2011, as the foundry expands its list of top suppliers.


Inside Intel's numbers: What the capex surge means

Mon, 1 Jan 2011

Historically countercyclical-investing Intel is up to its old tricks, pledging a massive record spending spree in 2011. We break down all the numbers and what they mean, from exec statements and Q&A comments to what key industry analysts think.


ASMC 2011: EUV, image sensors, and a capital perspective

Thu, 5 May 2011

The last day of this week's SEMI/IEEE Advanced Semiconductor Manufacturing Conference (ASMC) featured talks on EUV readiness and hurdles, CMOS image sensors' increasing complexity, embedded memory failure analysis to improve yields, and a coming shift from chip technology efficiency back to innovation.


ASMC 2011: Rain doesn't damper the spirit

Tue, 5 May 2011

Intermolecular's John Behnke offers his impressions from Day 1 of this year's SEMI/IEEE Advanced Semiconductor Manufacturing Conference (ASMC) in New York. Highlights: a keynote from a suddenly famous GlobalFoundries exec, on-the-fly edge inspection, equipment health monitoring, and a TSV overview.


EUV, DSA ready at 11nm

Wed, 5 May 2011

Describing work being done at Albany Nanotech, IBM's Dave Medeiros listed the new anticipated due-date for EUV lithography (11nm), and what other lithography option might be ready as an alternative technique around that same time.


Making progress with EUV

Wed, 5 May 2011

imec's An Steegen outlined the requirements to continue Moore's Law and new technologies being pursued to that end. Perhaps most important is lithography, where she provided an update on EUV tool productivity, resist benchmarking, and mask defect results.


KLAC: Yields are key to low costs, in traditional chips and emerging LEDs

Tue, 5 May 2011

High performance and low power consumption are expected of today's chips and LEDs. Today's chip makers still expect to keep their costs down. The key to making this work, says Brian Trafas, KLAC, is yield optimization. Trafas, speaking at The ConFab 2011 in Las Vegas, touches on tool supplier/user collaborations as well.


Wafer fab roadmap below 10nm: imec at The ConFab

Thu, 5 May 2011

An Steegen, imec, shares how imec is helping enable Moore's Law's continuation to <10nm. Moore's Law through 19nm could be lithography-enabled, Steegen says, but past that point we need to rely on materials, such as high-k, and new device architectures. She also provides an update on imec's EUV progress.


Surface preparation for 2011 and beyond

Fri, 4 Apr 2011
Surface clean engineers must discover new methods to realize contamination and surface termination requirements at each step of the manufacturing process, while simultaneously considering the impact to health, cost and the environment. Joel Barnett, SEMATECH, Austin, TX, USA

Pioneering new devices and materials for future ICs

Sun, 5 May 2011
It is expected that from the 15nm node on, the industry will need to adopt new transister architectures; among the contenders: FinFETs and TunnelFETs. Thomas Hoffmann, imec, Leuven, Belguim

BEOL technology at 20nm half-pitch

Sun, 5 May 2011
New approaches to patterning, low-k and metallization are reviewed for 20nm hp interconnects. Gerald Beyer, Zsolt Tokei, imec, Leuven, Belgium

Ultratech plans HB-LED dev center in Taiwan

Thu, 5 May 2011

Ultratech, Inc. (Nasdaq: UTEK) announced an Asia Technology Center (ATC) in Taiwan to develop processes for HB-LED manufacture on its Sapphire 100 lithography system.


Gap measurement tech from Novellus' Peter Wolters benefits from sensor, algorithm advances

Tue, 5 May 2011

Figure 3. Gap profile control on the GBIR measurement.Novellus Systems (NASDAQ: NVLS) subsidiary Peter Wolters GmbH introduced innovative gap measurement technology for double-side silicon prime wafer polishing. New high-resolution sensors and software algorithms increase control of wafer quality, as well as throughput for the AC2000-P3 system.


Terry-Brewer-Brewer-Science-profile

Fri, 3 Mar 2011

Terry Brewer, Brewer Science"You can't approach the future by predictions. You approach the future by making it happen," Terry Brewer, founder/president of Brewer Science, says. And this mindset carries over into real-world results for the semiconductor industry, he points out: "EUV will happen if we want to make it happen."

 


SPIE 2011: Where are we now with EUV?

Wed, 3 Mar 2011

What does the industry have to show so far from its mountainous investments in EUV? Reporting from the SPIE Advanced Lithography conference, Franklin Kalk from Toppan Photomasks examines several papers summarizing EUV progress and challenges, and pins current work somewhere between "science project" and "a long way to go."


Nanometrics-launches-overlay-metrology-system-wins-Asia-order

Tue, 3 Mar 2011

Nanometrics Incorporated (Nasdaq:NANO), advanced process control metrology provider, launched the Mosaic II turnkey image-based overlay metrology solution for advanced high-volume IC manufacturing. NANO reports an initial delivery to a leading Asian memory customer.


EUV-resists-multibeam-lithography-chat-with-imec

Thu, 3 Mar 2011

At SPIE Advanced Lithography, Kurt Ronse, director of lithography at imec, discussed with Debra Vogler the research center's new ASML pre-production EUV scanner, EUV readiness with source power (still a concern) and resists (practically there). He also discusses the perhaps overlooked topic of pattern collapse.


EUV-lithography-vs-EBDW-Toppan-Photomasks-at-SPIE

Tue, 3 Mar 2011

Franklin Kalk, CTO of Toppan Photomasks, tells ElectroIQ's Debra Vogler, senior technical editor, where the current hurdles are for EUV mask work, the pros and cons of EUV vs. e-beam direct write (EBDW), and why there hopefully is room for both technologies -- which isn't great news for foundries.


Cymer-focus-drilling-for-immersion-light-sources-improves-depth-of-focus-by-2x

Wed, 3 Mar 2011

Cymer Inc. (Nasdaq: CYMI) introduced a focus drilling technology for its immersion light sources including the XLR 600ix, XLR500i, XLA 400 and XLA 300. Focus drilling provides up to a 2X improvement in the depth of focus on the wafer.


Cymer-EUV-source-timelines-and-DUV-highlights

Thu, 3 Mar 2011

Cymer shows lithography tool cost of ownership reductionNigel Farrar, Cymer, provides an update on EUV source technology, DUV lithography, laser lifetimes with gas improvements, and the company's product release at SPIE Advanced Lithography, Focus Drilling. He speaks with senior technical editor Debra Vogler.


Carl-Zeiss-photomask-registration-correction-system-RegC-debuts

Wed, 3 Mar 2011

Carl Zeiss RegCCarl Zeiss introduced a new production tool aimed to improve registration and overlay of advanced photomasks. RegC is based on ZEISS femtosecond-laser technology. RegC enables correction on high-end photomasks for remaining registration errors after the pattern generation process. Current results show registration improvements over 50% in advanced lithography.


austriamicrosystems-sends-high-voltage-0.18micron-CMOS-process-to-volume-production-at-IBM

Wed, 3 Mar 2011

austriamicrosystems (SIX:AMS) conditionally released its advanced 0.18µm High-Voltage CMOS process technology "H18" to for volume production. It will be manufactured in IBM's 200mm Burlington wafer facility.


VLSI: Slight shuffles in WFE vendor rankings

Wed, 3 Mar 2011

Every top-10 wafer-fab equipment supplier in VLSI Research's annual rankings remained on the list in the new 2010 version, but there were some position changes.


Analysts' take: Intel's four trigate transistor triumphs

Thu, 5 May 2011

As a follow-up Intel's announcement of a new 22nm trigate transistor structure, we polled and tracked multiple industry watchers for their thoughts on the technology. Their key takeaways: Intel reasserts its manufacturing prowess, and could be setting up for plays in mobile and foundry.


ASM plasma-enhanced atomic layer deposition (ALD) ordered for HVM, new app

Thu, 4 Apr 2011

ASM International N.V. (NASDAQ: ASMI) received multiple system orders for its plasma enhanced atomic layer deposition (PEALD) reactor from a leading memory customer in Asia. The company also qualified a new PEALD oxide application with a memory manufacturer for the 2X nm node.


IBM's double-exposure patterning creates BEOL interconnects beyond 22nm

Thu, 4 Apr 2011

Figure. Via chain SEM cross-section along M1 line direction (upper) and along M2 line direction (lower).Shyng-Tsong Chen, lead integrator for back-end integration at IBM (Albany Nanotechnology Center), will be presenting "64nm pitch Cu dual-damascene interconnects using pitch-split double-exposure patterning scheme" at the IITC 2011 Conference. This technology will be needed for BEOL interconnects beyond 22nm devices.


RRAM developer joins SEMATECH to prototype NVM technologies

Thu, 4 Apr 2011

4DS will collaborate with engineers from SEMATECH's memory program to build a full transistor-memory, demonstrating a working prototype of a low-power RRAM device.


Semiconductor capex not slowing down in 2011, say analysts

Mon, 4 Apr 2011

Two analyst reports review just how prosperous 2010 was for most (but not all) semiconductor capital companies, and how 2011 is shaping up to be even better -- even with ramifications from Japan's earthquake/tsunami disaster.


GLOBALFOUNDRIES-imec-partner-on-sub-22nm-GaN-on-Si

Mon, 4 Apr 2011

GLOBALFOUNDRIES, semiconductor foundry, signed a strategic long-term partnership on sub-22nm CMOS scaling and GaN-on-Si technology with the nanoelectronics R&D center imec.


The-physics-behind-Gigaphoton-EUV-source-technology

Fri, 3 Mar 2011

Gigaphoton SPIE podcastGigaphoton released the latest developments in its EUV source program at this week’s SPIE Advanced Lithography conference. The company reported achieving a 3.3% CE with tin droplets <20µm in diameter with its plasma-based LPP.


Ushio hands Gigaphoton EUV JV to Komatsu

Wed, 4 Apr 2011

By transferring all ownership in the litho source JV with Komatsu, Ushio and Gigaphoton can go thier separate ways with EUV source development.


Imec CNT research: IITC preview

Mon, 4 Apr 2011

after barrier deposition and Cu fillImec researchers will present "Carbon nanotube interconnects: electrical characterization of 150nm CNT contacts with Cu damascene top contact" at IITC 2011. Dr. Marleen van der Veen, senior research scientist at imec discussed the research results and their significance.


Picosun launches plasma enhanced atomic layer deposition source, records global sales

Tue, 4 Apr 2011

Picosun Oy has launched production of plasma enhanced ALD (PEALD) systems based on a highly advanced ion-free remote plasma source, Picoplasma. Various excited species such as oxygen, nitrogen and hydrogen radicals with zero charge can be generated to broaden the range of ALD process chemistries.


Tighter chip densities tease out litho, metrology weaknesses, says Intel

Thu, 5 May 2011

Janice Golda, Intel, co-led a session at The ConFab 2011 on continued device scaling. EUV infrastructure will be a major topic, as well as transistor challenges. While lithography difficulties exist at tighter device densities, Golda reminds us that metrology obstacles must also be tackled.


Flat 2011 wafer fab equipment capex, but look to 193i stepper to step out

Wed, 1 Jan 2011

Semiconductor capital equipment, 4Q10: strength through 2013, then retrenchment. Source: Gartner.Wafer fab capex in 2011 is expected to stick around 2010 levels. But don't despair of growth, says Dean Freeman of Gartner. For one thing, cutting-edge wafer fab equipment will be hot. On top of that, 2011 will be a brief respite, with a strong 2012/2013 waiting in the wings.


Toppan, IBM focus 14nm photomask JV on ArF immersion lithography

Mon, 1 Jan 2011

Toppan Printing Co. Ltd. extended a joint development agreement with IBM for leading-edge photomask process, covering the 14nm technology node for logic devices. Toppan and IBM will focus their joint development efforts on ArF immersion lithography for the 14nm node.


Enabling lithography for the 22nm node

Tue, 1 Jan 2011

Single-exposure patterning schemes are unable to meet 22nm specifications, which leads fabs to use double-patterning like LELE. However, below 22nm, a simple multiplication of double-patterning is exceedingly difficult. Alternative processes like tone reversal, EUV, and resist freezing are under development, says Nick Pugliano, Dow Electronic Materials. This is an online exclusive essay in SST's Forecast for 2011: Back to Reality series.


22nm brings maskmakers, end users closer

Tue, 1 Jan 2011

The conditions and challenges at the 22nm technology node are becoming clear: double patterning, source-mask optimization are becomign pervasive, EUV is on the doorstep, and they will all have significant impact on mask manufacturers, writes Franklin Kalk from Toppan Photomasks.


Below 22nm, spacers get unconventional

Thu, 1 Jan 2011

IEDM Spacer discussionSpacers are considered "conventional materials," and thus an odd topic for the cutting-edge IEDM. ASM CTO Ivo Raaijmakers points out that semiconductor fab below 22nm will require different processes for spacers: atomic layer deposition (ALD) and plasma-enhanced ALD (PEALD).


Silicon nanophotonics could answer data needs if manufacturing requirements are met

Fri, 1 Jan 2011

The amount of data that will need to be moved in the not-too-distant future motivates research into a better way to connect devices, said Intel Fellow and director of the Photonics Lab at Intel Labs, Mario Paniccia, at SEMI’s Industry Strategy Symposium (ISS). Paniccia discusses the manufacturing requirements for silicon photonics, including optical testers.


SPIE keynote Imec installs ASML pre-production EUV scanner

Mon, 2 Feb 2011

At the SPIE Advanced Lithography conference, Luc Van den hove, president and CEO of imec, announced during his keynote speech that imec has started the installation of ASML's pre-production extreme ultraviolet lithography (EUVL) scanner, the NXE:3100, in its Leuven, Belgium facility.


DNA origami fuses lithography with self-assembly

Thu, 2 Feb 2011

Arizona State University's Hongbin Yu and Hao Yan are exploring how to use top-down lithography combined with modified bottom-up self-assembling nanostructures to guide the placement of nanostructures on silicon wafers.


Real-time-gas-flow-monitoring-improves-mass-flow-controller-performance-in-wafer-fab

Tue, 2 Feb 2011

Real-time gas flow monitoring improves mass flow controller performance understanding in wafer fabSanjay Yedur et al, from Pivotal Systems and J.H. Lee et al from Samsung’s R&D Equipment Engineering Team discuss the use of a real-time gas flow monitoring system that allows for in-situ flow measurements, based on a highly accurate rate of pressure drop over a known volume and temperature. Using this system, insights are gained on the run-to-run repeatability of mass flow controller (MFC) transient and steady-state flow during wafer processing.


Eulitha, DNP pattern photonic crystals on 4-in wafers

Tue, 2 Feb 2011

Eulitha AG and Dai Nippon Printing (DNP) say they have successfully patterned 4-in Si wafers with Eulitha's "PHABLE" technology, creating uniform photonic crystal patterns with 600nm period and hexagonal symmetry.


Model-based-mask-data-prep-Solving-the-impossible-mask

Thu, 3 Mar 2011

SPIE Advanced Lithography eBeam Initiative annual meeting, circle shot imageAki Fujimura, chairman & CEO of D2S, provides an update of the eBeam Initiative roadmap. Speaking at SPIE Advanced Lithography with editor Debra Vogler, Fujimura recalls mask cost/yield and write time developments, summarizes the eBeam Initiative's meeting, and describes member Dai-Nippon Printing's impressive time results with an "impossible" mask.


Mattson-Technology-debuts-photoresist-dry-strip-system

Mon, 3 Mar 2011

Mattson Technology Inc. (NASDAQ: MTSN) introduced the SUPREMA XP5 photoresist dry strip system for high-volume production of current and future-generation logic, DRAM and flash memory devices.


Complementary-electron-beam-lithography-extends-optical-litho-life

Wed, 3 Mar 2011

At SPIE Advanced Lithography, David Lam, Multibeam chairman and former CEO of Lam Research, presented the complementary e-beam lithography (CEBL) concept. IC manufacturers will find CEBL beneficial as they search for ways to continue using their optical lithography equipment, says Lam.


Analyst's take: Why the gate first-last debate isn't over

Mon, 1 Jan 2011

Common Platform Technology execs have declared that they will switch from a gate-first approach to a gate-last approach starting with the 20nm process technology node, essentially reversing their position for the past few years. Analysts told SST why the CPA had a change of heart, why it's not unexpected, and why other concerns will very soon overshadow this switchover -- and likely resurrect the debate.


450mm-TSV-EUV-transitions-SEMATECH-Armbrust

Wed, 1 Jan 2011

SEMATECH January 2011Dan Armbrust, SEMATECH, spoke about the role of collaboration in his SEMI Industry Strategy Symposium presentation. Significant technology transitions facing the semiconductor industry include lithography (introduction of EUV), interconnects (TSVs and 3D packaging), and productivity (450mm wafer manufacturing). Additionally, disruptive technology in logic and memory devices will challenge the industry.


ITRS 2010: What happened during this off-year?

Wed, 1 Jan 2011

The 2010 Update to the International Technology Roadmap for Semiconductors (ITRS), while not one of the scheduled major revisions, nevertheless includes substantial changes have occurred in 2010, including boosts in the timelines for NAND flash and DRAM device rollouts, backup plans for lithography forced by EUV delay, impending device and interconnect structural changes, and progress in 3D packaging.


22nm Challenges Abound for 2011

Sat, 1 Jan 2011
Pete Singer Editor-in-Chief

Brewer-Science-immersion-lithography-products

Mon, 2 Feb 2011

Brewer Science launched the OptiStack system of advanced lithography products: a combination of materials, software and process support. In tandem, Brewer Science debuted the ARC 300 coating series, designed to work with OptiStack.


SoftJin-enhances-defect-analysis-software

Fri, 2 Feb 2011

SoftJin NxDAT defect analysis softwareSoftJin Technologies, a provider of customized automation software for electronic design and manufacturing, enhanced NxDAT, its defect analysis software. The enhanced version of NxDAT is optimized for better speed and memory performance.


Wafer cleaning: the next frontier in semiconductor fabrication

Tue, 2 Feb 2011
Ralph Spicer, Qcept Technologies, Atlanta, GA USA

The future of lithography

Tue, 2 Feb 2011
Semiconductor manufacturers are now relying on immersion lithography for the 32 nm node, sometimes with double- and triple-patterning approached. Work progresses on EUV as the heir apparent, but e-beam lithography could emerge as a viable alternative. We invited experts from SEMATECH, imec, Cymer , D2S and Molecular Imprints to give their perspective on next generation lithography challenges and solutions.

Predictive, short-interval scheduling improves litho utilization and cycle time

Tue, 2 Feb 2011
An advanced scheduling approach is providing semiconductor manufacturers with improved results in critical photolithography areas. Steve Marteney, Applied Materials Inc., Salt Lake City, UT USA

Technology and cost considerations for high-volume HBLED lithography

Tue, 2 Feb 2011
Lithography is one of the critical processes affecting overall LED device yield and performance, but the use of 1X steppers provides significantly better technology and economic advantages for high-volume manufacturing environments. Manish Ranjan, Doug Anberg, Warren Flack, Ultratech Inc., San Jose. CA USA

Five takeaways from TSMC's 450mm pledge

Fri, 2 Feb 2011

TSMC's Morris Chang has laid out a surprisingly bullish timeline for the foundry's 450mm wafer-size transition. Analysts weigh in on whether TSMC's goals are achievable, and what it means for the rest of the industry.


Mask defect-inspection-tool-software-from-Reticle Labs

Tue, 3 Mar 2011

Reticle Labs RS-MiniReticle Labs released RS-Mini, an enterprise-class highly compact mask inspection defect management framework for mask and wafer fabrication plant infrastructure. It allows fabs to share inspection results, track defect trends, summarize inspection results from multiple systems, and more.


Synopsys_eliminates-intermediate-I-O-steps-with-EUV-design-verification

Wed, 3 Mar 2011

Synopsis Proteus LRCSynopsys introduced the Proteus LRC for lithography verification at the SPIE Advanced Lithography Conference. It is targeted for 28nm and below and includes EUV as well as double-patterning (DPT) capabilities. George Bailey, director, technical marketing at Synopsys, describes the data flow process.


Synopsys-lithography-verification-in-Proteus-LRC-handles-EUV-double-patterning

Tue, 3 Mar 2011

Synopsys introduced Proteus LRC for lithography verification at SPIE Advanced Lithography. Proteus LRC provides process-window-aware checking features to identify locations in a design that are sensitive to process variations, enabling corrective actions prior to committing a semiconductor design to manufacture.


Leveraging ion implant process characteristics to facilitate 22nm devices

Tue, 3 Mar 2011
Using implant as a precision material modification in contrast to its traditional role as a semiconductor dopant tool, provides enabling technology and new applications. James L. Kawski, Varian Semiconductor Equipment Associates, Gloucester, MA USA

SPIE keynote: imec stance on materials innovation

Wed, 3 Mar 2011

Luc Van den hove, president/CEO of imec, summarizes key themes from his keynote presentation at the SPIE Advanced Lithography symposium. Van den hove speaks about materials challenges, silicon photonics, and semiconductors in healthcare/medicine in an interview with Debra Vogler at the show.


16nm-hp-EUV-blanks-inspected-with-KLAC-Teron

Fri, 3 Mar 2011

Lithography defect inspection. SOURCE: KLA-Tencor (KLAC)Among the topics covered at KLA-Tencor’s annual Lithography Users Forum was extension of KLAC's Teron 600 platform for inspection of EUV blanks at the 16nm hp node. Here, Brian Trafas speaks with Debra Vogler about process control in advanced lithography.


SPIE 2011: An ASML review of EUV

Tue, 3 Mar 2011

Ron Kool from ASML reports on updates in EUV and other next-generation lithography technologies at this year's SPIE Advanced Lithography symposium.


AMAT-inspection-Magma-yield-analysis-integration-accelerates-litho-quals-better-chip-yields

Tue, 3 Mar 2011

Excalibur Litho from Applied Materials (AMAT) and Magma Design AutomationApplied Materials integrated Magma's CAD-based navigation and yield analysis software with AMAT inspection systems; it's called Excalibur Litho and targets designs at 2xnm and below. Ankush Oberai, Magma and Erez Paran, AMAT, explain why hot spot identification and real line data for libraries will fuel better lithography processes.


SPIE: A glimpse into Intel's litho future

Mon, 3 Mar 2011

Dr. David Lam from Multibeam reports on the Nikon LithoVision conference at this year's SPIE Advanced Lithography symposium, where Nikon and Intel tipped results and strategies for 1D gridded layouts, and hinted at mysterious "game-changer" litho efforts besides 193i and EUV.


Toppan Photomasks grows Shanghai site, adds more advanced capabilities

Thu, 11 Nov 2011

Toppan Photomasks will expand its Shanghai manufacturing operation serving China's semiconductor industry. Costing about $20 million, the expansion will increase photomask production significantly, and enable more advanced photomasks made with feature sizes as small as 90nm.


450mm lithography system order bagged by Molecular Imprints

Wed, 11 Nov 2011

Molecular Imprints Inc. will build a 450mm-capable lithography system for an undisclosed leading IC manufacturer.


Novellus replaces TiN hard masks with ceramic for sub-22nm nodes

Wed, 11 Nov 2011

Novellus Systems (NASDAQ:NVLS) debuted ceramic hard mask (CHM) materials for use in sub-22nm patterning applications. The CHM materials reportedly improve performance over TiN hard masks, and with easier integration onto the fab floor.


Maskless lithography progress from the IMAGINE Workshop

Thu, 9 Sep 2011

Yann Gallais, Leti, shares updates from Leti, TSMC, and Mapper on maskless lithography tools, processes, and cost. Gallais reports from the IMAGINE workshop held September 6 in Tokyo.


e-beam lithography precision at optical lithography speed: Complementary lithography breaks the NGL logjam

Tue, 9 Sep 2011

David K. Lam, Multibeam, summarizes the gap between today

ASML's Brion launches model-based SRAF

Tue, 9 Sep 2011

Brion Technologies, a division of ASML, uncrated Tachyon MB-SRAF (Model-Based Sub-Resolution Assist Features) for its Tachyon computational lithography platform.


Applied Materials EUVL mask etch system debuts with multiple installs

Mon, 9 Sep 2011

Applied Materials (AMAT) unveiled its Centura Tetra EUV advanced reticle etch system at the SPIE BACUS conference. Amitabh Sabharwal, GM, mask etch products, talks about the product's technical specs, and how it overcame EUV challenges.


SIS lithography eliminates hard mask for deep patterns at Argonne Labs

Fri, 8 Aug 2011

Argonne Lab researchers have created an e-beam lithography process that boosts resist layers to eliminate the hard mask application. It results in more precise features and deeper etch for semiconductor, solar energy, and other products.


Model-based mask data prep using overlapping shots for 20nm devices

Tue, 8 Aug 2011

OPC technologies use aggressive assist features with sub-80nm features on the mask to offer improved process window, and therefore yield. MB-MDP, coupled with new-generation mask-writing equipment, produces overlapping e-beam shots that result in lower shot count.


Cymer wafer-level light source metrology targets advanced lithography control

Thu, 10 Oct 2011

Light source supplier Cymer Inc. (Nasdaq:CYMI) launched SmartPulse, which monitors light source parameters at the wafer, collecting data for a suite of reporting and analysis tools.


SPIE BACUS 2011: Having your cake and eating it too

Wed, 10 Oct 2011

Jan Willis from the eBeam Initiative summarizes the group's annual event at SPIE BACUS 2011, with presentations on both improving wafer quality and mask write times at the 20nm node. Other presentations dealt with EUV masks and a lack of funding support.


SEMATECH's Bryan Rice: Why it's time for a "refresh"

Tue, 10 Oct 2011

Bryan Rice, SEMATECH's newly appointed director of strategic initiatives, tells SST what his new job entails: what he sees as his biggest challenges, which areas will keep SEMATECH's main attention (hint: the "once and future king" of resources), and what new areas are being explored.


Making EUV work, with a subsystem ear: Interview with SEMATECH's Stefan Wurm

Fri, 9 Sep 2011

Dr. Stefan Wurm, newly appointed director of SEMATECH's lithography program, tells SST what areas continue to be top-priority to SEMATECH, where progress is being made, and how SEMATECH's pursuits are changing along with its membership base.


Argon increases silicon etch rate 4x

Fri, 9 Sep 2011

Engineers at the NIST Center for Nanoscale Science and Technology (CNST) NanoFab have developed a plasma etch/argon process that improves etch rate, mask selectivity, and the sidewall profile of silicon structures.


EUV lithography flare distortion correction

Wed, 8 Aug 2011

Extreme ultraviolet (EUV) lithography introduces new patterning distortions -- flare along with proximity effects -- that must be accurately modeled and corrected on the reticle. James Word and Christian Zuniga of Mentor Graphics discuss an all model-based approach to flare compensation.


GLOBALFOUNDRIES: Ready for 20nm semiconductor designs

Tue, 8 Aug 2011

GLOBALFOUNDRIES successfully taped out a 20nm test chip using flows from Cadence Design Systems, Magma Design Automation, Mentor Graphics Corporation, and Synopsys Inc. GLOBALFOUNDRIES customers can now begin evaluating their 20nm semiconductor designs.


Mix of end users and challenges drives Qcept Technologies' partnering strategy

Thu, 8 Aug 2011

Robert Newcomb from Qcept explains the two types of customers for inspection technology and their different needs: those on the leading edge who want yield improvements, and mainstream fabs seeking a better yield/cost mix on older processes.


Ultratech's market/technology strategies support revenue growth

Thu, 8 Aug 2011

Scott Zafiropoulo explains Ultratech's business and positioning strategies in an interview at SEMICON West, including how the company weathers market cyclicality and prepares for a 450mm wafer-size transition.


Projection litho tool lowers CoO for HB-LED manufacturing

Tue, 8 Aug 2011

Doug Anberg, VP of advanced stepper technology at Ultratech, discusses the physics behind improvements in the company's new Sapphire 100E HB-LED tool in a video interview at SEMICON West 2011.


Leti lithography update at SEMICON West

Mon, 8 Aug 2011

Leti's Serge Tedesco, lithography program manager, provides an update on the research group's 193 optical lithography program for 22nm and below, and exploration of multi e-beam lithography techniques.


SEMATECH names lithography director

Wed, 9 Sep 2011

SEMATECH appointed Dr. Stefan Wurm as the consortium's director of lithography, responsible for the strategic direction of SEMATECH's Lithography program, particularly worldwide EUV infrastructure development.


SPIE BACUS: Delayed Photomask Japan 2011 in a nutshell

Wed, 9 Sep 2011

Reporting from this week's SPIE BACUS Photomask Technology conference, Franklin Kalk from Toppan Photomasks picks through the "10 best" papers that were to have been presented at Photomask Japan earlier this year.


Litho tool explores tradeoffs at 20nm and below

Tue, 9 Sep 2011

D2S announced a mask-wafer double simulation accelerated workstation, TrueMask DS, for R&D exploration, bit-cell design, hot-spot analysis and mask defect categorization. Aki Fujimura, CEO, D2S, speaks with ElectroIQ's Debra Vogler about the technology, and what makes 20nm different.


Materion buys EIS Optics Limited, adds Shanghai factory

Thu, 10 Oct 2011

Materion Advanced Materials Technologies acquired EIS Optics Limited, adding a 97,000sq.ft. manufacturing site in Shanghai, China for optical coatings. EIS Optics makes optical thin film filters, glass processing, lithography and optical subassemblies.


JSR joins lithography research at CEA-Leti

Wed, 10 Oct 2011

JSR Micro and CEA-Leti will partner to develop sub-20nm next-generation lithography materials and processes, focusing on pitch division in 193nm optical lithography for <20nm logic applications and on direct-write maskless lithography (ML2) technology.


Inside ASML's numbers: EUV update, 2012 predictions, and 450mm disconnect

Thu, 10 Oct 2011

A deep dig inside ASML's 3Q11 results and execs' commentaries unearths insights into 4Q11 and 2012 projections, an updated EUV timeline, and some curious disconnect about the industry's 450mm readiness.


Imec, ASML extend litho work, debut EUV sensors

Mon, 10 Oct 2011

Imec and tool vendor ASML have signed a new 5-year deal to continue collaboration on lithography technologies, both immersion and EUV, as well as associated components -- including new sensors to help calibrate lens alignment and dose.


Freescale Semiconductor CEO takes SIA lead

Thu, 11 Nov 2011

The Semiconductor Industry Association (SIA) elected Freescale Semiconductor CEO Rich Beyer as its 2012 chairman. This will be the SIA's 35th year.


Ushio achieves 30W EUV lithography output

Mon, 10 Oct 2011

USHIO INC.'s wholly owned subsidiary, XTREME technologies GmbH, achieved 30W output at an intermediate focus under a duty cycle of 100% for high-volume extreme ultraviolet (EUV) lithography.


EUV Symposium report card: EUV's past, present, and future

Fri, 10 Oct 2011

Two Wall Street analysts report their impressions from last week's EUV Symposium (Oct. 17-19 in Miami), where companies in the EUV supply chain reported their latest results and planned progress through 2012. And don't look now but there's a competition brewing in source power.


EUV Symposium: Updates on defects, resists, AIMS, and non-EUV NGL

Fri, 10 Oct 2011

Stefan Wurm, director of SEMATECH's lithography program, relayed highlights from last week's EUV Symposium (Oct. 17-19 in Miami), including results in defects (mask blanks and substrates) and an update on SEMATECH's EUV Mask Infrastructure (EMI) program.


SEMATECH Litho Forum: Steady progress on all fronts, surprise showing by e-beam

Thu, 6 Jun 2008
by Debra Vogler, Senior Technical Editor, Solid State Technology
June 5, 2008 - With almost all major R&D lithography efforts reporting at SEMATECH's Litho Forum (May 12-14, Bolton Landing, NY), the common theme resonating throughout a debrief with forum co-chair Mike Lercel and program chair Bernie Roman was one of great progress made on many fronts, with a growing interest in maskless/e-beam lithography.

SEMI: Suppliers see no net benefit in 450mm

Thu, 5 May 2008
by Pete Singer, Editor-in-Chief, Solid State Technology
May 22, 2008 - For a 450mm wafer-size transition to happen, suppliers need to be convinced that their initial investments will translate into sales and won't eat into their 300mm business. But speaking at the Confab, SEMI standards VP John Ellis indicated that suppliers still think there's no benefit to them -- and he presented new data showing that the cost modeling is flawed, and that investments are better used elsewhere.

Litho will get much tougher with double patterning, extensive computation

Wed, 5 May 2008
by Bob Haavind, Editorial Director, Solid State Technology
May 21, 2008 - There's a tough road ahead for lithography, with double patterning and complex computation as well as requirements for more litho-friendly design, explained ASML's Martin van den Brink, EVP of marketing & technology, speaking at the Next Generation Lithography session at The ConFab.

450mm by 2012: Between the lines of PR lingo

Tue, 5 May 2008
by James Montgomery, News Editor, Solid State Technology
May 13, 2008 - Some big chipmakers are eager to transition to 450mm wafers because of cost savings, but resistant semiconductor equipment/materials suppliers are still smarting from their 300mm investment burden and lower-than-hoped returns. After a lot of saber-rattling on both sides, a toned-down PR from Intel/Samsung/TSMC might be the first step for both sides to finally move forward with 450mm development.

Analysts: Good, bad news with IMFT's 34nm flash debut

Thu, 5 May 2008
May 29, 2008 - Intel and Micron's announcement that they have developed a 34nm NAND flash device could give the companies a better cost/profit profile vs. competitors, and/or help stretch an already painful oversupply situation well into the next year, according to a report from Objective Analysis. Meanwhile, Gartner notes that the two need to make some related capacity decisions soon if they want to leverage their short-lived technology lead on the competition.

ASMI: New ALD tool offers single-metal gate stack for 32nm HK+MG

Mon, 5 May 2008
May 19, 2008 - ASM International's US subsidiary, ASM America, says it has a new atomic layer deposition (ALD) process targeting 32nm-node chip manufacturing with lanthanum oxide (LaOx) and aluminum oxide (AlOx) high-k cap layers that enable high-k metal gate stacks using a single metal, instead of two different metals required previously for CMOS.

Analysts: DRAM, NAND outlook stable; look for B2S build as next beacon

Thu, 5 May 2008
May 29, 2008 - Fundamentals in the memory industry are stable and "incrementally improving," with DRAM prices rising again and NAND flash demand seen improving in general, according to analyst firm FBR Research. The next big market indicator is rapidly approaching, in the late-June timeframe with an update of devicemakers' back-to-school build rate schedules.

CNT-asbestos links point to need for more research, say experts

Thu, 5 May 2008
by James Montgomery, News Editor, Solid State Technology
May 22, 2008 - A new report published in the journal Nature Nanotechnologies is raising alarms about apparent health risks associated with carbon nanotubes (CNT), similar to those seen with asbestos. But efforts are already underway to look more closely at potential issues, according to Walt Trybula, former SEMATECH immersion lithography guru and now at Texas State U., in an email exchange with WaferNEWS.

ALD comes to single-metal high-k gate stacks

Fri, 5 May 2008
by Katherine Derbyshire, contributing editor, Solid State Technology
May 23, 2008 - Controlling the interface between the metal gate and the hafnium-based dielectric has been one of the most difficult issues for high-k integration schemes. ASM now says it has ALD processes for both LaOx and AlOx, and that its Polygon platform and Pulsar process modules offer a reliable platform for sequential deposition of dielectric and cap layers in a gate-first process.

3D for microprocessors now...TSV later

Wed, 5 May 2008
by Ed Korczynski, senior technical editor, Solid State Technology
May 21, 2008 - While manufacturing of 3D ICs is today limited mostly to memory chip stacks and cell-phone camera modules, the next huge application seems to be the embedded memory in microprocessors. Subramanian Iyer, distinguished engineer and chief technologist of IBM's systems and technology group, explained the economic considerations behind 3D microprocessors at the ConFab in Las Vegas.

AMAT + ASMI: What's in it for both sides?

Mon, 6 Jun 2008
by James Montgomery, News Editor, Solid State Technology
June 8, 2008 - Applied Materials has made a verbal unsolicited $400M-$500M offer to buy ASMI's atomic layer deposition (ALD) and plasma-enhanced chemical vapor deposition (PECVD) businesses. Gartner research VP Dean Freeman helps WaferNEWS brainstorm the most likely reasons behind AMAT's offer (and some unlikely-yet-interesting-but-good-luck-proving-it possibilities), and what it means for ASMI.

KLA Tencor announces Archer 200 overlay metrology system

Thu, 6 Jun 2008
by M. David Levenson, Editor-in-Chief, Microlithography World
June 5, 2008 - Overlay specifications have narrowed dramatically as the semiconductor industry advances toward the 32nm node, requiring control of high-order grid and field distortions, as noted by the ITRS. Seeking to meet these new requirements is KLA-Tencor's new Archer 200, the latest version of the company's imaging overlay measurement tool.

Toppan-IBM 22nm pact: More than meets the eye?

Wed, 6 Jun 2008
June 25, 2008 - Toppan Printing and IBM have forged a new development agreement extending their photomask process development work to the 22nm node, continuing a longstanding partnership -- but an industry insider tells WaferNEWS that there's a strategic agenda at work that could shake up the market.

Dow Corning targets maskless lithography with latest e-beam photoresists

Tue, 6 Jun 2008
by Debra Vogler, Senior Technology Editor, Solid State Technology
June 24, 2008 - Dow Corning Electronics aims to support development efforts toward high-volume manufacturing using e-beam lithography technology with its new XR-1541 spin-on resists, which it says are capable of defining features as small as 6nm.

Terafab addresses mask requalification, but more's needed

Fri, 2 Feb 2008
by M. David Levenson, Editor-In-Chief, Microlithography World
Feb. 15, 2008 - An odd thing happened on the way to 65nm chip technology -- perfectly good photomasks started going bad after a few hundred wafer exposures, due to the deposition of crystal-like defects. If detected, they can be cleaned off and the $100k mask re-used. KLA-Tencor says its new suite of tools can requalify masks in the fab, avoiding yield crashes (though occasionally delaying production).

SPIE: SEMATECH starting imprint litho work, buys MII tool

Wed, 2 Feb 2008
Feb. 27, 2008 - SEMATECH has purchased Molecular Imprints new Imprio 300 tool to demonstrate the feasibility of nanoimprint lithography for 32nm and below semiconductor production. Initial work will focus on demonstrating and enhancing overlay performance, and identify development areas to accelerate the introduction of the technology into manufacturing. Delivery is scheduled for mid-2008.

SPIE: Philips, XTREME push EUV source to 500W

Wed, 2 Feb 2008
Feb. 27, 2008 - Presenting at the SPIE Advanced Lithography Symposium, Philips Extreme UV and XTREME Technologies offered proof-of-principle experiment results showing their gas-discharge plasma source can be scaled to 100kHz operation frequency, which translates to a record 500W EUV source power -- more than enough to meet requirements for high-volume semiconductor manufacturing.

SPIE: AMD, IBM tip first "full field" EUV chip

Wed, 2 Feb 2008
by Bob Haavind, Editorial Director, and James Montgomery, News Editor, Solid State Technology
Feb. 27, 2008 - AMD and IBM say they have produced a working 22mm x 33mm test chip built with 45nm process technologies using EUV lithography for the first critical layer of metal interconnects, pushing beyond previous EUV efforts that involved "narrow field" portions of the design.

SPIE NEWS: SEMATECH, Carl Zeiss finalize design for DP photomask metrology system

Tue, 2 Feb 2008
Feb. 26, 2008 - Carl Zeiss and SEMATECH say they have completed final design for a next-generation photomask registration and overlay metrology system, dubbed "Prove," that will enable production of advanced photomasks "with substantially improved image placement accuracy," eyeing in particular the tighter placement control required for double-patterning technology.

SPIE NEWS: HamaTech, SEMATECH tout EUV mask blank cleaning work

Tue, 2 Feb 2008
Feb. 26, 2008 - HamaTech says its advanced modular processing platform, MaskTrack, has achieved "all critical SEMATECH roadmap milestones" for cleaning EUV mask blanks, with demonstrated successful removal of all particles at 30nm and greater, as well as "a number of" 10nm defects, seen as necessary for 22nm semiconductor manufacturing processes.

Updated: Nikon's double-patterning tool due by 4Q08

Wed, 2 Feb 2008
Feb. 20, 2008 - Nikon Corp. says it will have an "enhanced" version of its NSR-S610C ArF immersion scanner, optimized for double-patterning lithography process, ready for customers by 4Q08, billing the upgrade as a "low-risk solution" for developing double-patterning technology for use at the 32nm node.

KLA-Tencor uncrates new mask inspection tools

Fri, 2 Feb 2008
Feb. 15, 2008 - KLA-Tencor has unveiled three new inspection tools for requalifying masks in a wafer fab and inspect for contaminants, capabilities it says will improve yield and lower production risk in 65nm and 45nm chip manufacturing and 32nm development.

SEMATECH hits EUV blank defect target

Tue, 2 Feb 2008
Feb. 11, 2008 - SEMATECH says it has demonstrated defect density of 0.04/cm2 for EUV mask blanks, with a total of 8 defects combined from substrate and multilayer, surpassing the consortium's published commercial EUV mask blank roadmap target for the end of 2007.

ISSCC: TI discloses 45nm details

Tue, 2 Feb 2008
Feb. 5, 2008 - At this week's International Solid-State Circuits Conference (ISSCC), Texas Instruments is disclosing process and design information about its 45nm process-based 3.5G baseband and multimedia processor, which offers 55% better performance and uses 63% less power than the 65nm version.

SanDisk: We'll ship 43nm NAND in 2Q08

Thu, 2 Feb 2008
Feb. 7, 2008 - SanDisk says it will start shipping 16Gb multilevel NAND flash memory products built with 43nm process technologies during 2Q08, with 32Gb versions slated for later in the year. Manufacturing of the newer process node is underway at Toshiba's Yokkaichi operations near Nagoya, Japan, produced initially at Fab 4, followed by Fab 3 sometime in 2H08.

Lithography workshop report: 193nm/DEDE for 32nm, still weighing 22nm options

Mon, 1 Jan 2008
Immersion lithography was the central theme at the 2007 [formerly IEEE] Lithography Workshop (Dec. 9-13, Puerto Rico), since 193nm immersion and double exposure/double etch appears the likely choice at 32nm. Also discussed were EUV's trio of major unsolved problems, multibeam's revival, and possible litho inspiration in magnetic discs and flat-panel displays.

Ponte Solutions sees advantage in taking DFM to the IP level

Wed, 1 Jan 2008
As illustrated by recent news, Ponte Solutions is strategically targeting DFM at the IP level by placing tools in the hands of designers where they are most comfortable: within the "cockpits" of their favorite EDA tools. (The message being sent to fabless companies: you must own the DFM challenge.) Execs also tell WaferNEWS about their new physics-based etch modeling for vias/contacts and poly/metal at 45nm and beyond.

Toshiba, SanDisk ramping 43nm NAND flash with HK+MG, 3b/cell

Fri, 1 Jan 2008
Toshiba and SanDisk aim to increase their share of the NAND flash market by bringing down costs, as they accelerate the ramp of their new Yokkaichi Fab 4 next year, introducing 43nm geometries, high-k/metal gates, second generation 1.3NA immersion lithography, and 3 bits per cell. Executives from both companies detailed their current production plans and future roadmap for flash memory technology to SST partner Nikkei Microdevices.

SST On the Scene: Lars Liebmann on DFM, scaling

Fri, 2 Feb 2008
Feb, 29, 2008 - In this exclusive video interview, IBM's Lars Liebmann talks about his papers presented at this week's SPIE, including persistent misconceptions about restricted design rules, and the need for designers to react to systematic and stable effects with broad, coarse layout adjustments vs. minor movements based on a specific moment. He also discusses the opportunities at 22nm with "soft" and "hard" DFM, and how these concepts will be required to keep the scaling path profitable.

Double patterning will challenge litho, metrology, push feedback, computation

Tue, 2 Feb 2008
by Bob Haavind, Editorial Director, Solid State Technology
Feb. 26, 2008 - Plenary talks at this week's SPIE Advanced Lithography Conference reviewed the road ahead for lithography, from how far 193nm immersion can be pushed (probably 32nm, helped double patterning, new lens materials/fluids, and 3D) to the projected readiness of an EUV infrastructure (maybe by 2010-2012), and the progress and stalls in ongoing work to achieve success in both areas.

SPIE: Tela Innovations lays it all out straight

Thu, 2 Feb 2008
by M. David Levenson, Editor-in-Chief, Microlithography World
At about the 90nm node, circuit features so much smaller than the exposure wavelength led to increased circuit variability, lithography hotspots, and limited yields (and applying restrictive design rules had limited success). Now, startup Tela Innovations is proposing a radical step to solve the industry's layout problems: employing pre-defined linear topologies, workable with 32nm and double-patterning and down to 22nm.

Gauda harnesses graphical processor units for OPC

Tue, 2 Feb 2008
by M. David Levenson, Editor-in-Chief, Microlithography World
Feb. 26, 2008 - Have you ever wished that computational lithography could be more like a videogame? Gauda, a Sunnyvale, CA, startup decloaking at this week's SPIE's Advanced Lithography Symposium is offering to make it so, at least for optical proximity correction and verification (OPC and OPV).

Molecular Imprints announces 4WPH step-and-flash imprint tool

Mon, 2 Feb 2008
by M. David Levenson, Editor-in-Chief, Microlithography World
Feb. 25, 2008 - Molecular Imprints CEO Mark Melliar-Smith tells WaferNEWS why its Imprio 300 imprint lithography tool is the "only game in town" for semiconductor prototyping and process development in the <30nm realm, capable of printing 32nm, 28nm and 22nm features at 4WPH with 35nm overlay.

Dow Corning taking collaborative route to photoresist goals

Mon, 2 Feb 2008
by James Montgomery, News Editor, Solid State Technology
Feb. 25, 2008 - Dow Corning exec Jeff Bremmer talks with WaferNEWS about how his company has turned to a new business model, development partnerships with litho materials suppliers, for its push into the world of photoresist resins.

Brion powers up to meet DPT challenges at 32nm-22nm

Mon, 2 Feb 2008
by Debra Vogler, Senior Technical Editor, Solid State Technology
Feb. 25, 2008 - At the opening of this week's SPIE Advanced Lithography Symposium, Brion Technologies unveiled a more powerful version of its Tachyon Computational Lithography platform, and the release of Tachyon DPT, software that allows chipmakers to meet the low k1 requirements for memory and logic devices at 32nm and below.

DNS, Sumco, IBM among Chartered supplier honorees

Thu, 3 Mar 2008
Mar. 13, 2008 - Ten outperforming suppliers have been honored with awards by Singapore chipmaker Chartered Semiconductor, for their efforts providing equipment, materials, and service. Dainippon Screen Singapore Pte. Ltd., Sumco Techxiv, and IBM Singapore Pte Ltd were named top suppliers for 2007 in their respective categories.

Cost, performance challenge both established and advanced lithography

Wed, 3 Mar 2008
by Katherine Derbyshire, Contributing Editor, Solid State Technology
Conferences like the recent SPIE focus on the leading edge (e.g., EUV, double patterning, immersion lithography), yet process technologies remain commercially important long after the leading edge has moved on. Case in point: KrF-based litho, currently used in >30% of 65nm DRAMs and poised to increase substantially. Here's what resist suppliers like Fujifilm Electronic Materials are doing to support this trend.

JSR touts "freezing material" for double patterning

Thu, 3 Mar 2008
Mar. 13, 2008 - JSR says it has achieved 32nm line and space patterns for 22nm node semiconductor devices with a new "freezing material" used in double patterning. Results were presented at last month's SPIE Advanced Lithography conference.

SPIE report: Getting ready for double patterning...

Wed, 3 Mar 2008
by M. David Levenson, Editor-in-Chief, Microlithography World
Since high-volume EUV lithography is delayed, the first 32nm generation chips will have to be printed with double patterning technology (DPT) for critical layers and much of the conference focused on the various options, none of which seemed fully developed. (First in a four-part series)

SPIE report: ...and EUVL, eventually

Wed, 3 Mar 2008
by M. David Levenson, Editor-in-Chief, Microlithography World
Progress continued in EUV lithography, but at a rate well below that needed for insertion at 32nm. AMD described the patterning of an entire metal-1 layer for a full exposure field chip and the integration of EUVL into the process flow. Sources remain an issue, though some think solid state lasers could help improve efficiency. Others are thinking ahead to 22nm. (Second in a four-part series)

SPIE report: Nonstarters, and dark options

Wed, 3 Mar 2008
by M. David Levenson, Editor-in-Chief, Microlithography World
Intel chose this SPIE conference to present five papers on pixelated masks, an apparently abandoned program on pixelated masks that had pre-occupied litho engineers for several years. Elsewhere, prospects for high-index immersion technology seem to be dimming, and progress remains sluggish on a promising medium-throughput e-beam direct write for imprint litho. (Third in a four-part series)

SPIE report: Cleverness, and a computational arms race

Wed, 3 Mar 2008
by M. David Levenson, Editor-in-Chief, Microlithography World
Avoiding unprintable structures will be essential for manufacturing 45nm and smaller circuits, and that was reflected in a series of papers on design for manufacturing and design rule restrictions, some of them quite aggressive. (Fourth in a four-part series)

U. Albany's Denbeaux: EUV works, though far from what's needed

Tue, 3 Mar 2008
by Bob Haavind, Editorial Director, Solid State Technology
An insightful update on three key semiconductor technologies -- SOI, TSV/3D, and SOI -- sparked a lively Q&A following a SEMI-sponsored breakfast near Boston (Mar. 5). Here, Gregory Denbeaux, assistant professor of nanotechnology at the U. of Albany, gave an overview of progress needed in EUV to make it suitable for high volume manufacturing.

SPIE: And now there are three, again

Thu, 3 Mar 2008
by M. David Levenson, Editor-in-Chief, Microlithography World
Friday (Feb. 29) sessions at the SPIE Advanced Lithography conference featured detailed presentations by Canon, Nikon, and ASML, all talking about improvements in lens aberration control, defectivity, and throughput. Their water immersion optical lithography equipment seems fully capable of producing 45nm devices, and should be OK with some double patterning at 32nm -- but none of it as shown will jump to the 22nm node.

SST On the Scene: IMEC's Kurt Ronse on EUV, double patterning

Tue, 3 Mar 2008
March 4, 2008 -- Kurt Ronse, IMEC's director of lithography, reviews that group's progress on EUV (first results on the alpha tool) and double patterning with Solid State Technology's Senior Technical Editor Debra Vogler.

SPIE REPORT: Optics, EUV competing for the 22nm node

Tue, 3 Mar 2008
by Griff Resor, Resor Associates
Mar. 4, 2008 - With 38nm half-pitch seemingly the limit for single image 193nm immersion lithography, how the industry will reach the 32nm and 22nm nodes was the focus of last week's SPIE Advanced Lithography conference. Optics with double patterning, EUV, and e-beam direct write -- which will it be for 22nm? After a decade as a doubting Thomas, here's why I think the biggest IC companies will use EUV for the most difficult layers at the 22nm node.

SST On the Scene: SEMATECH's progress in immersion, EUV

Mon, 3 Mar 2008
March 3, 2008 -- Stefan Wurm, program manager, EUV strategy at SEMATECH, updates Solid State Technology's Senior Technical Editor Debra Vogler on that group's progress in immersion lithography and EUV. Highlighted is progress on EUV mask defectivity and the first integrated chip with a layer made using EUV lithography. He also discusses the nanocomposite approach to high-index immersion lithography and the consortium's efforts to monitor non-optical lithography methods (e.g., NIL).

Turning an immersion litho "defect" into a double patterning "feature"

Fri, 3 Mar 2008
by Bob Haavind, Editorial Director, Solid State Technology
A presentation by RIT engineers at this year's SPIE Advanced Lithography conference suggested the intriguing possibility of utilizing contrast differences for the TE/TM modes of exposure light to enable double patterning with frequency doubling imaging -- a technique that might provide a single-exposure alternative to double exposure/double patterning schemes at sub-45nm nodes.

Pixelated phase-shift computational techniques developed for sub-wavelength 4X maskmaking

Tue, 3 Mar 2008
by Bob Haavind, Editorial Director, Solid State Technology
Problems with complex circuit patterns using alternating phase shift masks for low k1 lithography led Intel to experiment with using trillions of pixels for imaging. A number of papers at this year's SPIE Advanced Lithography Conference described the techniques developed to successfully do the critical first metallization layer (M1) on a microprocessor using pixelated phase-shift masks.

Double development offers simpler double patterning

Mon, 3 Mar 2008
by Katherine Derbyshire, Contributing Editor, Solid State Technology
Traditionally, achieving high resolution with negative imaging has been difficult. Research presented by Fujifilm Electronic Materials at this year's SPIE Advanced Lithography conference showed how to tune the resist imaging threshold to clear "dark" and "bright" regions, and ultimately double the pitch frequency and thus the density of lines and spaces.

Rensselaer touts new polymer for conventional, nanoimprint litho

Sun, 2 Feb 2008
Feb. 2, 2008 - Scientists at Rensselaer Polytechnic Institute say a new cheaper, quick-drying polymer could enable better performance and lower costs in both conventional photolithography processes and on-chip nanoimprint lithography. Also seemingly heavily involved in developing the technology: Applied Materials.

February 2008 Exclusive Feature #1:
Yield at any cost

Tue, 2 Feb 2008
By Roy White, RAVE LLC, Delray Beach, FL USA

Photomask costs are a painfully visible issue in today's competitive semiconductor market. This puts substantial pressure on the profitability of photomask makers. Since the "mask makers' vacation" ended some 15 years ago, it seems every paper you read has another exorbitant estimate of future mask costs.

IBM, ASML, others gain SPIE Fellow honors

Wed, 2 Feb 2008
Feb. 27, 2008 - Eight new Fellows have been added to SPIE's roster to honor their scientific and technical contributions in optics/photonics/imaging, and to the group in particular. Also, receiving awards at this year's SPIE Advanced Lithography symposium were researchers from ASML, IBM, KLA-Tencor, and the U. of Wisconsin/Madison.

SPIE NEWS: Gigaphoton opens US office, squaring off on Cymer's turf

Tue, 2 Feb 2008
Feb. 26, 2008 - The war between two rival international lithography source providers has reached US shores. Gigaphoton says it is expanding its presence in the US with a new subsidiary in Beaverton, OR, following recent customer wins in the US region that represents one-fifth of the worldwide market.

Replisaurus decloaks with "middle of the line" metallization tech

Wed, 6 Jun 2008
by Françoise von Trapp, managing editor, Advanced Packaging
June 11, 2008 -- Replisaurus has maintained a low profile since announcing their first round of funding in August 2006, but there's been a lot going on for the start-up company. With last week's announcement of the company's acquisition of Smart Equipment Technologies (SET), the company is ready show the world what it's been up to.

Intel eyes scalable FBC technology for 15nm and beyond

Tue, 6 Jun 2008
One of the papers being presented by Intel at this week's VLSI Symposium describes fabrication of the smallest reported floating body cell planar devices, seen as a potential replacement for standard transistor cache memory. Functional devices have been made measuring down to 30nm gate lengths, with a possible introduction at the 16nm node.

Toppan touts first 32nm-capable photomask process

Fri, 6 Jun 2008
June 12, 2008 - Toppan Printing Co. Ltd. says it has developed the first 32nm-generation photomask manufacturing process, for 193nm immersion (water) lithography, targeting volume production by June of this year. But how did the company overcome known problems with double patterning? And how compatible is it with non water-based immersion?

Report: Japan firms tout 2x efficient nonmercury UV source

Fri, 6 Jun 2008
June 19, 2008 - Researchers at Kobe U. and Yumex have prototyped a UV light source made without mercury and twice as efficient as existing mercury lamps, with a commercial product possibly ready in two years, according to the Nikkei Business Daily.

IMEC tips streamlined HK+MG steps, touts 32nm high-k, Ta gate improvements

Tue, 6 Jun 2008
June 17, 2008 - At this week's VLSI Symposium (July 17-20, Hawaii), IMEC says its researchers say they have improved performance in planar CMOS using hafnium-based high-k dielectrics and tantalum-based metal gates for the 32nm node, reduced inverter delay by 33% (15ps to 10ps) and simplified the HK+MG process from 15 steps to nine.

Process integration drives the IC industry

Fri, 6 Jun 2008
by Ed Korczynski, Senior Technical Editor, Solid State Technology
The next 10 years will witness more changes in mainstream IC manufacturing technology than in the last 40 years combined. With rapidly escalating costs projected for ≤32nm-node digital CMOS manufacturing, IC companies are turning to analog, packaging, and heterogeneous integration to add greater value for lower cost and risk. In short: unique process integration challenges at each fab will drive everything.

Gartner trims capex outlook again; 2009 now in doubt

Wed, 10 Oct 2008
Semiconductor capital equipment spending had been expected to be lousy through 2008, but the upswing would start sometime in 2009. No longer -- Gartner now expects capex to slide even further this year and will drop another 13% in 2009, thanks to a full-on collapse in memory investments and economic pressures on consumer spending habits.

IBM: 22nm node will need "computational scaling"

Thu, 9 Sep 2008
The complexity design and process interactions at the 22nm node are so great that they will require a new level of computational power. Thus, IBM and select partners have devised a "computational scaling" strategy that provides an end-to-end look at technology development, and how to accept designs into technology for manufacturing.

Litho crossover at Diskcon

Wed, 9 Sep 2008
A full-day symposium at this year's Diskcon USA explored the lithography implications of sub-ITRS roadmap feature sizes on disk drives, with the challenge that HDD lithography must cost 10× less than NAND flash lithography, the lowest-cost semiconductor process.

HP optimizes low-cost processing for inkjet printheads

Fri, 8 Aug 2008
One of the most common and most ignored types of chips is on almost every desk in this electronic world of ours -- the inkjet printhead. This edition of Chip Forensics examines a three-color printhead device out of Hewlett Packard's low-cost HP 60 Tricolor ink cartridge launched earlier this year.

Litho vendors flirt with double patterning, but no date yet

Fri, 7 Jul 2008
Double patterning was the talk of the litho panels during SEMICON West and in pitches by top scanner makers ASML, Canon, and Nikon -- but still none have evolved their tools to offer the required overlay capability, with throughput sufficient to be profitable. Even the closest one of the bunch is billed as the "ultimate" single-patterning tool.

AMAT: Double patterning gaining favor for 3X litho

Thu, 7 Jul 2008
Execs from ASML and Applied Materials tell SST what's driving the re-emergence of memory as a driver for IC manufacturing, and how this trend is impacting development and adoption of new technologies such as double-patterning and EUV lithography.

Litho breakfast offers no surprises for 32nm

Fri, 7 Jul 2008
The content of Sokudo's annual lithography breakfast at SEMICON West on Wednesday was very similar to what one could have heard at SPIE back in February, but it was helpful to hear it again, focused on the 32nm node. There were no surprises, which was good news; a central theme was a review of double patterning methods, including Applied's spacer method.

Gigaphoton updates marketshare, EUV progress

Thu, 7 Jul 2008
Gigaphoton sat down with SST to discuss the company's penetration into the US market -- the home turf for its primary competitor -- and offer an update on its EUV product progress.

Molecular Imprints chasing multiple markets

Thu, 7 Jul 2008
In an interview at SEMICON West, Mark Melliar-Smith, CEO of Molecular Imprints described two paths for his company: one toward insertion into the semiconductor industry in 2009, and another toward producing a billion disks a year with 20nm features for the hard disk drive industry in 2010.

Rave "Rhazers" reticle haze

Wed, 7 Jul 2008
Rave's just-announced Rhazer tool offers a new scheme to deal with haze that builds up on reticles, and do it directly in a fab at a lower cost -- making it "the first real solution" to the problem of mask haze," according to one prominent industry expert.

Editor's Take: IMEC/ASML 32nm EUV rivals Intel work

Mon, 7 Jul 2008
IMEC/ASML's newly 32nm SRAM, partially built with EUV lithography, offers a possible contrast to how Intel is working with the litho technology.

IMEC, ASML: Another step closer to production-worthy EUV

Mon, 7 Jul 2008
IMEC and ASML give SST an inside scoop on their latest EUV milestone -- functional 32nm SRAM cells (FinFETs) -- and which technology is now under the gun to ensure a production tool is ready as advertised by the end of 2009.

Extending/complementing optical litho using S-FIL for memory applications

Fri, 7 Jul 2008
New technologies are needed to keep the semiconductor industry on track with Moore's Law. Step and Flash Imprint Lithography (S-FIL) has gained traction in recent years among several leading memory manufacturers.

Understanding characteristic EUV image variations in full-field exposure tools

Fri, 10 Oct 2008
A clear understanding of the physical origin of image CD and placement variations will make it possible for EUV users and optical proximity correction (OPC) vendors to develop OPC strategies at the 22nm and 16nm device nodes to effectively compensate for them.

To 32nm and beyond: SPIE panel debates assortment of challenges

Tue, 10 Oct 2008
What challenges must maskmakers overcome to reach the 32nm node, and what hurdles lie beyond? A star-studded panel of experts assembled at this year's SPIE Photomask Technology Conference (Oct 6-10) to examine the future.

ASML's new platform pushes ArF to the limit

Tue, 10 Oct 2008
A litho-etch, litho-etch (LELE) approach is one of several double patterning schemes concocted to help span the gap between current single-exposure 193nm immersion litho and EUV. But LELE places extreme demands on both the productivity and the performance of the lithography tool. ASML's new Twinscan NXT platform strives to address these challenges, as described at ASML's recent Eindhoven (Netherlands) press event.

Haze and sun for mask symposium

Tue, 10 Oct 2008
Highlights from last week's SPIE/BACUS Symposium on Photomask Technology in Monterey CA, include discussion of damage to pellicles caused by aggressive 193nm radiation, what's behind a new "sun effect" linked to clearing off reticle haze, more calls to replace chrome with opaque MoSi, why mask industry sales are improperly skewed, and the difficulty of migrating to smaller dimensions.

Fujitsu, e-Shuttle, D2S deal benefits maskless IC slice

Mon, 10 Oct 2008
The new partnership between Fujitsu Microelectronics, Advantest Corp. (through their JV, e-Shuttle), and startup D2S aims to make ICs faster and more cost-effectively for low- to mid-volume ASICs.

Report: Samsung, LG to roll out LCD steppers

Thu, 10 Oct 2008
In further efforts to cut production costs, and reduce reliance upon foreign technology providers, Korea's top two electronics manufacturers reportedly are in early stages of collaboration on development of steppers for LCD panel manufacturing.

Economics, design issues top device-scaling concerns

Wed, 7 Jul 2008
Concerns about the next steps in device scaling -- profitability at 32nm and beyond, challenges of double-patterning, worries about chipmakers' commitment to design-tool functionality -- were aired out in a SEMICON West TechXpot discussion.

AMD's 2020 Vision for 450mm: Leave inefficiency behind

Tue, 7 Jul 2008
There is a lot that can still be done to improve the efficiency of today's 300mm factories, and an early move to 450mm would only carry those inefficiencies forward another generation. That was the main message in an interview with Gerald Goff, principle member of technical staff for Advanced Micro Devices (AMD) in Austin, TX, during last week's SEMICON West.

SIA: Chip sales still chugging (slowly) in June

Mon, 8 Aug 2008
Memory concerns aside, there's still reason to be happy with growth in the semiconductor industry, mainly thanks to emerging markets' hunger for PCs and mobile phones, according to the latest data from the Semiconductor Industry Association (SIA).

IBM group builds 22nm SRAM cell

Mon, 8 Aug 2008
IBM and joint development partners (AMD, Freescale, STMicroelectronics, Toshiba, CSNE in Albany, NY) say they have built a working static random-access memory (SRAM) using 22nm process technologies -- but details will have to wait until December's IEDM.

MoSi-ing along to 32nm

Mon, 8 Aug 2008
The chrome material that has blocked the light on binary masks for a generation may finally have outlived its usefulness, with interest now turning to opaque OMOG for 32nm generation and beyond photomask technology, explains Toppan Photomasks' Franklin Kalk, in an exclusive interview with SST.

KLA-Tencor pitches double-patterning with Prolith 11

Wed, 8 Aug 2008
In a post-SEMICON West interview, Edward Charrier, VP/GM of KLA-Tencor's process control information division, described the latest improvements in Prolith, the company's venerable litho simulation tool.

Toppan, IBM tie off 32nm photomask work, eye 22nm

Fri, 6 Jun 2008
June 19, 2008 - Toppan Printing and IBM have forged a new development agreement covering the final phase of 32nm photomask process development, and all phases of 22nm photomask process development. Work will start this month at IBM's photomask facility in Essex Junction, VT.

Report from the VLSI Symposium: Planar CMOS to 22nm, but no more

Tue, 7 Jul 2008
Overall agreement at this year's VLSI Symposium (June 16-19, Waikiki, Hawaii) was that planar CMOS is extendable to 22nm node but unlikely beyond that. By the 16nm node SRAMs will need FinFETs or a trigate-like design, which can be fabricated in bulk wafers rather than SOI wafers, as first reported by Toshiba in 2006 and now many others.

Analysts: KLAC+Vistec is a mask metrology play

Thu, 7 Jul 2008
Gartner and VLSI Research analysts tell SST what's the driving interest behind KLA-Tencor's proposed acquisition of Vistec Semiconductor Systems' inspection business, and where areas of overlap might be leveraged to take on other sector competitors.

Report: Macronix eyes NOR battle vs. Spansion, Numonyx

Wed, 4 Apr 2008
Apr. 23, 2008 - Taiwan's Macronix plans to push into NOR flash for handsets within the next three years, placing it in direct competition with Spansion and Numonyx, according to a local report.

Analyst's "contrarian" view: ASML set to outperform

Wed, 4 Apr 2008
Apr. 23, 2008 - A pending memory recovery later this year and more migrations to smaller technology nodes will spur another round of immersion tool orders for ASML, according to an analysis from FBR Research.

ZMD sells SRAM biz to Alliance

Fri, 1 Jan 2008
Jan. 17, 2008 - ZMD AG has sold its complete SRAM product line to San Carlos, CA-based Alliance Memory, including manufacturing rights, mask sets, IP and all remaining inventory.

Expert interview: European collaborative programs

Tue, 4 Apr 2008
by Brian Dance, European Contributing Editor, Solid State Technology
Ian Burnett, past chairman of JEMI UK, tells WaferNEWS European correspondent Brian Dance what was successful about the just-completed MEDEA+ R&D programs, and how the new programs dubbed CATRENE will force the R&D community to relate expenditures to tangible benefits for society -- and "become the blueprint for government supported R&D not only throughout Europe but at a global level."

KLA-Tencor's WPI software disposes defects

Mon, 4 Apr 2008
by M. David Levenson, Editor-in-Chief, Microlithography World
April 21, 2008 - KLA-Tencor's Wafer Plane Inspection software attempts to do with computation what Zeiss' AIMS and Applied Materials' Aera2 try to do with optics: sort printable defects from harmless anomalies and false defects (backed up in a paper coauthored with Intel). Success will facilitate meaningful inspection of complicated OPC masks, and more creative solutions to advanced imaging problems employed in production.

AMAT's Aera redux

Wed, 4 Apr 2008
by M. David Levenson, Editor-in-Chief, Microlithography World
April 16, 2008 - With aerial images now having simpler geometry than OPC mask designs, it may be time for aerial image inspection to replace microscopic mask measurement. If it performs as advertised, Applied Materials' reentrance into the mask inspection tool market, the Aera2, could enable more aggressive RET strategies, lower reticle costs, and help make chip yield more predictable at 45nm and 32nm.

IEDM Day 4: Sub-45nm roundup

Fri, 12 Dec 2008
Wednesday morning at IEDM was an endurance test, with nine consecutive papers on 22, 32, and 45nm devices. A lot of strained silicon, and not a few strained attendees! Rather than cherry-pick, here's a run-through of Session 27.

IEDM: IMEC touts 11MP micromirror array

Tue, 12 Dec 2008
Dec. 15, 2008 - In a paper discussed at this week's IEDM, researchers from IMEC reveal a monolithically integrated 11-megapixel 10cm2micromirror array, double the pixel density of comparable micromirrors, and a 10312 cycle mechanical lifetime, also a record, they claim.

IEDM Day 1: Dense data on 22nm

Mon, 12 Dec 2008
In an exclusive daily blog for SST, Chipworks' Dick James soaks in the first day of IEDM with dense presentations of 22nm CMOS presentations.

Intel decloaking 32nm logic tech at IEDM

Mon, 12 Dec 2008
Intel's 32nm logic technology will be described in a paper to be presented at the IEDM conference this week by Sanjay Natarajan, the company's director of 32nm CMOS technology development.

IMEC, U.Albany combining EUV efforts

Mon, 1 Jan 2008
Jan. 21, 2008 - The two leading R&D centers for EUV lithography, IMEC in Europe and the U. of Albany's College of Nanoscale Science and Engineering (CSNE), say they will jointly perform experiments for EUV in order to "demonstrate the practical feasibility of EUVL and build confidence in the technology for the 32nm half-pitch device node and below."

IBM, Japan's Central Glass to make new photoresists

Fri, 1 Jan 2008
Jan. 11, 2008 - IBM and Central Glass have agreed to jointly explore use of fluoromaterials (materials that contain fluorine atoms) in developing photoresist materials for future semiconductors.

IMEC's Ronse: Albany-IMEC joint EUV work not giving up on 32nm-hp, yet

Wed, 1 Jan 2008
Jan. 23, 2008 - In an exclusive interview with WaferNEWS, Kurt Ronse, lithography program director at IMEC, discusses the newly announced partnership with the U. of Albany's College of Nanoscale Science and Engineering to accelerate development of extreme ultraviolet (EUV) lithography technology -- what finally pulled the two sides together, what they hope to gain short- and long-term, and plans for readiness by the 32nm and 22nm half-pitch nodes.

Fujifilm materials biz buys ArF immersion tool to monitor photoresists

Mon, 1 Jan 2008
Jan. 21, 2008 - Fujifilm says its electronics materials subsidiary has purchased an advanced argon fluoride (ArF) immersion scanner to help accelerate the push to bring its new family of ArF immersion photoresists to high-volume manufacturing.

Elpida touts 50nm DRAM

Wed, 11 Nov 2008
Elpida Memory says it has completed development of a 50nm DDR3 SDRAM that's twice as fast as Samsung's version, with what the company says is the lowest power consumption available (1.2V operation).

AMAT's compact cleaning cluster for masks

Wed, 4 Apr 2008
by Ed Korczynski, Senior Technical Editor, Solid State Technology
April 23, 2008 - Cleaning has always been essential for mask manufacturing, but today there is increasing concern to the point where fabs may soon clean masks in-house to prevent haze buildup. Meanwhile, EUV and NIL don't use pellicles, which almost certainly will mean cleaning masks in production. Seeking to address this need/opportunity is Applied Material, with its new Tetra Reticle Clean tool.

IMEC's vision of next-generation memory

Thu, 11 Nov 2008
The industry has established a collection of production-worthy high-k gate stack options, and fabs will adopt their own such processes gradually. While research institutions are winding down their work in this area, there's still future research to be done on high-k dielectric materials (e.g. for memory scaling), as IMEC researchers discussed at their annual press review.

When photoresist is not enough

Wed, 11 Nov 2008
Pattern transfer is becoming trickier at 4x/32nm nodes and beyond, with thinner resist layers and higher aspect ratios/etch requirements for both logic and memory. Enter ashable hardmasks as a possible solution. Novellus VP Tim Archer tells SST about the company's strategy and technology to address this pain point.

45nm node registration metrology for EUV reticles

Wed, 11 Nov 2008
Tighter registration tolerances for the 45nm node and beyond require a next-generation registration metrology tool with capability to measure EUV masks with diverse substrate materials that might be used in 32nm and 22nm chip production.

E-beam, nanoimprint, and novel lithographies approach semiconductor mainstream

Tue, 4 Apr 2008
by Tom Cheyney, Senior Contributing Editor, Small Times
Electron-beam direct write, nanoimprint lithography (NIL), and other potentially disruptive semiconductor nanopatterning technologies drew strong attendance and elicited spirited discussion during the SPIE Advanced Lithography conference, as Small Times' Tom Cheyney reports.

NIST: NIL actually improves nanoporous layers

Wed, 4 Apr 2008
Apr. 30, 2008 - NIST says its work has helped resolve whether nanoimprint lithography (NIL) can accurately stamp delicate insulating structures without damage -- and in fact makes them better.

Suss, Philips developing new nanoimprint tech

Tue, 4 Apr 2008
Apr. 29, 2008 - Suss MicroTec and Philips Research say they are partnering to develop a new nanoimprint lithography technology targeting a niche in sub-50nm patterning between small rigid stamps and larger soft stamps.

Maskless litho program launched in EU

Fri, 4 Apr 2008
Apr. 25, 2008 - The European Commission's 7th Framework Program (FP7) is funding a new program on maskless lithography for IC manufacturing -- MAGIC -- to explore and promote maskless lithography technologies developed by a pair of European companies, including developing infrastructure on data preparation, proximity effect corrections, and processes.

Freeze frame: JSR closes in on double-patterning at 22nm

Thu, 4 Apr 2008
by Debra Vogler, Senior Technical Editor, Solid State Technology
April 3, 2008 - JSR Microelectronics tells WaferNEWS about its new "freezing material" targeting brightfield applications (i.e., line first double-patterning (DP) processes), and why logic and some memory applications should be a good fit.

Qcept, CEA-Leti to explore leading-edge characterization, yield

Wed, 5 May 2008
May 28, 2008 - Qcept Technologies and European R&D organization CEA-Leti have inked a deal to investigate techniques for characterizing leading-edge semiconductor materials and processes, including high-/low-k dielectrics, atomic layer deposition (ALD), fully silicided (FUSI) metal gates, and advanced cleaning technologies.

Chartered's Lin: Three-way push in litho needed to keep scaling alive

Wed, 5 May 2008
by Bob Haavind, Editorial Director, Solid State Technology
May 21, 2008 - The future of lithography from the viewpoint of a major foundry was presented at ConFab by Chartered Semiconductor 's K.K. Lin. Concurrent advances across a trilogy of disciplines (physical and computational lithography, including OPC/RET, and DFM) will be required to keep scaling alive, he said, and litho tool contenders face some significant challenges -- but with key advantages too.

Intel: EUV seen ready at 16nm; mask infrastructure challenges are key

Wed, 5 May 2008
by Debra Vogler, Senior Technical Editor, Solid State Technology
Having essentially crossed EUV off its 22nm plans, Intel is looking forward to getting it ready for the 16nm node -- but also is wary of addressing mask infrastructure needs as well, notes Janice Golda, the chipmaker's director of litho capital equipment development, in her presentation at the Confab.

Nikon looks to EUV to reduce the mask cost trend for critical layers

Wed, 5 May 2008
by Debra Vogler, senior technical editor, Solid State Technology
May 21, 2008 - This year's SPIE Advanced Lithography Conference saw glimmers of hope that EUV might be ready in time for 22nm hp. Speaking at the ConFab event, Kazuo Ushida, president of Nikon Precision Equipment Co., agreed that EUV was still the most promising solution for 22nm, and the only one that would keep the industry on track to meet cost/bit reductions needed to stay within historical guidelines.

Slowly but surely, EUV moves toward reality

Thu, 10 Oct 2008
EUV lithography is still a long way from manufacturing, not expected for mass production until at least 2012 and the 22nm node. But early work with alpha tools is giving a much better understanding of what the platform's capabilities will be, and where the needs are (optics, resists, sources). And at some point the answers will come only with taking risks and making the investment.

Gartner: Caution, uncertainty extend 2008 capex slump, cloud 2009 recovery

Thu, 7 Jul 2008
Gartner has lowered its capex forecast yet again amid a bursting memory industry bubble, global economic uncertainties, and "little upside potential currently visible for the near term."

Making scanners march in step

Tue, 12 Dec 2008
Brion Technologies, an ASML company, has developed a suite of products to optimize the performance of diverse scanners so that challenging chip patterns can be manufactured in parallel, on old and new tools, at high volume.

Carl Zeiss delivers "complete" optics for production EUV

Thu, 9 Sep 2009

Carl Zeiss says it has delivered "a complete optical system for production-ready EUV" in an ASML tool. The entire completed system with projected 60 wafers/hour throughput is expected in 2H10 targeting 20nm node manufacturing.


HDD patterned media using jet-and-flash imprint lithography

Fri, 9 Sep 2009

This article from Molecular Imprints describes how te addition of patterned media to HDD disk fabrication presents a number of new challenges to magnetic media manufacturers, and how J-FIL systems and materials can provide the foundation for successful high-volume manufacturing.


IBM: DNA "scaffolding" builds tiny circuit boards

Mon, 8 Aug 2009
Researchers at IBM and the California Institute of Technology say they have come up with a solution to problems looming for future semiconductor manufacturing beyond the 22nm node: a combination of lithographic patterning and self-assembly that arranges DNA structures on surfaces compatible with current manufacturing equipment.

Luc Van den hove helms IMEC, discusses strategy

Tue, 6 Jun 2009
Amid preparations for IMEC's 25th anniversary celebration, SST spoke with Luc Van den hove, now president/CEO of European R&D consortium IMEC, who discussed the research center's strategy and the keys to its success over the years.

SEMATECH takes on funding challenge for EUV mask infrastructure

Tue, 6 Jun 2009
In a pre-SEMICON west technology briefing, SEMATECH's director of lithography, Bryan Rice, gave a sobering assessment of the readiness of EUV mask infrastructure -- currently, there are no commercial suppliers committed to building solutions for high-volume manufacturing mask blank inspection, mask defect inspection, and patterned inspection.

Intel Research Day: Update on EUV, other projects

Fri, 6 Jun 2009
A highlight at Intel's annual research open house held this week, amid general updates on eco-innovation, 3D graphics, mobility, and enterprise computing, was a roundtable discussion of the company's manufacturing research, including a summary of the status of EUV.

Does Tela-Blaze M&A spell end of DFM consolidation?

Tue, 2 Feb 2009
Tela Innovations' announced acquisition of Blaze DFM essentially clears the industry playing field of startup DFM shops -- but that doesn't mean consolidation is entirely over.

Brion Technologies unveils SMO technology at SPIE

Fri, 2 Feb 2009
Brion Technologies, a division of ASML, says its upgraded Tachyon source mask optimization (SMO) product targeted for the 22nm node, debuted at the SPIE Advanced Lithography Conference, enables full co-optimization of source and mask, witwh process windows improved by >40%.

IBM's Farrell: Computational litho, scaling to 16nm

Wed, 2 Feb 2009
Tim Farrell, distinguished engineer at IBM's semiconductor R&D center, provides an update on efforts to implement comprehensive computational scaling computational scaling to 22nm, and discusses the possibilities at 16nm.

MII's template replication system enables patterned media manufacturing

Thu, 9 Sep 2009
Molecular Imprints CEO Mark Melliar-Smith tells SST how the company's new Perfecta TR1100 template replication system for patterned media applications, in concert with its jet-and-flash imprint lithography tech, enables mass-replication of master imprint templates with high fidelity at an orders-of-magnitude lower cost vs. fabricating the original master template.

Microbridge and e-test opens defectivity reduction

Tue, 5 May 2009
In BEOL lithography layers, microbridge defects can manifest as catastrophic single-line open circuit faults in the metal lines of the finished device. Enhanced filtration of bi-layer resist and post-develop ozonated UPW is shown to contribute significantly to reduction in post-litho microbridge defects, and ultimately reduction in single-line opens at e-test.

Developers push c-Si efficiency toward 20% with help from narrower interconnect

Wed, 8 Aug 2009
Photovoltaic cells are getting steadily more efficient, and even the small area taken up by interconnect is shrinking to get more electrons flowing. Some of these developments were discussed at the recent Photovoltaic Specialists Conference in Philadelphia and at the accompanying PV America exhibition.

Collaboration, manufacturing innovation vital for next-generation foundries

Fri, 6 Jun 2009
Samsung engineers discuss advancements in manufacturing using the company's S1 fab, a state-of-the-art 300mm foundry line, as an example in the areas of patterning and closed loop variation control systems.

The reliability margin of interconnects for advanced memory technologies

Fri, 5 May 2009
The trends of decreasing dimensions and new materials motivated the investigation of how these may affect the dielectric reliability of the interconnect structures.

Ultratech: Melt LSA at sub-16nm, readying move to FinFETs

Wed, 9 Sep 2009

Ultratech execs Art Zafiropoulo and Jeff Hebb update SST on the status of laser-spike anneal (LSA) technology: readiness for 32nm, extendibility to 22nm, and evaluation for 16nm and beyond.


KLA-Tencor goes for 2xnm trifecta with Teron 600 reticle defect inspection platform

Tue, 9 Sep 2009

September 14, 2009 - KLA-Tencor exec Dan Lopez gives SST a preview of its new Teron 600 Series mask defect inspection system, with programmable scanner-illumination capability and improvements in sensitivity and computational lithography power to address a major transition in mask design at the 2Xnm logic (3Xnm half-pitch memory) node.


SPIE/BACUS: Patterned media is fertile ground for mastering, replication, metrology developments

Thu, 9 Sep 2009

Several papers presented at last week's SPIE/BACUS Symposium described the mastering, replication and metrology challenges of patterned media, writes Toppan Photomasks' Franklin Kalk, reporting exclusively for SST.


SPIE/BACUS: NIL in patterned media...but when for ICs?

Fri, 9 Sep 2009

Reporting exclusively for SST, Toppan Photomasks' Franklin Kalk reviews papers from the SPIE/BACUS Symposium that mapped nanoimprint lithography's intersection with patterned hard-disk media, and discussed how to resolve the key technical issues that have prevented its traction in semiconductor manufacturing.


Making E-beam direct write faster

Thu, 11 Nov 2009

E-beam direct write lithography using character projection capability has the potential to enable maskless production for systems-on-chip at leading-edge technology nodes. Advantest and D2S describe their collaborative work that yielded a 4× increase in the number of characters available on EBDW stencil masks, a key factor in achieving the throughput increase needed to make maskless SoCs practical.


Toshiba discloses molecular resist for EUV litho

Wed, 11 Nov 2009

Toshiba Corp. says it has developed a high-resolution photoresist specifically for extreme ultraviolet (EUV) lithography, viable to the 20nm-scale generation.


Pressure control for reduced microbubble formation

Tue, 11 Nov 2009

Microbubbles in leading-edge photoresist materials can distort the exposure pattern and affect yield, sometimes even if proper steps are taken. Entegris' Jennifer Braggin discusses results of a study in which positive pressure applied on the chemistry before the dispense nozzle reduces microbubbles in top anti-reflective coating (TARC).


COO benefits in manufacturing mobile displays with steppers

Mon, 11 Nov 2009

Frank Bok Namgun and Philippe Cochet from Azores discuss the various cost-of-ownership merits of steppers vs. scanners in photolithography for flat-panel displays, including capital equipment and mask costs.


Doubleheader out of SEMATECH's RMDC

Tue, 5 May 2009
A recent collaboration between SEMATECH and Japan's TOK presents an opportunity for a look at the consortium's Resist Materials and Development Center, and its 22nm litho efforts and progress toward "manufacturable EUV."

A new NGL between ArF Immersion and EUVL

Tue, 5 May 2009
Lasertec describes a proposal for a new NGL that uses a DUV light source oscillating at 172nm or 175nm -- at this wavelength, higher-index materials such as BaLiF3 can still be used enabling 32nm half-pitch by a single exposure.

Litho firms climb up heap in bloody 2008

Wed, 3 Mar 2009
In a year that ultimately was terrible for the semiconductor industry, a few firms managed to claw their way up the list of sales leaders, though the top firms remain well entrenched, according to data from VLSI Research.

SPIE observations: EUV vs. "all other" litho

Tue, 3 Mar 2009
Ken Rygler offers his view of this year's SPIE event, and what's at stake in a proposed divergence of focus into EUV and "all other" litho technologies.

SPIE tracks the tightening litho horse race

Mon, 3 Mar 2009
How much longer can the industry stay on an 'optics forever' path? EUV is gaining momentum and closing the gap, with most infrastructure in place (but one missing piece could be a "showstopper"). This year's SPIE's Advanced Lithography Conference in San Jose, CA, provided a detailed update on this tightening horse race.

Coopetition via radical collaboration

Fri, 3 Mar 2009
Mark Slezak, director of lithography technology at JSR Micro, weighs in on Bernie Meyerson's (IBM) SPIE keynote urging industry "coopetition" -- a concept he notes is already alive and well in the materials sector.

Making a pitch for EUV

Wed, 3 Mar 2009
Stefan Wurm, AMD assignee to SEMATECH and associate director of the lithography division, believes the industry wants to see EUV lithography work in anticipation of its potential at 22nm, 16nm, and possibly 11nm.

SPIE panel: DP is only litho solution for 22nm volume production

Tue, 3 Mar 2009
Several lithography candidates seem promising for patterning circuits at 22nm and beyond: EUV, nano-imprint, direct write, and optical double patterning methods. But at an afternoon panel at SPIE hosted by Applied Materials, it became clear that only double patterning can deliver the necessary balance of performance and cost required for 22nm volume production.

Status report: 1X mask infrastructure

Sun, 3 Mar 2009
Mark Melliar-Smith, CEO of Molecular Imprints, discusses the company's work to develop a 1X mask infrastructure.

Analysis of the effect of point-of-use filtration on microbridging defectivity

Fri, 12 Dec 2009

Microbridging defects have emerged as one of the top yield detractors in immersion lithography at the 32nm node and beyond. This study from Entegris, IMEC, and Sokudo examines the effect of point-of-use filtration and how it is best used to mitigate microbridging defectivity.


IEDM: Scaling to continue, but with fully depleted "disruption"

Tue, 12 Dec 2009

Scaling will continue to follow the Moore's Law pace and will continue to rely on silicon to the 11nm node and beyond, although the emergence of fully depleted devices will disrupt device architectures, predicted Ghavam Shahidi from IBM research division, in a talk at this week's International Electron Devices Meeting (IEDM).


ASM, Air Liquide to work on advanced high-k ALD

Tue, 12 Dec 2009

ASM International NV has licensed key processes and material IP to the Air Liquide Group, related to deposition of advanced ultra-high-k insulator films such as yttrium-doped zirconia, STO, and BST, used most recently as gate insulator material in logic manufacturing.


Samsung: R&D moving to 32/28nm foundry process

Tue, 11 Nov 2009

Samsung Electronics says it has begun focusing its R&D on advanced logic process development for its foundry business, leveraging synergies with its memory development and work with partners and consortia.


ITRI adds AMAT tools for 3D IC work

Fri, 10 Oct 2009

Taiwan's Industrial Technology Research Institute (ITRI) will add Applied Materials to its partners for developing 3D chip stacking technology, by placing "a full line" of AMAT processing tools in its labs.


Die-scale stress management to advanced annealing optimization

Fri, 8 Aug 2009
Lithography overlay and leakage requirements are becoming increasingly stringent for the next-generation devices. Two case studies illustrate the role that stress non-uniformity has in misalignment and the effect of cumulative stress variations on device performance and leakage.

Using soluble gap-fill materials in VFTL integration

Wed, 8 Aug 2009
Cu wiring based on dual damascene is beginning to hit fundamental limits of current via-first, trench-last (VFTL) integration, but thicknesses of films in the lithography stack for trench patterning can't scale as rapidly. This article outlines a novel approach for eliminating these variations using existing processes and equipment.

Extending double-patterning to 22nm

Wed, 8 Aug 2009
Hamid Zarringhalam, EVP, technology, sales and marketing at Nikon Precision, talks about the need to extend double-patterning immersion lithography to 22nm. He also describes solutions to meet overlay accuracy requirements and a target throughput of 200wph.

Double-patterning design challenges

Thu, 8 Aug 2009
With the move towards fabless models and the use of double-patterning, it is critical that layout designers and manufacturing engineers remain engaged in the discussion of effective design rules that provide the types of yield, predictability and cost information that IC companies require.

Litho contaminants: Getting ready for EUV

Wed, 8 Aug 2009
Jitze Stienstra, director, gas microcontamination, at Entegris, discusses the challenges of managing contaminants in leading-edge lithographic processes. When the industry begins using EUV lithography, the materials of construction of the tools, the process materials, wafers, reticles, and the photoresists, will all be potential sources of contamination.

EUV: "Turned the corner to inevitability"

Tue, 7 Jul 2009
SEMATECH's Bryan Rice gives a positive assessment of EUV and offers hope for getting companies to open their checkbooks for mask inspection infrastructure funding. It's no longer a matter of "if" but "when," he says -- and see news below of an imminent 100W source.

EV Group uncrates NIL stepper for micro-optics, nano R&D

Mon, 7 Jul 2009
EV Group has unveiled a next-generation UV-nanoimprint lithography (NIL) step and repeat system eyeing use for microelectronics applications including optics/image sensors, lens arrays, and certain R&D nanoelectronics processes.

Cymer ships 75W LPP EUV tool to ASML

Mon, 7 Jul 2009
July 13, 2009 - Cymer says it has delivered the world's first fully integrated laser produced plasma (LPP) EUV lithography source to ASML, achieving 75W of full-die exposure power, and says the system will hit 100W "within the current quarter," enabling 60 wafers/hr throughput.

MII continues bid to make J-FIL the choice over EUV for NVM

Mon, 7 Jul 2009
On the heels of new funding and mask tool support from DNP, Mark Melliar-Smith, CEO of Molecular Imprints, lays out his case for imprint lithography vs. EUV for post-193nm lithography, particularly in memory.

The year ahead: A time for innovation

Thu, 1 Jan 2009
Technology-driven growth is still possible in the current downturn, according to SST's poll of executives from across the semiconductor manufacturing supply chain. Even during an economic slump, they remain optimistic about two things: the continuing need to innovate, and the ineveitable upturn.

Semiconductor and HDD manufacturers turning to imprint lithography

Thu, 1 Jan 2009
To paraphrase Samuel Johnson, nothing focuses the mind like an economic meltdown. The semiconductor industry and its capital equipment suppliers were already in the midst of a severe downturn as we entered the fourth quarter of 2008. Softening consumer demand and overcapacity in memory caused prices to plummet. Overlay the global credit crisis, and our industry faces challenges with a depth and breadth we've rarely had to face, even given our volatile history.

Foundries, IDMs will catalyze broad adoption of 3D/TSV and NIL

Thu, 1 Jan 2009
The macroeconomic issues that plagued the second half of 2008 will continue to impact the semiconductor and MEMS markets in 2009, specifically in segments that are automotive and consumer-product driven. Despite the effects, companies in these markets remain committed to innovation, and in turn, are expected to continue to invest in new manufacturing technologies (e.g., 3D/TSVs and nanoimprint lithography) to bring to market novel devices.

IITC 2009 preview: Innovation in copper contacts, 3D, metrology

Wed, 4 Apr 2009
IITC 2009 program chair Mike Shapiro (IBM) and publicity chair Mike Armacost (Applied Materials) brief SST on selected papers from the more than 80 technical presentations expected at the summer conference, held for the first time in Japan.

Gartner: Few unscathed in worse-than-thought 2008

Mon, 4 Apr 2009
A month ago Gartner pegged preliminary 2008 capex at a -25% slide to ~$33.46B. Turns out the firm was about $3B on the high side -- its "final" tally pegs 2008 semiconductor capex at just $30.7B, down -31.7% from 2007.

IMEC's Ludo Deferm: Behind the news

Fri, 7 Jul 2009
IMEC's Ludo Deferm provides a look behind some major announcements the consortium made at SEMICON West: laser anneal over spike anneal, EUV mask cleaning, RuTa metallization showing promise for 22nm PVD.

Report from the VLSI Symposium: Less spirited, still informative

Mon, 7 Jul 2009
This year's VLSI Symposium (June 14-17, Kyoto, Japan) was not as spirited as the past two years, which featured hot topics like high-k/metal gate approaches and bulk vs. SOI CMOS and planar vs. FinFETs, notes John O. Borland, in an exclusive report for SST. Nonetheless, many interesting papers and discussions emerged, notably finding out who else is adopting the same HK+MG scheme, and various analyses of device variability.

Enabling 22nm litho with double-sided silicon wafer polishing process

Fri, 7 Jul 2009
Peter Wolters CEO Kay Peterson tells SST how three key capabilities in the company's new double-sided polishing tools meet lithography challenges for 22nm and beyond semiconductor manufacturing.

Upgrade from KLA-Tencor provides access to design layout files

Mon, 7 Jul 2009
KLA-Tencor's new upgrade package for its 28XX broadband brightfield inspection systems enables access to standard IC design layout files, from which the inspection system can use knowledge of the defect's location within the circuit to better estimate its probability of affecting device yield.

Kalk: No litho option closed for 16nm

Thu, 7 Jul 2009
Franklin Kalk, CTO at Toppan Photomasks, lists the lithography options for 22nm-16nm and below (immersion/double patterning, EUV, imprint) and why no option should be closed until a cost-effective solution is available with which everyone can live.

Mapper delivers e-beam tool for Leti joint work

Tue, 7 Jul 2009
Continuing progress of the CEA-Leti-led three-year IMAGINE program to explore maskless lithography for the 22nm node and beyond, Mapper Lithography has delivered a "massively parallel" e-beam platform to Leti.

Double patterning's 22nm win for breakfast

Thu, 7 Jul 2009
Franklin Kalk of Toppan Photomasks reports for SST from Wednesday's Sokudo Lithography Breakfast, which offered a buffet of double patterning views as the transition from single-exposure 193i closes in at 40nm half-pitch.

ASML fulfills "holistic litho" plan with two tools, custom packages

Wed, 7 Jul 2009
Citing the embodiment of its concept of "holistic lithography," ASML has unwrapped two hardware/software components to help chipmakers improve lithography process windows while avoiding costly and timely steps and maintenance downtime.

ASMI, SAFC eye new ultrahigh-k mats for ALD

Tue, 1 Jan 2009
ASM International and SAFC's Hitech division have signed a partnership targeting atomic layer deposition (ALD) source materials for advanced ultrahigh-k (ULK) insulators targeting the 3x manufacturing node.

Optimizing lithographic stack materials when using hyper-NA exposure tools

Fri, 1 Jan 2009
As lithography pushes past 32nm resolution, the need to optimize stack materials, including resist, bottom anti-reflective coating (BARC), and substrate, has never been greater for IC manufacturers. This article describes a new simulation tool enabling engineers to more accurately model complex systems and make more informed decisions when selecting the best material solutions.

Editor's Take: IMEC sees 22nm EUV SRAMs as call to action

Tue, 4 Apr 2009
IMEC provides more details and some broader perspective on its progress using EUV lithography, now on 22nm SRAMs on both the contact and metal-1 layers.

Toppan's Kalk: 28nm tapeouts proceeding according to plan

Mon, 4 Apr 2009
Toppan Photomasks exec Franklin Kalk talks with SST about the joint work with IBM on photomasks for 32nm and 28nm semiconductor manufacturing, the key differences vs. 45nm-40nm work, the emergence of OMOG and SMO -- and eventually (and carefully), EUV.

MIT makes 36nm lines with "interference" litho step

Tue, 4 Apr 2009
A team of researchers at MIT have produced 36nm-wide lines using interference patterns and a photochromic material, and say the technique could be extended down to patterns on the scale of individual molecules.

Leverage strong cash position with leading-edge technology for continued growth

Thu, 1 Jan 2009
To successfully maneuver in today's restless economic waters, companies must possess a stellar balance sheet with a strong cash position, and provide leading-edge technology.

Yield management strategies need to keep pace with semiconductor innovation

Thu, 1 Jan 2009
Amid the gloomy outlook on IC demand in the coming quarters, many chip manufacturers are cutting back on their investments to build capacity. However, it is at this time -- when demand is at its softest -- that the wisest of chip manufacturers are continuing to make strategic investments in new manufacturing technologies and methodologies in order to position themselves to quickly ramp up on new chip designs when semiconductor demand inevitably swings upward once again.

Steady progress reported on HK+MG for ≤32nm

Thu, 1 Jan 2009
Chipmakers are trying many paths toward high-k metal gate dielectric (HK+MG) CMOS for 32nm and beyond, and papers presented at IEDM 2008 in San Francisco, CA, showed steadily improving results even though the routes may vary. Still, getting to uniform manufacturable devices presents some tough challenges.

Moving from DFM to MFD

Thu, 1 Jan 2009
As the global economic tide starts to recede, it exposes many high technology manufacturing challenges that were otherwise hidden. In the semiconductor industry, these challenges are often opportunities for innovation -- and the situation we face in lithography today is an excellent example.

Position for leadership with predictive computational manufacturing

Thu, 1 Jan 2009
In the quest to develop products with higher functionality at lower cost, the semiconductor value chain is struggling to cope with the increasingly complex technologies and expenditures needed to develop leading-edge CMOS products. Though the nature of these challenges is not new, their intensity is unprecedented.

EUV lithography approaches reality at IMEC

Tue, 10 Oct 2006
One of the first two full-field extreme ultraviolet (EUV) lithography systems in the world is now being installed at IMEC in Leuven, Belgium (the other is at Albany Nanotech in New York). Journalists were invited to visit the class-1000 cleanroom full of 300mm tools to see the huge system that is expected to replace immersion lithography after another two or three nodes.

Immersion Symposium report: Industry optimistic about commercial success

Tue, 10 Oct 2006
Attendees at the Third International Symposium on Immersion Lithography earlier this month, found a field moving out of R&D and into a competitive commercial phase. Key technical presentations addressed hyper-NA, resists, exposure tools, optical materials, process, photomasks, immersion defects, and alternative immersion fluids. More than 20% of submitted papers dealt with immersion defects, revealing the industry's momentum in preparing 193i for volume manufacturing at sub-65nm half-pitch.

DFM: Are we there yet?

Tue, 10 Oct 2006
The special Friday session of BACUS '06, organized by Bob Naber of Cadence, addressed the question of industry progress and readiness for DFM, and discussed the remaining challenges as well as proposed solutions. Mark Mason of Texas Instruments pointed out that "DFM is a journey, not a destination," and worried that management did not yet understand how hard it was going to be.

ASML, Gigaphoton ink litho support pact

Wed, 7 Jul 2006
July 26, 2006 - Laser light source manufacturer Gigaphoton Inc. said it will now support US customers of Dutch litho tool provider ASML, including laser installation and sustaining maintenance, and said the deal could expand to other parts of the world "in due course."

Photronics opens China maskmaking shop, hires Asia CTO

Wed, 7 Jul 2006
July 26, 2006 - Photronics Inc., Brookfield, CT, has officially opened its photomask manufacturing site in Shanghai, China, about three years after announcing plans for its formation. A production ramp is planned by 4Q06 at the facility in the Zhangjiang Semiconductor Industrial Park, which the company noted is the first merchant photomask fab to be brought online in the Shanghai region in more than a decade.

Magma, Brion linking tools for common litho modeling environment

Wed, 7 Jul 2006
July 19, 2006 - Magma Design Automation Inc. and Brion Technologies say they plan to link their technologies in order to create a common modeling environment for lithography. The combined environment, expected to be available in late 2006, will span physical design, physical verification, resolution enhancement techniques (RET), optical proximity correction (OPC), and OPC verification.

TSMC rolls out 65nm reference flow

Mon, 7 Jul 2006
July 17, 2006 - Taiwan Semiconductor Manufacturing Co. (TSMC) has introduced Reference Flow 7.0 for its 65nm process technology, offering statistical static timing analyzer, power management techniques, and various DFM enhancements, including tools from Magma Design Automation.

Dow corning, Rohm and Haas pair for sub-65nm litho coatings

Mon, 7 Jul 2006
July 10, 2006 - Rohm and Haas Electronic Materials Microelectronic Technologies and Dow Corning Corp. have renewed a joint development agreement to work on novel spin-on silicon hardmask antireflective coatings for sub-65nm lithography in flash, DRAM, and logic IC devices.

Cymer tips ArF source for 45nm immersion litho

Fri, 7 Jul 2006
July 6, 2006 - Cymer Inc. has unveiled an argon fluoride (ArF) laser light source targeting 45nm production immersion photolithography, touting a 1.5x improvement in energy stability performance and >20% reduction in cost-of-ownership vs. previous-generation ArF products.

Huge ALD market foreseen -- but when?

Tue, 8 Aug 2006
As features approach the dimensions of 2nm strands of DNA, atomic layer deposition (ALD) appears to have great promise for the very thin, conformal film layers that will be essential. It's already being used by DRAM makers and displays, but work on gate stacks is slow due to process and materials integration. Potential uses of ALD, and how this will drive the future market were explored in a panel at SEMICON West.

Panelists debate cost-sharing future materials R&D

Tue, 8 Aug 2006
During SEMICON West 2006, a group of the industry's top senior technologists came together to discuss the limits and possibilities for semiconductor material development. Dealing with the atomic limits of semiconductors materials engineering, and delivering very small amounts of material, may also require fundamental changes in business models. How can suppliers support themselves under a paid-per-gram materials model, when critical amounts delivered are now sub-gram?

Panelists debate impact, challenges of "atomic" progression

Tue, 8 Aug 2006
During SEMICON West 2006, a group of the industry's top senior technologists came together to discuss the limits and possibilities for semiconductor material development. One of the main themes of the technical seminar and panel discussion, sponsored by DuPont Semiconductor Materials, involved the ramifications of a clear shift toward dealing with individual countable atoms, and what kind of endgame it leads to in terms of materials development.

Notes from the IEEE Lithography Workshop: Progress, challenges, and promises

Tue, 8 Aug 2006
General observations from this year's IEEE Lithography Workshop suggest that immersion lithography may take a little longer to move into mass production than its champions would like, and the path to the 32nm half-pitch node is also not clear. Still, the pursuit of Moore's Law continues on many fronts, such as finding ways to "cheat" the "laws" of optical physics, or using organic self-assembly techniques to augment optical lithography.

Novel vacuum chamber moves with the wafer

Tue, 8 Aug 2006
New Way Air Bearings, Aston, PA, has created a new "vacuum chamber stage" demo system which could have application in lithography, ion implant, mask-writing, and metrology processes requiring high precision in deep vacuum. Essentially, instead of putting a precision stage into a vacuum, the vacuum is put into the precision stage -- so the chamber volume is little more than the size of the wafer, and all mechanical linkages are outside the chamber.

Analyst: Flip-chip demand boosting litho, wet etch markets

Wed, 7 Jul 2006
July 12, 2006 - A projected 28% compound annual growth rate for the flip-chip packaging sector will give a big boost to vendors of lithography and etch systems, according to data from The Information Network.

SEMICON WEST PREVIEW: Expanded innovation showcase spans gamut from desktop e-beam generation to electrically measuring low-k stacks

Mon, 6 Jun 2006
Visitors to SEMICON West once again will have the opportunity to conveniently meet with a range of entrepreneurs with new ideas at the Technology Innovation Showcase. This year SEMI has expanded it to three separate and more focused areas -- devoted to innovations in DFM and frontend processing, MEMS and nanotechnology, and final manufacturing technologies. Here's the rundown on a few intriguing innovations picked by a volunteer committee of industry executives to have the most potential.

Dongbu, Mentor partner for 90nm OPC tool

Thu, 8 Aug 2006
August 30, 2006 - Dongbu Electronics says it is now using an optical proximity correction (OPC) tool developed in collaboration with Mentor Graphics for 90nm wafer processing, extending earlier work that resulted in a 0.13-micron system.

Albany, IMEC parade first EUV tools

Tue, 8 Aug 2006
August 29, 2006 - European research consortium IMEC and Albany Nanotech say they have received the first extreme-ultraviolet (EUV) lithography full-field alpha tools from Dutch equipment developer ASML, apparently within days of each other. EUV is considered the most likely candidate for the 32nm half-pitch node.

Matsushita, Renesas now testing 45nm SoCs

Thu, 8 Aug 2006
August 3, 2006 - Matsushita Electric Industrial Co. Ltd. and Renesas Technology Corp. say they have entered full integration testing of 45nm system-on-chip (SoC) manufacturing technology. The process will be used by both companies in manufacturing SoCs for mobile products and networked consumer electronics products.

August 2006 Exclusive Feature:
DESIGN FOR MANUFACTURING

Enhancing flows when moving manufacturing into IC design

Thu, 8 Aug 2006
By W. Luo, D. Thon, Cadence Design Systems

With the move to more advanced semiconductor manufacturing technologies, semiconductor companies are finding that modifications to physical design data meant to improve yield can seriously impact integrated circuit (IC) performance and functionality. As a result, IC design houses are focusing growing attention on manufacturing effects at the earliest possible stages of IC design....

Synopsys confirms $20M deal for litho sim firm SIGMA-C

Wed, 8 Aug 2006
August 16, 2006 - Semiconductor design software provider Synopsys Inc., Mountain View, CA, has officially announced its acquisition of Munich-based simulation software developer Sigma-C Software AG in an all-cash transaction worth $20.5 million.

Examining litho progress, prospects at SEMICON West

Tue, 7 Jul 2006
In a first-day presentation at SEMICON West, Klaus Rinnen of Gartner/Dataquest reported a bright outlook for 2006, both for the semiconductor industry and its equipment suppliers, followed by a potential "soft patch" in 2007, and an upturn to record levels in 2008. That feeling of comfort combined with tempered optimism characterized the entire atmosphere at SEMICON West -- everyone seemed to feel that things were good now and the future no more uncertain than usual, in our cyclical industries.

Auto-fix for hot-spots in nanometer node designs

Wed, 7 Jul 2006
DFM start-up Takumi Technologies, building on its mask-data preparation (MDP) work for NEC and other customers, is now promoting its ability to automatically detect, classify, and repair yield-limiting design "hot spots" -- areas of a design layout which, due to process or geometric conditions, fall outside of process windows, resulting in potential catastrophic or parametric failure.

IMEC adds double-patterning to 193nm immersion, EUV litho efforts

Wed, 7 Jul 2006
July 12, 2006 - European research consortium IMEC has extended its research program for 193nm immersion lithography to include double-patterning techniques to address needs of leading-edge process technologies, particularly for flash memory devices. The program now runs parallel to IMEC's other lithography efforts targeting hyper-NA immersion and extreme-ultraviolet lithography (EUV).

Nikon, ASML ready for "last" battle with 193nm high-NA water immersion tools

Tue, 7 Jul 2006
In what should be the last roundup of water-based 193nm immersion lithography systems, two of the big lithography tool vendors are coming out with their latest tools targeting 45nm (logic) and 32nm (memory) semiconductor manufacturing. Nikon's NSR-S610C ArF immersion scanner (1.30NA) is scheduled for deliveries by year's end, while ASML's Twinscan XT:1900i with 1.35NA optics, is being prepped for deliveries sometime in mid-2007.

JMAR adds funding for C-RAM work

Wed, 8 Aug 2006
August 9, 2006 - JMAR Technologies Inc., San Diego, CA, has received an additional $3.1 million from the US Naval Air Systems Command to continue developing sub-100nm feature x-ray masks and next generation nanolithography, for use in fabricating high-speed chalcogenide random-access memory.

Brion, DNP ink deal to verify photomask production

Tue, 8 Aug 2006
August 8, 2006 - Brion Technologies and Dainippon Printing have signed a joint development program to combine their technologies into a system that can simulate and verify photomask pattern data prior to the printing of the wafer.

Brion adds marketing, bizdev, sales execs

Fri, 8 Aug 2006
August 4, 2006 - Brion Technologies says it is expanding its management roster following "considerable" growth over the past year, to help support work with partners spanning design to manufacturing and wafer metrology.

Analyst: Photomask growth slowing, marketshare gap narrowing

Thu, 9 Sep 2006
September 14, 2006 - Toppan Photomasks is seeing its lead shrink in the semiconductor photomask this year, as the overall segment adjusts to smaller growth due to design activity and a shift in capex from memory firms, according to a new report from The Information Network.

Nova puts litho metrology patents up for bids

Wed, 9 Sep 2006
September 6, 2006 - Nova Measuring Instruments, Rehovoth, Israel, is soliciting bids from approximately 100 companies to license six of its patents relating to use of a lithography tool with integrated metrology, and will even accept bids for outright ownership of the technology.

Photronics cuts 3Q outlook, cites FPD mask slump

Tue, 8 Aug 2006
August 1, 2006 - Photronics Inc., Brookfield, CT, has lowered its outlook for fiscal 3Q06, citing a shortfall in flat-panel display mask orders and shipments vs. previous forecasts, particularly in Korea and Taiwan.

PART II: Litho, metrology, mask/OPC tools make a splash at SEMICON West

Tue, 7 Jul 2006
Continuing his report on this year's SEMICON West, senior editor M. David Levenson looks at the latest tools for immersion lithography and e-beam, new metrology from startup firms, and innovations from companies involving mask substrate tuning and automating OPC.

Analyst: Litho, dielectric etch sole bright spots in 2007 tool market

Thu, 10 Oct 2006
October 12, 2006 - With the exception of two technology sectors, the overall market for semiconductor manufacturing equipment should be flat in 2007, as "enormous quantities" of chipmaking tools ordered in recent months is absorbed and new orders have slowed dramatically, according to analyst firm The Information Network.

ASMI votes to stay intact, make frontend unit profitable

Fri, 10 Oct 2006
October 6, 2006 - ASM International NV directors say they have decided to keep the company intact with both its frontend and backend business, and will concentrate on restoring its frontend business to profitability, negating a proposal from shareholders earlier this year calling for a split of the company's frontend and backend operations.

Litho panel probes concerns about the "Road" ahead

Tue, 9 Sep 2006
A somewhat surprising consensus on future lithography came out of a panel of experts at SEMICON West, with discussions of potential lithography solutions for the 32nm half-pitch node including major problems facing developers of EUV and high-index fluid immersion lithography using 193nm lasers. The message from panelists was clear -- the industry will have to learn how to live with dual-patterning at least for awhile, while toolmakers seek ways to boost throughput limits.

Nova putting litho metrology patent licenses up for bids

Wed, 9 Sep 2006
September 6, 2006 - Nova Measuring Instruments, Rehovoth, Israel, is soliciting bids from approximately 100 companies to license six of its patents relating to use of a lithography tool with integrated metrology, and will even accept bids for outright ownership of the technology.

Euro partners tout EUV infrastructure progress

Wed, 9 Sep 2006
September 6, 2006 - Focus GmbH and two German universities, Bielefeld and Mainz, working on a European Commission-sponsored project to develop extreme ultraviolet lithography (EUVL) technologies, say they have build a photoemission electron microscope capable of measuring features as small as 20nm without destroying the sample, a key step in development of EUV infrastructure.

Nikon, Synopsys to develop sub-45nm litho models

Wed, 9 Sep 2006
September 20, 2006 - Nikon Corp. and Synopsys Inc. are collaborating to develop "manufacturing-aware" optical proximity correction (OPC) and resolution enhancement technology (RET) lithography simulation models for 45nm-and below semiconductor process technologies.

ASML, SEMATECH qualifying RET for sub-45nm designs

Tue, 9 Sep 2006
September 19, 2006 - SEMATECH and its manufacturing-oriented subsidiary, the International SEMATECH Manufacturing Initiative (ISMI), have signed an agreement to incorporate ASML Holding NV's resolution enhancement techniques (RET) in order to qualify imaging performance of advanced logic patterns, metrology structures, and defect designs for the 45nm, 32nm, and 22nm technology nodes.

Magma, Synopsys keep firing after patents withdrawn

Mon, 9 Sep 2006
September 18, 2006 - Synopsys Inc. and Magma Design Automation Inc. have agreed to set aside dispute over three patents, but the two firms are still a long way from being nice to one another.

Fujitsu, Advantest form e-beam litho JV

Fri, 9 Sep 2006
September 15, 2006 - Fujitsu Ltd. and Advantest Corp. plan to collaborate on development of an electron beam direct lithography to use in semiconductor manufacturing using Fujitsu's 65nm and 45nm process technologies.

Inside the IBM/Chartered/Samsung chipmaking partnership

Tue, 10 Oct 2006
After leading much of IBM's technology development over a multidecade career, Walter Lange recently joined common platform alliance partner Chartered Semiconductor Manufacturing. In an exclusive interview with WaferNEWS during the recent Chartered Technology Forum (Sept. 28), Lange offered frank and insightful comments on Chartered's R&D strategy and its manufacturing goals, and some amusing stories of what it takes to prove a new technology really works.

SEMATECH touts sub-45nm dual-oriented features using 193i litho

Wed, 10 Oct 2006
October 4, 2006 - Researchers at SEMATECH North in Albany, NY, claim to have successfully patterned features narrower than 45nm (half-pitch) in multiple orientations using 193nm immersion lithography and azimuthal polarization, which allows for aggressive imaging of arbitrary circuit features beyond simple line-and-space test patterns.

Healthy photomask industry confronts data and RET challenges

Tue, 10 Oct 2006
Though growing at just half the rate of the semiconductor industry, the long-suffering maskmaking industry is presently in fine shape, according to experts at the 26th Annual BACUS Symposium on Photomask Technology in Monterey, CA, Sept. 18-22. Average yields are quite high, and most obvious failure modes are being successfully addressed. EUV maskmaking technology continues to improve, while high-index fluids and double processing technology still present a lot of challenges.

BOC, Aviza forge JDP to evaluate ALD precursors

Mon, 10 Oct 2006
October 30, 2006 - BOC Edwards and Aviza Technology Inc. have agreed to jointly develop atomic layer deposition (ALD) technology, combining BOC's chemical precursor formulation with Aviza's hardware to optimize deposition processes for high-k materials and metals.

ASML takes first EUV preproduction tool order

Tue, 10 Oct 2006
October 17, 2006 - ASML Holding NV says it has received the first order from an unidentified customer for a pre-production EUV system, following shipments of two alpha tools earlier this year to IMEC and Albany Nanotech.

Nikon, Brion team for "litho-enabled" DFM

Tue, 10 Oct 2006
October 10, 2006 - Nikon Corp. and Brion Technologies Inc. are partnering to combine Brion's high-performance computational lithography technology with Nikon's high-NA immersion equipment, to deliver "lithography-enabled DFM applications."

Cadence debuts "litho-aware" flow for Brion, Clear Shape tools

Mon, 10 Oct 2006
October 2, 2006 - Cadence Design Systems Inc. has announced what it calls a "lithography-aware" design flow that links resolution-enhancement technologies (RET) with physical design and verification.

October 2006 Exclusive Feature:
LITHOGRAPHY

Outlook for EUVL manufacturing insertion

Mon, 10 Oct 2006
By Stefan Wurm, SEMATECH, Austin, Texas

Extreme ultraviolet (EUV) technology maturity must be demonstrated by the performance of the first EUV lithography (EUVL) alpha tools, by the readiness of EUVL infrastructure to support beta-level EUVL lithographic performance in the near future, and by the overall cost of ownership (CoO) of EUVL. ...

Fujitsu, Advantest tip "e-Shuttle" details

Mon, 10 Oct 2006
October 30, 2006 - Fujitsu Ltd. and Advantest Corp. are offering more details about their upcoming 65nm-45nm prototyping service utilizing electron beam direct lithography, which might also pull in Fujitsu's optical prototyping services.

TEL adding Rudolph litho inspection to coater/developer

Thu, 10 Oct 2006
October 26, 2006 - Tokyo Electron Ltd. has signed a deal to integrate Rudolph Technologies' lithography inspection technology in its coater/developer tools, with worldwide distribution rights.

Nanometrics, ASML tie up for litho metrology

Thu, 10 Oct 2006
October 26, 2005 - Nanometrics Inc. and ASML Holding NV have entered into a cross-licensing agreement to incorporate Nanometrics' overlay and critical-dimension control metrology technology into ASML's lithography systems.

Toppan Photomasks revolves CEO spot

Mon, 5 May 2006
May 22, 2006 - Marshall Turner, president and CEO of Toppan Photomasks Inc., has stepped down after three years at the helm, leaving to return to his venture investment business. Ltd. David Murray, currently EVP of worldwide operations, will succeed Turner, and take his spot on the company's board of directors.

IBM's Meyerson: "Scaling is dead," long live collaborative innovation

Mon, 5 May 2006
The semiconductor industry needs to usher in a new era of "collaborative innovation" to push beyond the limits of classical scaling and achieve new advances in information technology price performance. That idea, proposed by The ConFab opening keynote speaker Bernard Meyerson, IBM fellow, VP strategic alliances, and chief technologist at IBM's Systems and Technology Group, set the tone for three days of top-level executive discussions on a range of issues facing chipmakers and suppliers alike.

ASMI lays out business case for shareholders

Fri, 5 May 2006
May 19, 2006 - At its annual meeting of shareholders, ASM International NV presented a "roadmap" for its corporate strategy going forward, and proclaimed it will achieve profitability in its maligned frontend equipment business in 2007.

ATDF, U-Texas open nano R&D center

Wed, 5 May 2006
May 17, 2006 - SEMATECH's R&D fab subsidiary Advanced Technology Development Facility (ATDF) and the U. of Texas-Austin have formed an Advanced Processing and Prototyping Center (AP2C), a specialized R&D program to develop leading-edge nanotechnology for use in semiconductor manufacturing.

Photronics, Micron kick off photomask JV

Mon, 5 May 2006
May 8, 2006 - Photronics Inc., Brookfield, CT, and Micron Technology Inc., Boise, ID, have officially formed a joint venture to develop and produce photomasks based on internal efforts to support 45nm chipmaking processes.

ASMI shareholder lays out demands for change

Fri, 5 May 2006
May 5, 2006 - Investment firm Mellon HBV Alternative Strategies, a 6% owner of ASM International NV, said it intends to attend the company's shareholders meeting on May 18 with its own agenda -- to come up with an endgame strategy for the company's frontend business, seen as not synergistic with its other areas of business.

SEMATECH names IBM's Lercel as litho head

Thu, 5 May 2006
May 4, 2006 - SEMATECH has appointed Michael Lercel as director of its lithography division, replacing former director Kevin Kemp who is returning to Freescale Semiconductor.

SEMATECH, Queensland U. working on high-index immersion photoresists

Thu, 5 May 2006
May 25, 2006 - SEMATECH and the U. of Queensland, Brisbane, Australia, have agreed to codevelop new resists for 193nm immersion lithography, in an effort to extend immersion technology for multiple generations.

TSMC lays out 65nm DFM plan

Wed, 5 May 2006
May 17, 2006 - Taiwan Semiconductor Manufacturing Co. (TSMC) has unveiled a 65nm design-for-manufacturing compliance "ecosystem" to channel DFM capabilities through selected EDA tools to TSMC's manufacturing data format.

April 2006 Exclusive Feature: LITHOGRAPHY

Processing and characterization of a positive thick photoresist

Fri, 5 May 2006
By Shang-Chou Chang, Shen Chi Hsieh, Kun Shan U., Taiwan; Tsung Chieh Cheng , Bau Tong Dai, National Nano Device Laboratories, Taiwan

OVERVIEW There is increasing interest in the thick, positive, epoxy-based photoresist made of the material AZ P4620 because of its wide applications in micro-fluidic devices and micro-electromechanical systems (MEMS). The optimization of polymerization for this material under near ultraviolet (UV) lithography...

Report from EIPBN: Accelerating the future of nano fabrication

Tue, 6 Jun 2006
We are entering a new era, in which nano-fabrication is moving beyond IC fabrication. Chasing Moore's Law is still an important challenge, but there are now other interesting challenges, such as making electronics ubiquitous, particularly in the medical field, and harnessing Nature's self-assembly methods. These were among the paths followed at the Electron, Ion, & Photon Beam Technology & Nanofabrication (EIPBN) held May 29 to June 2 in Baltimore, MD.

Firm touts part-per-quadrillion impurity analysis service

Fri, 6 Jun 2006
June 16, 2006 - Balazs Analytical Services, a division of Air Liquide Electronics US, has introduced a new analytical technique that can provide trace analysis of metal concentrations in water and process chemicals down to parts-per-quadrillion (ppq) -- 1ppq equivalent to one in a million billions.

NanoInk, SII ink photomask repair pact

Mon, 6 Jun 2006
June 26, 2006 - Seeking to provide nanoscale repair solutions to the photomask industry, NanoInk Inc. and SII NanoTechnology Inc. will modify NanoInk's dip-pen nanolithography technology and integrate it with SII's photomask repair instruments and nanomachining platforms.

Nantero, ON Semi continue nanotube-CMOS work

Fri, 5 May 2006
May 26, 2006 - Nantero Inc., Phoenix, AZ, and ON Semiconductor will pick up where Nantero and LSI Logic left off with work to integrate carbon nanotubes into CMOS fabrication. ON Semi acquired LSI Logic's facility in Gresham, OR, earlier this year, where the technology was being developed.

Analysts: litho market to "soften" in 2008

Fri, 5 May 2006
May 26, 2006 - Analysis from two firms predicts a soft market for lithography equipment in 2008, after leading-edge chipmakers are through placing initial orders for next-generation lithography tools.

Litho forum poll: We want 193nm immersion ready for 45nm

Fri, 5 May 2006
May 26, 2006 - Attendees at the SEMATECH-sponsored Litho Forum in Vancouver, BC, May 22-24 discussed the readiness of lithography technologies for the 32nm half-pitch and beyond technology generations, seen beginning in 2012, following the 45nm node generation expected to begin production in 2009.

Toward an open ecosystem for R&D

Thu, 5 May 2006
During a ConFab panel discussion on "Solutions to the R&D Challenge," Simon Yang, senior VP and CTO of Chartered Semiconductor Manufacturing, called for greater support of an industry-wide "open ecosystem of R&D" to deal with the impending R&D crisis. Several factors are converging to create a perfect storm in R&D, he said -- as scaling approaches physical limits, profit margins for technology and manufacturing companies are shrinking, and R&D operation costs are escalating out of control.

Can lessons from 300mm conversion keep the industry on the productivity roadmap?

Wed, 5 May 2006
A detailed economic model suggests that industry productivity will lag historical trends early in the next decade, slowing the decline in cost/transistor, unless new initiatives get underway to reverse this trend, reported Scott Kramer, director, International SEMATECH Manufacturing Initiative (ISMI), in a Tuesday afternoon presentation at The ConFab.

Litho costs won't limit Moore's Law, but technology is the key

Wed, 5 May 2006
Examining the history of lithography over the past two decades suggests that the choices ahead are similar to those that were successfully made in the past, suggested Kazuo Ushida, Nikon Corp., in his presentation on "Cost-effective lithography" at The ConFab. Comparing the array of future litho contenders in 2006 with the options considered in 1999, Ushida concluded that it looks like "deja vu all over again."

Innovation needed to tap huge potential markets

Tue, 5 May 2006
Enormous potential markets are emerging for semiconductors, said Jai Hakhu, corporate VP, Intel, at The ConFab. However, serving them will require continued innovation, and an intense focus on efficiency by the industry. Chips will have to provide multiple functions at lower price points to capitalize on the opportunities, he stated.

Pushing "Moore" out of lithography

Tue, 5 May 2006
Peter Jenkins, VP of marketing for ASML, described lithography options and challenges at the 32nm half-pitch for ConFab attendees. Among the challenges: there is no clear consensus on the part of IC manufacturers with respect to the kind of lithography needed at 32nm, although EUV is preferred for 22nm half-pitch.

Economics of sub-45nm chipmaking for equipment suppliers

Tue, 5 May 2006
Tough challenges facing process tool vendors as the industry moves toward sub-45nm chip features will require imaginative solutions. An analysis relating important application trends to process tool requirements was presented by Masayuki Tomoyasu, director of development and planning for Tokyo Electron, Ltd. (TEL), who then proposed a wide range of potential solutions for toolmakers.

ASML: Immersion ramp pushing tool demand in 2Q

Tue, 5 May 2006
May 23, 2006 - ASML Holding NV says it's seeing stronger than anticipated demand for its lithography equipment in 2Q06, as customers place orders for immersion lithography tools used in an anticipated production ramp-up in 4Q06-1Q07.

SMIC adds $600M through bank loans

Thu, 6 Jun 2006
June 8, 2006 - Fresh off a $300M infusion to support expansion at its Tianjin facilities, Chinese flagship foundry Semiconductor Manufacturing International Corp. (SMIC) said its Shanghai subsidiary has closed a five-year, $600 million secured term loan facility with a consortium of international and Chinese banks.

JEOL doubling e-beam tool output

Mon, 6 Jun 2006
June 5, 2006 - JEOL Ltd. reportedly is investing 1.8 billion yen (about US $16 million) to build a new facility that will double its production of electron-beam lithography equipment.

Toshiba, Takumi incorporating DFM for mask data prep

Wed, 5 May 2006
May 31, 2006 - Toshiba Corp.'s semiconductor company is using Takumi Technology Corp.'s automated layout modification methodology for mask data preparation design flow in sub-65nm IC manufacturing, the companies said.

Nantero touts success with 22nm memory switch

Wed, 4 Apr 2006
April 12, 2006 - Nantero Inc. says it has successfully demonstrated scalability of its nonvolatile random access memory (NRAM) technology, with fabrication and testing of a 22nm NRAM memory switch.

NEC tips 55nm CMOS work

Mon, 6 Jun 2006
June 12, 2006 - NEC Electronics America Inc., Santa Clara, CA, says it has developed 55nm standard CMOS process technology (dubbed "UX7LS) to be used with next-generation, ultralow-power consumption systems-on-chips (SoC), as well as the company's CMOS-compatible DRAM technology.

Immersion's evolution launches the age of hyper-NA lithography

Wed, 6 Jun 2006
ArF immersion lithography has started to reveal defectivity and overlay numbers comparable to dry ArF lithography, indicating that the technology is rapidly maturing and will soon be ready for introduction in volume manufacturing.

Brion, Crolles2 partners extend OPC work to 45nm

Tue, 6 Jun 2006
June 6, 2006 - Brion Technologies and Crolles2 Alliance partners STMicroelectronics, Philips Semiconductors, and Freescale Semiconductor, have incorporated Brion's Tachyon LMC lithography manufacturability verification technology into production on a fully automated 65nm process flow, and agreed to continue working to develop optical-proximity correction (OPC) technology for 45nm device fabrication.

Test methods, safety, CD photomask spec on SEMI standards list

Mon, 6 Jun 2006
June 5, 2006 - SEMI has published eight new technical standards for the semiconductor, flat-panel display (FPD), and MEMS manufacturing industries, including safety guidelines for hydrogen peroxide storage and handling systems, specifications for critical dimension (CD) measurement information data for photomask manufacturing, and test methods for measurement of the resistivity of resin black matrix for LCD color filters.

IR, Silicon Saxony join fab owners' group

Mon, 11 Nov 2006
November 13, 2006 - The Fab Owners Association (FOA), a collection of an association of mainly second-tier semiconductor manufacturers, has expanded its roster with the addition of power technology developer International Rectifier, and Silicon Saxony, a network of technology companies for the Saxony, Germany, region.

DFM startup decloaks with tools, customers, design flow

Mon, 11 Nov 2006
November 27, 2006 - After three years of behind-the-curtain development and joint work with several customers and foundries, Clear Shape Technologies Inc. has officially launched with an announcement of two flagship products, and a DFM-aware IC design flow resulting from a collaboration with Taiwan foundry United Microelectronics Corp. (UMC).

Tower adds 0.18-micron LDMOS process

Mon, 11 Nov 2006
November 6, 2006 - Israeli pure-play foundry Tower Semiconductor Ltd. has made available a new laterally diffused metal oxide semiconductor process (LDMOS) on its 0.18-micron platform, produced in its Fab 2 facility, targeting use in LCD drivers for cell phones and other handheld displays.

November 2006 Asian Exclusive Feature 2:

Japan: Addressing the challenges of next-generation litho track systems

Thu, 11 Nov 2006
Helen Armer, Sokudo Co. Ltd., Kyoto, Japan

Dainippon Screen Mfg. Co. Ltd. and Applied Materials Inc. formed the Sokudo semiconductor coat/develop track joint venture in July 2006 to develop new track technologies that will enable users to meet the challenges of next-generation lithography processing. Sokudo's goal is to offer users competitive and technically differentiated track products that can help keep the semiconductor industry on its roadmap to smaller linewidths.

Nova tips 8% worker layoffs in biz balancing act

Tue, 11 Nov 2006
November 21, 2006 - Days after a business unit reorg and executive shuffle, Nova Measuring Instruments Ltd. has announced layoffs of about 8% of its workforce in all parts of the organization, but mainly in R&D and operations and including management positions. The company will take a $300K charge in 4Q06 to cover termination expenses and other costs, but foresees saving $2 million in 2007.

Photronics shutting "unproductive" TX mask shop

Fri, 3 Mar 2006
March 31, 2006 - In an effort to streamline its "unproductive" photomask manufacturing infrastructure in North America, Photronics Inc., Brookfield, CT, said it will close its manufacturing facility in Austin, TX, taking a $15-$18 million charge in fiscal 2006 and laying off 6% of its workforce.

February 2006 Exclusive Feature: LITHOGRAPHY

Imaging of lines and contact holes using ArF immersion at 0.85NA

Wed, 2 Feb 2006
By Vincent Wiaux, Eric Hendrickx, Geert Vandenberghe, IMEC, Leuven, Belgium

193nm immersion lithography has become the industry's prime choice for printing critical layers in 45nm node processes. In a research facility, through-pitch imaging solutions for 65nm lines and 80nm contact holes were explored using a preproduction 193nm immersion scanner with a numerical aperture (NA) of 0.85.

M&A deals shuffle 2005 subsystems supplier ranks

Fri, 4 Apr 2006
April 21, 2006 - A late-year ramp in demand was not enough to prevent lower 2005 sales for suppliers of critical subsystems for the semiconductor, flat-panel display, and data storage manufacturing industries, according to data from VLSI Research Inc.

Cymer profits, sales soar

Thu, 4 Apr 2006
April 20, 2006 - Cymer Inc., San Diego, CA, posted a profit of $20.6 million in 1Q06, a whopping 283% increase over a year ago, on 50% higher sales of $127.1 million.

E-beam litho firm adds NA presence

Fri, 4 Apr 2006
April 7, 2006 - Elionix Co. Ltd., a Japanese manufacturer of electron-beam lithography equipment, has signed a deal with SEMTech Solutions to sell its sub-10nm 3-beam systems in the North American market.

Mentor Graphics debuts OPC tool

Tue, 1 Jan 2006
January 10, 2006 - Mentor Graphics Corp., Wilsonville, OR, has unveiled a new product to help verify post-optical-proximity correction (OPC) output, and help chipmakers minimize costly mask respins and delays getting products through production.

ACT's Tobey receives SEMI's Bob Graham award

Tue, 1 Jan 2006
January 10, 2006 - Aubrey "Bill" Tobey, president of ACT International, has been presented with the seventh annual Bob Graham award for "outstanding contributions in semiconductor equipment and materials marketing" by SEMI.

Photronics eyes Korea site for sub-65nm maskmaking

Tue, 1 Jan 2006
January 10, 2006 - Photronics Inc., Brookfield, CT, plans to build a new photomask fabrication facility in South Korea, to support R&D and volume production of photomask technologies for semiconductors using 65nm- and below process technologies.

ASML prints 42nm lines with immersion

Thu, 2 Feb 2006
February 23, 2006 - ASML Holding NV says it has produced images down to 42nm, at 84nm pitch and a 1-micron depth-of-focus in a 26 x 33 sq. mm field, on its Twinscan XT:1700i immersion lithography system (NA=1.2), noting a 30% improvement in resolution in dry tools.

KLA-Tencor tool analyzes CD metrology data

Wed, 2 Feb 2006
February 22, 2006 - KLA-Tencor has added a new feature spanning its lineup of overlay, CD SEM, and optical CD metrology tools to provide automated real-time analysis of overlay and critical dimension (CD) metrology data during 65nm and below IC manufacturing processes.

TSMC: Immersion yields, defect rates are ramp-ready

Wed, 2 Feb 2006
February 22, 2006 - Top foundry Taiwan Semiconductor Manufacturing Co. (TSMC) says it's achieved near-zero defect rates with test wafers using immersion lithography, comparable to dry lithography results and well within acceptable parameters for volume manufacturing.

KLA-Tencor spotlights Cymer source for litho tool

Wed, 2 Feb 2006
February 22, 2006 - Extending joint work on simulating laser bandwidth on critical dimensions (CD), KLA-Tencor Inc. will add Cymer Inc.'s light source spectra into its Prolith lithography optimization tool, to enable users to model the effects of changes in light source spectral characteristics on their advanced lithography processes.

Nanozone progress means focus and tough choices

Tue, 1 Jan 2006
By Bob Haavind, Group Editorial Director

While exotic properties of materials in the nanozone (1-100nm) promise a host of new devices and applications, success in the marketplace will depend on making tough choices and focusing on developing products offering sustainable profits.

IBM snaps up Inficon's process-control software IBM snaps up Inficon's process-control software

Fri, 1 Jan 2006
January 27, 2006 - In a move to bolster its lineup of factory process-control options, IBM Corp. has acquired the Argus line of lithography advanced process control software and related IP from Inficon.

ASMI clamping down on deposition, ALD development

Fri, 1 Jan 2006
January 27, 2006 - In an move to return to profitability for all of its frontend segments, ASM International NV, Bilthoven, The Netherlands, said that it will scale back its NuTool operation to license the technology, and consolidate its wafer-handling platforms.

EUV firm gets boost with Intel funding

Fri, 1 Jan 2006
January 27, 2006 - Xtreme Technologies GmbH, a joint venture between Jenoptik AG and Ushio Inc. developing light sources for extreme-ultraviolet (EUV) photolithography, has received an undisclosed amount of funding from Intel Corp.'s investment arm to accelerate development and commercialization of the technology.

Intel, DNP extend mask pact to 32nm

Mon, 1 Jan 2006
January 23, 2006 - Intel Corp. and Dai Nippon Printing Co. Ltd. have extended a mask development collaboration to cover mask technologies, including optical lithography (ArF excimer laser) and extreme ultraviolet (EUV), for the 32nm node and beyond.

Sematech tightens belt to fight "onerous" infrastructure investments

Thu, 1 Jan 2006
January 19, 2006 - In a move to reduce expenses and tighten focus on its technical programs, Sematech is eliminating about 15% of its cost structure, restructuring various support and administrative functions and reshaping its interconnect program.

IBM, JSR: Immersion can extend past 32nm node

Tue, 2 Feb 2006
February 21, 2006 - IBM Corp., along with Tokyo-based JSR Corp. and its US subsidiary JSR Micro Inc., say they have demonstrated sub-30nm patterning using deep-ultraviolet (DUV) 193nm optical lithography, indicating that immersion lithography can be extended to and beyond the 32nm node.

Mentor preps mask data tool for 45nm node

Fri, 2 Feb 2006
February 17, 2006 - Mentor Graphics Corp., Wilsonville, OR, said its new Calibre MDP mask data preparation tool suite has been qualified for production at IDMs for 45nm process technology in flows based on the OASIS stream format.

Nikon first out of gates with production immersion tool

Fri, 2 Feb 2006
Nikon Corp. says it has shipped the world's first production immersion lithography system to a memory chip manufacturer using 55nm process technologies, and for R&D on 45nm devices.

Notre Dame eyes magnetic logic

Thu, 2 Feb 2006
February 16, 2006 - Researchers at the U. of Notre Dame have developed a prototype demonstrating a chip design approach that utilizes tiny magnets for logic functions instead of electrical transistors.

KLA upgrades Starlight photomask inspection tool

Wed, 2 Feb 2006
February 15, 2006 - KLA-Tencor Corp., San Jose, CA, has introduced an upgrade to its Starlight photomask inspection system, offering contamination inspection for all types of photomasks, including mainstream extreme resolution enhancement technique (XRET) photomasks, at the 65-nm node and below.

SEMATECH touts zero-defect milestone for EUV mask blanks

Wed, 2 Feb 2006
February 15, 2006 - Researchers at SEMATECH North in Albany, NY, claim to have achieved total removal of particles as small as 43nm from quartz substrates, nearly the 40nm benchmark necessary required for pilot lines using extreme ultraviolet (EUV) lithography techniques.

New SEMI tech standards address compound semis

Tue, 2 Feb 2006
February 14, 2006 - SEMI has published 14 new technical standards as part of its 3x/year schedule. The group includes several applicable to the emerging growth area of compound semiconductors.

RIT touts litho "breakthrough" with EWL

Thu, 2 Feb 2006
February 9, 2006 - Researchers at the Rochester Institute of Technology have developed a new lithography method that they claim achieves results comparable with extreme-ultraviolet (EUV) lithography, and five years before requirements by the International Roadmap for Semiconductors.

Startup Invarium debuts 65-45nm IC layout tool

Wed, 2 Feb 2006
February 8, 2006 - Invarium Inc., San Jose, CA, has introduced a new product that it claims is superior to current RET and OPC tools for patterning IC layouts of 65nm- and below chipmaking processes, with an eye toward 32nm and EUV lithography.

Infineon touts first outsourced 65nm chips

Wed, 2 Feb 2006
February 1, 2006 - In the first achievement under its new "fab lite" business model, Infineon Technologies AG has produced sample 65nm chips, leveraging technologies developed under an alliance with IBM, Chartered, and Samsung.

SEMICON Japan: Suppliers tout immersion and EUV progress

Wed, 2 Feb 2006
By Masataka Tsubo, WaferNews Contributing Editor, Japan

With 65nm production ramping, the focus at SEMICON Japan in December turned to cutting-edge technology for 45nm production and 32nm development, leaving lithography suppliers in the unenviable position of midwifing two new exposure technologies into production at once.

Alliance trio lines up DFM support for 65nm process

Thu, 3 Mar 2006
March 30, 2006 - Chartered Semiconductor Manufacturing Ltd., IBM Corp., and Samsung Electronics Co. Ltd. have announced availability of design-for-manufacturing (DFM) technology, models, design kits, and data files for their common 65nm process technology platform.

ISS 2007 REPORT: The 450mm debate rages on

Tue, 2 Feb 2007
Just when the debate over transitioning to a new, 450mm wafer size was thought to be on ice for the foreseeable future, pronouncements at the recent SEMI Industry Strategy Symposium (ISS) in Half Moon Bay, CA, indicate that the controversy is as contentious as ever among four polarized groups. "We're about as divisive as a theological unification meeting," quipped VLSI Research CEO Dan Hutcheson.

Hitting up computational lithography with a 4x4

Mon, 2 Feb 2007
Brion Technologies is unveiling its second-generation system, Tachyon 2.0, at this week's SPIE Advanced Lithography Conference (Feb. 26, San Jose, CA). Still using Xilinx FPGAs (current generation) to achieve hardware acceleration, the company claims that a single Tachyon 2.0 system rack can replace the production capacity of four of the first generation racks.

DFM SERIES PART I: Clear Shape takes a stab at changing the shape of the DFM turf

Tue, 2 Feb 2007
The proliferation of DFM start-ups has set the stage for a plethora of announcements in the months leading up to the SPIE Microlithography Conference. In this three-part series, WaferNEWS interviews companies that are trying to make their mark on the DFM landscape. This week we look at a company with technology that predicts, during the design phase, how ideal GDS shapes will print as contours in silicon: Clear Shape Technologies.

Nikon touts shipment of 45nm immersion tool

Wed, 2 Feb 2007
February 28, 2007 - Nikon Corp. says it has shipped its newest ArF immersion lithography scanner, the NSR-S610C, to an unnamed IC manufacturer for 45nm production work and 32nm development. The selection came after a "one-year, head-to-head evaluation," according to Kazuo Ushida, president of Nikon Precision Equipment Co.

Luminescent touts 45-32nm benefits of "ILT"

Tue, 2 Feb 2007
February 27, 2007 - At this week's SPIE Advanced Lithography Symposium, Luminescent Technologies claims to have data showing customers using its inverse lithography technology (ILT) in 45nm and 32nm development efforts. The company is touting ILT as an alternative to optical proximity correction (OPC), offering better pattern fidelity and broader lithography process windows.

Nikon, CEA-Leti partner for 32nm double patterning/exposure

Tue, 2 Feb 2007
February 27, 2007 - Nikon Corp. and European R&D microelectronics research center CEA-Leti say they have formed a joint development program to develop optical lithography technologies at the 32nm node, including double exposure and double patterning. Work will be performed at CEA-Leti's Nanotec 300 research facility, utilizing a Nikon scanner.

DNP, Takumi team for photomask inspection system

Mon, 2 Feb 2007
February 26, 2007 - Dai Nippon Printing Co. Ltd. (DNP) and Takumi Technology Corp. say they are developing an automated criticality-aware photomask inspection system to help reduce manufacturing cost and turnaround times of advanced photomasks. The product, currently in beta phase with an unnamed semiconductor manufacturer, is expected to be ready by March 2008 for worldwide deployment to DNP's customers as a service, at no extra cost.

KLA-Tencor tips new litho optimizer

Fri, 2 Feb 2007
February 23, 2007 - KLA-Tencor says the new version of its PROLITH litho optimization product, PROLITH 10, enables users to accurately predict lithography process windows for integrated circuit (IC) designs down to 32nm.

Solving a sticky problem in refractory organics

Mon, 4 Apr 2007
The advent of 193nm (ArF) lithography brought a different kind of issue: contaminated scanner optics caused by the formation of silicon-containing organic compounds which form larger molecules that condense on the optics and cause lens contamination, resulting in flare and incorrect printing. A new absorbent material used in Entegris' filter keeps a "sticky" organic in its condensable form, preventing it from rearranging and propagating through the filter and ultimately reaching the optics.

SEMATECH, Veeco push EUV tool efforts

Mon, 4 Apr 2007
April 23, 2007 - SEMATECH is funding an additional $2.4 million project to support Veeco Instruments Inc.'s R&D of its ion beam deposition tool for use in extreme ultraviolet (EUV) lithography, part of SEMATECH's Mask Blank Development Center at the U. of Albany campus in New York.

Sematech touts "milestone" in EUV mask blank defect cleaning

Tue, 4 Apr 2007
April 17, 2007 - Sematech says its researchers at its Mask Blank Development Center (MBDC) at the U. of Albany (NY)'s College of Nanoscale Science and Engineering, have successfully detected and cleaned 10nm particles from mask blanks used in EUV lithography.

Cypress licenses 0.13-micron SONOS NVM to Hua Hong

Tue, 4 Apr 2007
April 17, 2007 - Cypress Semiconductor Corp. has licensed its 0.13-micron SONOS embedded nonvolatile memory technology to China's Hua Hong NEC Electronics Co. Ltd. Hua Hong already makes embedded EEPROM and OTP (0.35-micron) as well as embedded flash (0.25-micron) at mass production levels.

Vistec, Japan's TOOL combine tools for faster layout recipes

Fri, 4 Apr 2007
April 13, 2007 - Vistec Semiconductor Systems GmbH and TOOL Corp. say they have integrated Vistec's LWM9000 SEM-based CD measurement system with TOOL's Lavis layout visualization platform, making it possible to more quickly display measuring layout design data and visually create recipes.

ISS EUROPE REPORT: Russia chasing ITRS goals, AMD's process efficiencies paying off

Tue, 2 Feb 2007
Among presentations at SEMI Europe's Industry Strategy Symposium (ISS) in Z

SPIE keynotes dismiss EUV

Tue, 2 Feb 2007
The organizing committee of SPIE Advanced Lithography Symposium -- the conference formerly known as "Microlithography" -- probably didn't plan for the Monday (Feb. 26) keynote addresses to dismiss EUV lithography, but that's exactly what happened. Prior to three days of detailed EUV presentations, executives presented perspectives that do not include place for this next-generation lithography technology any time in the near future.

Merging Blaze, Aprio claim eDFM crown

Mon, 2 Feb 2007
The announced merger of Blaze DFM and Aprio Technologies establishes an entity ready to claim the mantle of tops in "electrical DFM (eDFM)," in a highly fragmented DFM market with many companies positioning for leadership, according to execs announcing the deal. "We believe that there is room for one eDFM company that stands by itself...and we are going to be that company," stated Jacob Jacobsson, currently president/CEO of Blaze DFM.

Macronix prepping 45nm NAND amid "swarming" demand

Fri, 2 Feb 2007
February 2, 2007 - Macronix International Co. Ltd. enjoyed five-year highs in profit margins and earnings last year due in large part to "swarming" orders from Nintendo for Mask ROM chips and improved costs for flash-memory production, and another boost in 2H07 will require significant additional capacity investments, according to the Taiwan Economic News.

Blaze, Aprio tie up in DFM merger

Wed, 2 Feb 2007
February 21, 2007 - Staking their claim to the mantle of tops in "electrical DFM," Blaze DFM and Aprio Technologies have announced a merger that they say will create "the industry's only comprehensive electrical DFM solution."

Nikon set to enter photomask glass market

Thu, 2 Feb 2007
February 8, 2007 - Japan's Nikon Corp. has invested about 2.3 billion yen (US $19 million) to start producing glass substrates for liquid-crystal display (LCD) photomasks, according to a Reuters report.

Imprint litho firm secures more funding

Wed, 4 Apr 2007
April 4, 2007 - Molecular Imprints Inc. says it has secured $8.5 million in venture debt financing from BlueCrest Capital Finance LP, an investment that will support continued development and commercialization of the company's step-and-flash imprint lithography technology.

"Two-photon absorption" technique shows promise for 3D microstructures

Mon, 4 Apr 2007
Georgia Tech researchers say they've developed a "3D multiphoton" technique, a process involving two-photon absorbing molecules that are sensitive to laser light at short wavelengths, that could be applied to simplify and cut costs for patterning 65nm devices.

TSMC prepping 45nm ramp

Mon, 4 Apr 2007
April 9, 2007 - TSMC says it will complete 45nm qualification and enter production as early as September, ahead of initial 4Q07 plans.

Extending the lithography-airplane metaphor

Tue, 4 Apr 2007
Popular aviation metaphors used to describe the evolution of lithography in the semiconductor manufacturing industry invoke propeller planes (i.e. 1:1 masks), jet aircraft (reduction steppers), and even the next-generation lithography equivalents of pricey supersonic planes like the Concorde. Here's what I think is a more accurate metaphor for lithography's evolution, explaining why we use planes, jets, and even helicopters for different applications -- and why 157nm litho tools "never flew."

Lone US mask blank maker closing shop

Wed, 4 Apr 2007
April 25, 2007 - Schott Lithotec, the last-standing US supplier of photomask plates, is ceasing production and will sell its Poughkeepsie, NY facility, finally deciding that lower ASPs and a shift of customers to Asia means it's no longer a viable business to be in.

Brion, Japan's TOOL pledge IC litho integration

Thu, 1 Jan 2007
January 18, 2007 - Brion Technologies Inc. and Japan's TOOL Corp. have agred to combine TOOL's LAVIS layout visualization platform with Brion's Tachyon OPC and RET/OPC verification system, in a bid to help users more easily obtain litho simulation results without difficult and complex data preparation.

ASML quadruples profits in 4Q, sees strong business in 1H07

Wed, 1 Jan 2007
January 17, 2006 - Lithography tool vendor ASML says its profits surged fourfold in 4Q06 from a year ago to about $265 million on record revenues, and expects to continue the good news with " healthy" order levels in 1Q07 and a yearlong ramp-up of 45nm volume manufacturing utilizing immersion lithography.

SEMICON WEST TiS PREVIEW: Quantum modeling software, diamond films, and nanoimprint tools start to go mainstream in semiconductors

Tue, 7 Jul 2007
Despite the fact that it's done much of its manufacturing in nanoscale dimensions for years, the semiconductor industry hasn't yet had much use for the unique nanoscale properties of the nanoparticles, nanowires, quantum dots, etc. usually considered nanotechnology, nor found much use for the nanoscale patterning processes developed by the chipmakers. But that may be starting to change, judging by the crop of emerging technologies selected for SEMICON West's Technology Innovation Showcase.

Entegris rolls out filters, reticle haze add-on

Fri, 7 Jul 2007
July 19, 2007 - Amid a batch of product rollouts this week, Entegris Inc. has unveiled a new line of high-flow liquid filters for sub-45nm contamination control, and an add-on to its 193nm litho reticle haze tool targeting deep-ultraviolet lithography.

Carl Zeiss lens ready in ASML's 1900i immersion litho tools

Fri, 7 Jul 2007
July 19, 2007 - Carl Zeiss SMT says more than 10 of its Starlith 1900i immersion lithography optical lenses have been qualified for integration into ASML's Twinscan XT:1900i wafer scanners, with one tool already shipped to an end user.

AMAT releases oxide spacer system at SEMICON West

Wed, 7 Jul 2007
July 18, 2007 - Applied Materials Inc. today released its Applied Producer ACE SACVD system, which helps extend 193nm lithography using self-aligned double patterning (SADP) schemes. The ACE system reportedly delivers a highly conformal oxide spacer film with greater than 95% step coverage, <5% pattern loading and <1% nonuniformity for critical dimension control.

ASML selects Cymer as EUV source supplier for HVM

Wed, 7 Jul 2007
July 18, 2007 - At SEMICON West 2007, ASML Holding NV (ASML) has selected Cymer Inc. as the extreme ultraviolet (EUV) source supplier for ASML's EUV scanners for high-volume manufacturing (HVM). Cymer disclosed that it has signed a multi-year, multi-unit EUV source agreement with the first shipment scheduled for late 2008.

Carl Zeiss announces new 248nm litho system for 80nm resolution

Wed, 7 Jul 2007
July 18, 2007 - Carl Zeiss SMT AG announced at SEMICON West today its new optical lithography system for KrF, the Starlith 1000, with a numerical aperture (NA) of 0.93, which will reportedly be the highest NA for 248nm exposure wavelength available in the market.

SEMICON WEST REPORT: The transistor is cool again

Thu, 7 Jul 2007
The main topics for discussion at Applied Materials' press event on Tuesday were about high-k/metal gate processes (HK+MG) and double patterning lithography, though much of the talks concentrated on the gate technology -- and how they created the delicately etched iceblocks serving as table centerpieces.

SEMICON WEST PREVIEW: ASML, Cymer, Synopsys headline litho announcements

Mon, 7 Jul 2007
A quick roundup of news and views ahead of SEMICON West finds ASML tipping a KrF version of its Twinscan and announcing a first customer for its "ultimate" XT:1900i immersion tool; Cymer's "socialized medicine" for laser light sources; and Synopsys weaving its tools together to drive next-generation yields.

Takumi showcases automatic repair of litho hot spots

Tue, 7 Jul 2007
As the industry marches from 90nm to 65nm and 45nm, it has become increasingly difficult to achieve fast yield ramp due to random defects, process variations, and other design-for-manufacturing (DFM) issues localized in layout hot spots. Hoping to become the leading company bridging the gap between IC design and manufacturing is Takumi Technology with its automatic layout repair/optimization software.

Making solar cells: This *is* your father's fab

Tue, 7 Jul 2007
What's the difference between semiconductor equipment and solar equipment? "A factor of ten, squared," said T.J. Rodgers, chairman of SunPower Corp. and president and CEO of Cypress Semiconductor, during his Wednesday (July 18) keynote address at SEMICON West. "If you want to sell a solar fab some equipment, it has to be 10x cheaper" -- e.g., $400,000 instead of $4 million -- "and it has to be 10x faster, say, 800 wafers/hr, not 80 wafers/hr."

SEMICON WEST REPORT: Keynotes tap into promises, challenges of solar

Fri, 7 Jul 2007
A pair of Wednesday keynotes at SEMICON West described opportunities for semiconductor suppliers in the solar energy market, but cautioned that there are fundamentally different manufacturing requirements in the two industries.

SEMICON WEST REPORT: DFM panel trains critical eye on yield progress

Tue, 7 Jul 2007
What happens when you put a design software vendor, a chip manufacturer, and a photomask maker all at one table and ask them to talk about yield? Not surprisingly, the software vendor finds himself on the hot seat.

SST July 07: Samsung's NAND Flash evolution

Fri, 7 Jul 2007
EXECUTIVE OVERVIEW This month's edition of Chip Forensics by analyst Dick James delves into Flash technology, including the Samsung K9F2G08U0M 2-Gb single-level cell (SLC) Flash.

SUSS spins off device bonder unit

Fri, 7 Jul 2007
July 27, 2007 - SUSS MicroTec has carved out its device bonder division through a management buyout initiated by SUSS France president Gael Schmidt, in order to gain independence from the parent company which has little strategic synergies.

Vistec combines litho groups

Thu, 7 Jul 2007
July 18, 2007 - Vistec Semiconductor Systems says it will combine its electron beam and lithography business groups in order to "better meet customers' requirements and improve synergy across the organization."

IMEC updates 32nm litho progress

Mon, 7 Jul 2007
July 16, 2007 - At SEMICON West, European R&D consortium IMEC is disclosing it results after a year of 32nm half-pitch work, noting progress in all three of its areas of focus: high-index 193nm immersion litho, double-patterning, and EUV.

Nikon tips ArF, KrF scanners

Wed, 7 Jul 2007
July 11, 2007 - Nikon Precision Inc. has released two new DUV lithography scanners, built on its Tandem Stage platform, to improve productivity and enhance overlay performance.

Litho, materials, manufacturing efficiency top SEMATECH meeting agendas

Mon, 1 Jan 2007
January 29, 2007 - Extreme ultraviolet lithography (EUV) and 193nm immersion lithography will be a primary focus of SEMATECH's 2007 Knowledge Series seminars in the upcoming year, the group said today in a statement. Other areas will include materials to enhance transistor and backend development, and methods to improve manufacturing efficiency and yield.

Analyst: Litho sales top 2000 record

Thu, 1 Jan 2007
January 25, 2007 - The semiconductor lithography market expanded at nearly twice the rate of the rest of the equipment industry in 2006 to top $6.7 billion, finally eclipsing the $6.0 billion mark achieved back in 2000, according to a report from The Information Network.

UMC breaks ground on 300mm Fab 12B

Mon, 1 Jan 2007
January 8, 2007 - UMC says it has begun construction of its 300mm Fab 12B in southern Taiwan's Tainan Science Park, and a R&D center on the site is entering the final stages of construction, on pace to be completed in March.

DNP buying NEC's Fabserve photomask biz

Wed, 1 Jan 2007
January 3, 2007 - In a move that may further juggle the top positions among photomask suppliers, NEC Electronics Corp. has agreed to sell its Fabserve photomask manufacturing subsidiary to Dai Nippon Printing Co. Ltd. for an undisclosed amount.

SEMICON WEST REPORT: Plenty of room for litho, DFM debates

Tue, 7 Jul 2007
Amid many debates over 45nm- and 32nm manufacturing challenges, photolithography wasn't the hottest topic at this year's SEMICON West, possibly because the first 45nm-capable immersion scanners have been shipped and no one seems to know how 32nm might be achieved economically. There were spirited discussions, though, about potentially radical ways to significantly increase throughputs by the time double-patterning is required, and whether DFM is really ready for the burden being asked of it.

Intel touts working 45nm chip with high-k, metal gates

Mon, 1 Jan 2007
January 29, 2007 - Touting "a significant breakthrough in transistor technology," Intel Corp. says it has progressed its 45nm process technology from a SRAM test chip unveiled in Jan. 2006 into a working 45nm transistor -- devices that incorporate a hafnium-based high-k dielectric material and a new combination of metals for the transistor gate electrode. The new "Penryn" transistor will start shipping in volume by year's end on various systems, including those with Microsoft Vista OS.

Intel's 45nm demo shows commitment, confidence

Tue, 1 Jan 2007
After attending a demo at Intel HQ the day before the big announcement, SST Senior Technical Editor Mark Levenson thinks achieving first production as scheduled in 2007 would have been a significant technological milestone by itself -- but getting the first design, first mask set, and first silicon all working properly was stunning.

Controlling line-edge roughness in EUV resist with sturdy, small molecules

Wed, 1 Jan 2007
Tokyo Ohka and Hitachi have demonstrated patterns with 28nm half-pitch resolution, with EUV resist made using small molecules that eliminate much line-edge roughness.

Stanford Magnetic Technology workshop not just about memories

Tue, 1 Jan 2007
A Dec. 8 workshop at Stanford U.'s Center for Magnetic Nanotechnology on the patterning and imaging of magnetic nanostructures offered many looks at the future of data storage, including unique fabrication technology used to make heads with state-of-the art sensors, and the challenges of "bit patterned media." Several interesting presentations also delved into medical and biotech applications of magnetic nanoparticles.

ASML illuminates a dry path to 40nm

Tue, 1 Jan 2007
The ITRS plots a route to 45nm half-pitch through water immersion lithography for critical levels, but ASML is giving its customers an alternative by request -- one that employs familiar dry DUV exposure and the double pattern method being considered for 32nm.

NIST working on single-nanowire positioning system for testing properties

Fri, 5 May 2007
May 4, 2007 - Researchers at the National Institute of Standards and Technology (NIST) say they have created a method for manipulating and positioning individual nanowires on semiconductor wafers, enabling fabrication of test structures using only optical microscopy and conventional photolithographic processing.

IBM adds airgaps for faster chips

Tue, 5 May 2007
Airgap structures have long been considered to increase the speed of on-chip IC interconnects, but it's a long way from proof-of-concept to a working process flow in a fab. In an exclusive interview with WaferNEWS, IBM strips away the hype to explain its new manufacturable variation on airgaps using a self-assembling polymer mask layer -- revealing that airgaps in standard low-k dielectric structures add only ~1% to chip cost for each layer.

Intel promotes computational lithography capabilities

Tue, 6 Jun 2007
Intel typically uses its annual "Research Day" to provide a glimpse into potential commercial applications for the chipmaker's technologies. But this year's event (June 20) also demonstrated the way Intel's technology advances the chipmaker's own electronics manufacturing -- showing how "computational lithography" will be the backbone of Intel's proprietary DFM strategy for the foreseeable future.

More to DFM than meets the ROI

Wed, 5 May 2007
Anyone trying to follow the topic of design for manufacturing (DFM) the last few years would be hard-pressed to accurately dissect the nuanced boundary lines that identify what each company that plays in the DFM space actually does and how users of DFM/EDA should evaluate their return on investment for the tools. ConFab panelist Joe Sawicki, VP & GM at Mentor Graphics, thinks we should look at the "DFM" label in a new way.

Dealing with silicon-package interactions

Wed, 5 May 2007
Chip design, foundry/fab, and packaging partners must work in concert to reduce risk on new technology offerings, according to Mike Barrow, SVP, flip chip technologies, Amkor. Giving the packaging group early access to advanced silicon can result in chip and package interaction (CPI) solutions that are market-ready upon silicon node release. Further, package and laminate design are in the critical path, and need to be co-designed with the silicon to deliver cost-effective solutions.

Trio to collaborate on e-beam tech for sub-10nm devices

Mon, 6 Jun 2007
June 4, 2007 - GenISys GmbH, JEOL Ltd., and Cornell U. are partnering to develop advanced technologies for direct-write e-beam data preparation and electron process correction technologies for nanometer-range structures.

LithoWare brings PROLITH to design

Fri, 6 Jun 2007
PROLITH has long been the most popular tool for optimizing lithography processes before exposure, enabling accurate simulations on small circuit regions with a library of calibrated resist and other material parameters. But running it under Windows on a PC has always seemed too slow to help wavefront engineers optimize entire chip designs. To address this, KLA-Tencor has introduced LithoWare, a new Linux-based product enabling semiconductor circuit designers to run PROLITH on large server farms.

Selete touts 26nm linewidths with small-field EUV

Fri, 6 Jun 2007
June 1, 2007 - Japan's government-affiliated New Energy and Industrial Technology Development Organization (NEDO) says it has drawn circuit patterns with just 26nm linewidths (isolated and dense lines), which would vault Japan back among the frontrunners for achieving chip manufacturing at the 32nm node using EUV, according to local news reports.

Analyst: 193nm requirements driving resists market

Wed, 5 May 2007
May 16, 2007 - Extending 193nm lithography through the 45nm and 32nm nodes while EUV litho struggles to gain traction will require performance improvements such as multilayer patterning and multiple exposure schemes, driving more use of spin-on patterning materials (aka resists), according to a report from Linx Consulting. Analyst Mark Thirsk reviews his firm's outlook for the resist market, indicating which areas will see the most growth and where are the best chances for market opportunities.

SEMATECH shifting HQ to Albany

Thu, 5 May 2007
May 10, 1007 - International SEMATECH is moving its headquarters from Austin, TX, to its operations located at the U. of Albany, and will launch a significant expansion there, matching $300 million in state investments for facility upgrades.

Survey: HK+MG, 193nm immersion likely by 2010; EUV, 450mm on the outs

Thu, 6 Jun 2007
June 21, 2007 - A new study by Wright Williams & Kelly Inc. and Strategic Marketing Associates sheds light on what people in the industry think will be most likely to hit production process lines in the next 2-5 years, and which ones may take longer than expected to be adopted into manufacturing lines, if ever.

Luminescent adds $9M financing, swaps CEO

Thu, 6 Jun 2007
June 14, 2007 - Luminescent Technologies Inc. says it has raised $9 million in a new round of financing, led by new investor Adams Capital Management along with existing investor Sevin Rosen Funds. The funds will be used to continue driving adoption of the company's inverse lithography technology (ILT), which it is touting as an alternative to optical proximity correction (OPC), offering better pattern fidelity and broader lithography process windows.

Report: Image sensor market nearing $7B

Tue, 6 Jun 2007
June 12, 2007 - The image sensor market is projected to grow 14% in 2007, following 30% growth in 2006 to roughly $6 billion, and will slow through the next several years, with many providers jostling for position, according to a report from Strategies Unlimited.

Mentor buys place-and-route firm Sierra Design

Mon, 6 Jun 2007
June 11, 2007 - Mentor Graphics has acquired Sierra Design Automation for $90 million in a half-and-half cash/stock deal, bolstering its design offerings. Mentor says the deal will be "slightly accretive" for FY07 (ending Jan.31 2008), and shave about $0.02 off of its anticipated FY08 earnings.

Matsushita touts 45nm production of AV LSIs

Tue, 6 Jun 2007
June 19, 2007 - Matsushita Electric Industrial Co. says it has begun the "world['s] first" mass production of 45nm LSI chips at its factory in Uozu, central Japan, using ArF immersion lithography (NA>1) with "proprietary super-resolution enhancement technology" and multilayer wiring using low-k dielectrics.

Silterra, IMEC extend pact to 90nm

Thu, 6 Jun 2007
June 14, 2007 - Silterra Malaysia says it has signed a "joint development project" with European R&D consortium IMEC to create a foundry-compatible 90nm CMOS process technology, based on IMEC's process, with intention to scale to 65nm (while developing a 110nm derivative in parallel). The two already had worked on 0.13-micron process technology under a deal signed in June 2004.

IMEC discloses finFET progress, but 32nm introduction still hazy

Thu, 6 Jun 2007
June 13, 2007 - Providing updates on work performed with its 32nm CMOS research partners at this week's VLSI Symposium, IMEC says it has improved its process to yield "reproducible" finFETs with fin widths down to 5nm, and high aspect ratios, using 193nm immersion lithography and dry etching. However, "several bottlenecks have to be overcome" before the finFETs can be viable in manufacturing.

ST tips low-power 45nm SoC results

Thu, 6 Jun 2007
June 13, 2007 - STMicroelectronics says it has taped out the design for a low-power system-on-chip (SoC) "demonstrator" device with a multiple threshold transistors, dual-core CPU and associated memory hierarchy. The process improves speed by 20% vs. 65nm designs or reduces leakage current by half when in operation (and by "several orders of magnitude" when in retention mode), and takes up half the silicon area.

NIST using nanowires to make UV LEDs

Tue, 5 May 2007
May 29, 2007 - Researchers from the National Institute of Standards and Technology (NIST), with help from the U. of Maryland and Howard U., have devised a fabrication method that creates tiny ultraviolet light-emitting diodes from nanowires, and NIST says the technique is "well-suited" for scaling to commercial production.

Hynix joins IMEC group as 32nm CMOS R&D partner

Fri, 5 May 2007
May 24, 2007 - Korean memory chipmaker Hynix Semiconductor Inc. has joined IMEC's 32nm memory R&D program, which now boasts participation from the top five global memory chipmakers (Samsung, Elpida, Micron, and Qimonda).

Common Platform partners officially extend to 32nm

Thu, 5 May 2007
May 23, 2006 - Five of the "Common Platform Alliance" partners -- IBM, Chartered, Samsung, Infineon, and Freescale -- say they will extend their current technology development agreements through 2010 and beyond, incorporating 32nm bulk CMOS process technologies and joint development of process design kits.

SEMATECH: LPP gaining favor as EUV source

Mon, 5 May 2007
May 21, 2007 - Laser-produced plasma sources, once seen as a "dark horse" technology for extreme-ultraviolet (EUV) lithography, seem to be gaining steam as the most promising power source for the future litho equipment, according to SEMATECH, citing feedback from a recent workshop.

Analysis: Cadence+Invarium deal seems a "win-win"

Mon, 7 Jul 2007
On the surface, the latest DFM-industry consolidation appears to be a win-win for both Cadence Design Systems Inc. and Invarium Inc., though interviews with WaferNEWS suggest much work still has to be done to figure out the exact combination and roadmap going forward.

Cadence snaps up Invarium, cites pattern synthesis benefits

Thu, 7 Jul 2007
July 12, 2007 - In the latest sign of consolidation in the DFM universe, Cadence Design Systems Inc. has acquired Invarium Inc., a developer of lithography modeling and pattern-synthesis technology, creating what the firms say is combined DFM solution that can enable, prevent, detect, correct, and optimizate manufacturing effects on advanced geometry designs.

Analyst: Intel pushing out more chip orders

Fri, 6 Jun 2007
June 8, 2007 - Intel Corp. appears to be pushing out all orders and shipments for equipment relating to the upgrade of its fab in New Mexico from 200mm to 300mm-compatible, just three months after announcing it would make that facility into its fourth 45nm production site, according to an analyst report.

Analyst: Photomask market rebounding in 2007

Thu, 6 Jun 2007
June 7, 2007 - The market for lithography photomasks continued to slow in 2006, reaching $2.2 billion (5.4% growth), but should pick up again in 2007 thanks to increased demand from the logic segment which uses more and higher-priced masks, according to a report from The Information Market.

Modeling becomes key to advanced lithography

Tue, 3 Mar 2007
The prominence of a dedicated joint session and a panel discussion on "computational lithography" at this year's SPIE Advanced Lithography Symposium -- not to mention ASML's recent $270M purchase of Brion Technologies -- illustrate the growing importance of resolution enhancement tricks that have made it possible to approach the 45nm node using an exposure wavelength four times larger. Making sure that those tricks actually work before fabricating complex masks has become crucial.

TI, Ramtron join forces on FRAM technology in 130nm process

Mon, 3 Mar 2007
March 12, 2007 - Texas Instruments and Ramtron International Corp. have entered into a commercial manufacturing agreement for ferroelectric random access memory (FRAM) products. The agreement provides for the production of Ramtron's FRAM memory products on TI's advanced 130nm FRAM manufacturing process, including Ramtron's 4Mb FRAM memory.

Photronics cuts outlook on FPD, photomask slowdowns

Wed, 8 Aug 2007
August 1, 2007 - Photronics Inc. says 3Q07 sales will be 6%-14% below previous projections to a range of $101-$103 million, due to a shortfall in photomask orders from FPD and European semiconductor customers.

Report from SPIE: Optics lives, but for how long?

Mon, 3 Mar 2007
By Griff Resor, Resor Associates

Each year, experts gather at the SPIE Advanced Lithography Symposium in San Jose to report on their pursuit of Moore's Law. Every two years, a new node in the ITRS is reached, and 2007 is the year for 45nm technology production. Many presentations at SPIE showed the 45nm node in production, as scheduled, using 193 immersion lithography, while other presentations looked further ahead...

SPIE 2007
Burn Lin's wish list for optical lithography: Eliminate the mask

Mon, 3 Mar 2007
by Griff Resor, Resor Associates

March 13, 2007 - Kicking off the 20th annual Conference on Optical Microlithography last week during SPIE, TSMC's lithography guru Burn Lin wove a tale that began as a history lesson, but shifted to a modern message tackling today's top lithography challenges. The common thread throughout: "The devil is in the mask."

REPORT FROM SPIE: Double double, toil and trouble!

Tue, 3 Mar 2007
Progress in water immersion exposure technology since last year's SPIE Advanced Lithography Symposium has been so convincing that its insertion into manufacturing at the 55nm and 45nm generations (as reported by Toshiba, STMicro, and others) is not likely to be interrupted. However, the consensus today is that some evolutionary step has to be taken to extend immersion technology and keep up with Moore's law -- and double patterning technology seems to be the step that will take us to 32nm.

Equipment galore at SPIE 2007

Mon, 3 Mar 2007
by M. David Levenson, Editor-in-Chief, Microlithography World

The traditional Exposure Systems and Components session on the last day of the SPIE Advanced Lithography Symposium gave vendors the opportunity to tout their latest hyper-NA immersion scanners and supporting technologies.

TECH TALK
Topcoat trends at SPIE 2007

Mon, 3 Mar 2007
by M. David Levenson, Editor-in-Chief, Microlithography World

First-generation resist systems for immersion lithography employed a topcoat material to protect the resist and prevent leaching of resist components that might damage the optics. By making the topcoat surface hydrophobic and controllable, topcoat materials suppressed defects and facilitated rapid wafer scan.

NanoIdent opens first fab for printed semiconductor-based optoelectronic sensors

Tue, 3 Mar 2007
March 13, 2007 - NanoIdent Technologies AG, which prints semiconductor-based optoelectronic sensors, has reportedly opened the world's first manufacturing facility for the delivery of printed semiconductor-based optoelectronics.

Blaze DFM closes $10M Series B funding

Tue, 3 Mar 2007
March 13, 2007 - Blaze DFM, an electrical design for manufacturing (DFM) company, has closed its Series B round of funding for $10 million.

August 2007 Exclusive Feature #2
VLSI SYMPOSIUM REPORT: Chipmakers, consortia reveal HK+MG integration

Mon, 8 Aug 2007
By John Borland, contributing editor, Solid State Technology

The VLSI Symposium meeting this year (June 12–14, Kyoto, Japan) revealed there will be not one, but many different solutions for the production implementation of hafnium-based oxides at the 45nm node and beyond, with Hf-based dielectric k values varying from a "medium"-k (8–12) up to a true high k of 22–24. The gate electrode for some companies will remain poly ...

Joint MLW/SST April 2007 Exclusive Feature:
Contact hole lithography for 65nm logic

Tue, 3 Mar 2007
By Yuji Setta, Tatsuo Chijimatsu, Satoru Asai, Fujitsu Ltd., Tokyo, Japan

Arrays of 100nm contact holes can be printed with adequate depth of focus (DOF) through pitch using dry 193nm wavelength exposure and a special illuminator design.

Contact holes are among the most difficult IC structures to pattern. The design rule for nested holes patterns at the 65nm-node generation assumes a spacing almost the same as the wavelength used in ArF lithography.

Integration extends 193nm litho

Tue, 3 Mar 2007
As thoroughly reported by WaferNEWS, SST, and Microlithography World, the 2007 SPIE lithography meeting detailed that 193nm wavelength lithographic reduction steppers may be the last mainstream lithographic technology for the semiconductor manufacturing industry. We must now look for ways to create ever smaller device features using 193nm litho with clever combinations of other known unit-process steps: thin-film depositions, etches, and plasma surface treatments.

DFM double-take: Cadence snaps up Clear Shape

Thu, 8 Aug 2007
August 16, 2007 - Just weeks after acquiring lithography modeling and pattern-synthesis developer Invarium, Cadence Design Systems is making another splash across the DFM and litho marketspace with its purchase of Clear Shape Technologies. Terms of the deal, which closed Aug. 15, were not disclosed.

ASML completes acquisition of Brion Technologies

Thu, 3 Mar 2007
March 8, 2007 - Litho systems supplier ASML Holding NV (ASML) today announced that it has completed its acquisition of Brion Technologies Inc., a provider of semiconductor design and wafer-manufacturing optimization products for advanced lithography.

Nova solicits $5M from investors

Fri, 3 Mar 2007
March 2, 2007 - Israel metrology equipment provider Nova Measuring Instruments Ltd. says it has agreed to a $5 million private placement of nearly 2 million shares by a group of several investors.

Cadence, ClearShape execs hint at future DFM integration

Tue, 8 Aug 2007
August 21, 2007 - Execs from Cadence Design Systems and Clear Shape Technologies talked about their proposed M&A deal with WaferNEWS and Microlithography World, hinting that integration will soon go deeper than just an interface, and what other applications besides litho are in the pipeline.

ACS preview: Research reveals work on nanoimprint, porous low-k, PV

Tue, 8 Aug 2007
Among the literally hundreds of presentations lined up for this week's American Chemical Society fall national meeting (Boston, MA, Aug. 19-23) are talks about chemical advancements in nearly every field imaginable, from medicine to petroleum and agriculture, and materials science. Here's a quick rundown of several papers of interest to the semiconductor industry, including research into nanoimprint lithography, porous low-k dielectrics, and photovoltaic cells.

SST ON THE SCENE @ SEMICON WEST: The consortia balancing act; Dishing on the rest of the transistor

Tue, 8 Aug 2007
IMEC's VP of Business Development, Ludo Deferm, takes SST On the Scene down the path from 45nm to 22nm, and points out the tough questions that loom, such as single-node lithography options and introduction of new architectures such as finFETs. Meanwhile, Larry Larson, frontend associate director at SEMATECH, explains whether Schottky contacts could be a solution to the need for lower resistivity contacts.

Nova gains license deal from patent auction

Wed, 8 Aug 2007
August 8, 2007 - Nearly a year after putting some of its lithography metrology patents up for auction, Nova Measuring Instruments says it has signed a >$1 million deal with an unnamed "top-10 semiconductor manufacturer" for a license covering use of its technologies for integrated metrology and integrated process control before and during the photolithography manufacturing step.

Qualcomm tapes out 45nm design

Thu, 8 Aug 2007
August 2, 2007 - Qualcomm Inc. says it has taped out a chip fabricated on a low power-optimized 45nm CMOS process technology, using "very low-k" intermetal dielectrics and immersion lithography, and says it has started development work on a 40nm process.

STARC taps Blaze DFM for CEL reference design flow

Thu, 8 Aug 2007
August 2, 2007 - The Semiconductor Technology Academic Research Center (STARC), which works with all of Japan's major chipmakers, will use Blaze DFM for lithography simulation and analysis in its STARCAD "certified engineering linkage" (described as "one step ahead of DFM") reference design flow, the companies announced.

OAI adds NIL module for mask aligners

Wed, 8 Aug 2007
August 1, 2007 - Optical Associates Inc. (OAI) says it has added a nanoimprint lithography module as an option to its mask aligners, technology provided by HP spinoff Nanoimprintsolution Inc.

Toppan joins CEA-Leti's double patterning program

Tue, 9 Sep 2007
September 18, 2007 - Toppan Photomasks Inc. has joined a consortium led by European research lab CEA-Leti to jointly develop double patterning techniques, seen as a way to extend 193nm lithography to the 32nm and offer an eventual bridge to EUV whenever it enters semiconductor manufacturing (likely after 2013).

Synopsys, Nikon: Software + scanner data = "manufacturing-aware" DFM

Tue, 9 Sep 2007
September 18, 2007 - Nikon Corp. and Synopsys Inc. have delivered what they say is a "manufacturing-aware" system for 45nm and below chipmaking by combining info gleaned from Nikon scanners with Synopsys' Proteus software, to develop sub-45nm litho models.

Firm touts "breakthrough" for 32nm maskless litho

Sat, 9 Sep 2007
September 14, 2007 - Dutch firm Mapper Lithography says it has achieved "massively parallel electron beam writing" with its newest maskless litho technology, demonstrating 45nm dense patterns in resist.

ASML: i-Line customer topping 150WPH for 24hrs

Wed, 9 Sep 2007
September 12, 2007 - ASML says a Taiwanese customer achieved a record throughput using the company's TwinScan XT:400F i-Line scanners -- 150 wafers/hr for 24 hrs, producing nearly 3600 wafers in a single day earlier this spring.

X-Fab upgrades 0.35-micron process to be "fully modular"

Tue, 9 Sep 2007
September 11, 2007 - X-Fab Silicon Foundries says it has enhanced two of its 0.35-micron chip processes to widen offerings for chip designers working on analog/mixed-signal and smart-power applications. X-Fab says the upgrades amount to the first fully modular 0.35-micron foundry process, encompassing digital, analog, lower on-resistance, high-voltage, and embedded non-volatile memory features.

Aviza, Mosel Vitelic to make ALD films for flash devices

Tue, 9 Sep 2007
September 11, 2007 - Aviza Technology Inc. and Mosel Vitelic Corp. have signed a pact to jointly develop advanced atomic layer deposition (ALD) materials for next-generation flash applications.

Firms tout "end-to-end etch process" for NIL

Mon, 9 Sep 2007
September 10, 2007 - NIL Technology and Oxford Instruments say they have developed a common etch process that covers all etch steps in nanoimprint lithography production.

Lam, Novellus take two paths to strip wafer edges

Tue, 9 Sep 2007
Silicon wafer edges induce inherent non-uniformities in processing, and also seem to be the main source of defects for immersion lithography. Cleaning/stripping the wafer edge (or "bevel") is thus essential for production yield. Here follows a tale of two companies, two machines, and two different ways to solve the edge problem by dry stripping.

Samsung makes an enterprise play with SSDs

Tue, 9 Sep 2007
The growing role that solid-state drives, which use NAND flash memory to store digital data, are playing in the storage market, was the subject of much discussion at the IDEMA DISKCON 2007 conference (9/19-20). Samsung, for one, is upbeat for new applications as costs decline and densities soar, and has big plans to cut costs further. However, the fact is that disk drives are still the storage technology of choice -- and the rise of consumer demand is actually helping HDDs as much as flash.

Analysts debate impact of efficiency, consumer on process equipment stocks

Fri, 9 Sep 2007
Analysts presenting at a SEMI breakfast panel on Sept. 19 reviewed changes reshaping the chipmaking and equipment industries, agreeing on several fronts such as progress in production efficiencies and an increasingly consumer-reliant future. But there was plenty of room for debate about the real growth possible in certain new markets (e.g. photovoltaics), and what the sum of all these parts means for investors.

Brion debuts tools for dual dipole and custom illumination

Tue, 9 Sep 2007
Brion Technologies, the computational lithography wing of lithography toolmaker ASML, says its Tachyon system will now do the mask transformations needed for dual dipole lithography, to permit chip designs to approach more closely to the limit of single resist exposure technology. Also, to enhance the process window for repetitive structures in memory, Brion's LithoCruiser can now co-optimize the diffractive optical element needed for custom illumination along with the mask pattern.

Cadence leverages recent acquisitions with new products

Mon, 9 Sep 2007
September 10, 2007 - Targeting 45nm design, Cadence announced several new design flows that will be part of the 7.1 release of its Encounter digital IC platform in October. Described by the acronym WYDIWYG ("what you design is what you get"), the flows leverage products from the acquisition of Praesagus (CMP Predictor) and ClearShape Technologies (InShape and OutPerform, for physical and electrical variability analysis).

IMEC tips early EUV results, readies for preproduction tool

Tue, 10 Oct 2007
October 16, 2007 - IMEC has tipped initial results of alpha-demo work on extreme ultraviolet (EUV) lithography work which it says produced the first high-resolution images, and has agreed to push ahead with plans to add a "preproduction" tool from partner ASML in its 300mm facility in time for the 22nm node in 2010.

VACUUM: Fifty years of vacuum technology marked by evolutionary advances

Tue, 10 Oct 2007
By Stephen Ormrod, Edwards, West Sussex, United Kingdom EXECUTIVE OVERVIEW Vacuum technology is not often considered as leading semiconductor manufacturing. However, a look back at the last 50 years reveals that it has played an essential supporting role. Complex interactions between vacuum and manufacturing technologies have inspired

E-shuttle starts 65nm prototyping with e-beam direct write

Tue, 10 Oct 2007
E-Shuttle, the joint venture of Fujitsu Ltd. and Advantest Corp., aims to bring down ASIC development costs by using e-beam direct write instead of masks for some critical layers in its prototyping service for 65nm chips starting this month, company president Haruo Tsuchikawa tells SST partner Nikkei Microdevices.

Molecular Imprints touts imprint litho for 22nm CMOS

Tue, 10 Oct 2007
In what it claims is validation for imprint lithography for 22nm CMOS, Molecular Imprints Inc. (MII) is touting results from Toshiba, reported at the 33rd International Conference on Micro-and Nano-Engineering (MNE, Copenhagen, Denmark, Sept. 23-26), which show defect levels "very similar" to those seen in the early days of immersion lithography.

IMEC achieves contact patterning with no assist features

Thu, 10 Oct 2007
Research presented by IMEC at the SEMATECH Immersion Workshop in Colorado shows patterning of through-pitch contact layers without assist features using combined illumination sources and two ASML immersion scanners.

Oxford Instruments goes 3-for-3 with ICP etching for NIL

Tue, 10 Oct 2007
WaferNEWS talks with Oxford Instruments about why it's following the money with its inductively coupled plasma tool into nanoimprint lithography applications, to fill NIL's particularly critical needs in stamp etch, descum, and etching of the polymer mask.

Samsung touts 30nm NAND flash using double-patterning

Tue, 10 Oct 2007
October 23, 2007 - Samsung Electronics Co. Ltd. says it has developed 64Gb multilevel cell NAND flash memory chip using 30nm process technology, built using double-patterning lithography, with commercial chips ready in about a year.

SEMI hands out awards to UT-Austin's Willson, IBM's Meyerson

Thu, 10 Oct 2007
October 18, 2007 - At its annual award banquet, SEMI has named winners of two awards: UT-Austin's C. Grant Willson, for his work in chemically amplified resists; and IBM's Bernie Meyerson for a lifetime of technical innovation.

Yale U. dedicates new nanodevice fab

Fri, 11 Nov 2007
November 2, 2007 - Yale U. has dedicated a new $8 million, 2600-sq.-ft cleanroom facility for its Center for Microelectronics Materials and Structures for fabricating micro- and nano-scale devices for engineering research. The Center serves over a dozen research groups, nearly 40 students in engineering, and an increasing number of collaborators.

"In-the-trenches" roundup of ISMI

Tue, 10 Oct 2007
People doing the actual day-to-day work in fabs gathered at last week's ISMI Manufacturing Symposium (Oct. 24-25, Austin, TX), addressing topics on yield improvement/productivity methodologies, ESH, and sustainability. Specific talks focus on how to fix litho "hot spots," cleaning wafer chucks without DI water or solvents, guidelines for detecting/preventing electrostatic discharge (ESD) events, and why process stability may be the deciding factor in the battle over 450mm wafers.

Immersion lithography reaches new heights at CO symposium

Tue, 10 Oct 2007
Attendees at last week's International Symposium on Immersion Lithography in Keystone, CO, heard that three types of 193nm water immersion exposure tools are being used for 55nm/~50nm/<50nm mass production, with solutions for the few remaining difficulties at hand, and machines achieving the maximum resolution possible with water are being delivered in time for the 45nm node. However, the course beyond 45nm seems murky, and decisions must be made soon about deploying high-index technology.

Doubling down at BACUS

Mon, 10 Oct 2007
Double patterning technology seemed to be the consensus choice for the next half-pitch node or two for the maskmakers convened in Monterey for SPIE's annual BACUS Symposium on Photomask Technology (Sept. 16-21) -- not that anyone thinks it will be easy. The evident delay in EUV technology poses special challenges for the photomask community, highlighted in a special Friday session subtitled: "Twice the pain for twice the gain."

BACUS 2007: Pushing optics yet again to 32nm

Tue, 10 Oct 2007
This year's BACUS meeting was all about the 32nm node, and with EUV and nanoimprint still not ready, it's clear that the industry will use today's immersion processes plus double patterning lithography. Discussions involved how to get the needed incremental improvements in image placement errors and CD uniformity, and ongoing progress in mask blanks, e-beam writers, resists, and inspection/repair tools. And two innovations that will help sustain the future pace of this industry were debuted.

BACUS keynote: The new business model is collaboration

Tue, 10 Oct 2007
Rick Wallace, CEO of KLA-Tencor, launched BACUS 2007 with his keynote speech highlighting the technical and business challenges facing mask toolmakers. An early leader in mask inspection equipment, KLA-Tencor at first relied on technical innovation, he noted. In its middle years, 24 x 7 production reliability was the top priority. Now a new business model is needed: collaboration with key customers and supplier.

Mask industry survey: Steady as she goes, no icebergs ahead

Tue, 10 Oct 2007
The photomask industry is puttering along as usual, with mask revenues as a percentage of the global semiconductor industry remaining steady, as are the number of plates shipped, according to the annual self-assessment survey presented by Gil Sheldon at the SPIE Symposium on Photomask Technology (Sept. 18). Almost all of the papers presented at this year's BACUS dealt with refinements of technology supporting optical lithography, with EUV and imprint notably under-represented.

Call for improved EDA tools at the Common Platform Tech Forum

Mon, 11 Nov 2007
Advanced technology design was a major topic at this year's Common Platform Tech Forum (Nov. 6, Santa Clara, CA). The good news/bad news is that there are no new major design concerns at 45nm, but the hurdles the industry faced at 65nm are even more challenging at 45nm, and EDA tools need to be improved to overcome them.

What's really behind the top foundries' 2008 capex cutbacks?

Tue, 11 Nov 2007
After forecasting good to "lackluster" 4Q sales forecasts, the top pure-play foundries (TSMC, UMC, SMIC, and Chartered) say they will reduce spending in 2008, (10%-25% declines or more). Their stated reasons -- improve productivity in current production, migrate more mature processes down to 90nm and 65nm, and get ASPs back up and improve profitability -- send a great message to the investor community. But the real reason could be a much bigger shift in the leading-edge foundry business model.

Tackling systematic/random variations while matching process chambers

Mon, 11 Nov 2007
Few fab management practices are more "in the trenches" than using mathematics and statistics to investigate and solve real-life problems. One such technique highlighted at the recent ISMI Symposium on Manufacturing Effectiveness was "multivariate analysis" -- specifically, comparing two ashing chambers that were supposed to be matched, but whose output showed differences.

Intel product launch event yields more insight into its manufacturing strategy

Tue, 11 Nov 2007
Based on talks at Intel's Research Day in June, it appeared the company's proprietary pixelated mask technology would not be required at 32nm, but it would be ready for 22nm in case EUV and double-patterning are not. Fast-forward to this week's celebrated launch of 17 new Intel products, all based on 45nm node technology, and a few clues are emerging as to what's next on the company's lithography roadmap -- but it's still not clear if the pixelated mask technology will be used at 32nm.

ASMI licenses ALD to Hitachi Kokusai

Thu, 11 Nov 2007
November 28, 2007 - Hitachi Kokusai Electric has agreed to license ASM International's patents for batch atomic layer deposition (ALD) technology, to bolster its own work in the technology.

ASML, Zeiss, Canon licensing litho tool IP

Fri, 12 Dec 2007
December 21, 2007 - ASML and Carl Zeiss SMT say they have agreed to cross-license patents with Canon in their respective fields of semiconductor lithography and optical components, meaning they can market products using technology covered by the others' litho equipment-related patents.

IEDM news: TSMC reports 32nm SRAM, sans HK+MG

Tue, 12 Dec 2007
December 10, 2007 - Top global foundry TSMC says it has developed a 2Mb SRAM test chip with 32nm process technologies that supports both analog and digital functionality -- and doesn't rely upon high-k gate dielectrics or metal gates.

KLA-Tencor, Nikon collab to corral "mix-and-match" litho setups

Tue, 12 Dec 2007
December 10, 2007 - KLA-Tencor and Nikon say they have developed a set of fully automated system tools for correcting overlay errors in "mix and match" lithography setups that encompass tools of varying capabilities and from different suppliers.

JSR, IBM to work on new materials, self-assembly

Mon, 12 Dec 2007
December 10, 2007 - IBM and JSR Micro say they will worth together to explore new technologies for emerging semiconductor materials and processes, targeting next-generation lithography as well as self-assembly applications.

Report: Toppan unit prepping 45nm mask volumes

Mon, 11 Nov 2007
November 12, 2007 - Toppan Chunghwa Electronics is readying mass production of photomasks for 45nm chip production to be ready by mid-2008, following the lead of parent company Toppan Printing, according to a Digitimes report.

December 2007 Exclusive Feature #1: "In-the-trenches" roundup of ISMI

Fri, 11 Nov 2007
By Debra Vogler, Senior Technical Editor

The tradition of the ISMI Manufacturing Symposium as an "in the trenches" conference, by and for the people doing the actual day-to-day work in the fabs, continued Oct. 24-25 in Austin, TX. Particular attention was given to topics on yield improvement/productivity methodologies, ESH, and sustainability. Specific talks included how to fix litho "hot spots," cleaning wafer chucks without DI water or solvents...

Successful MEDEA+ collaboration to continue under CATRENE

Fri, 12 Dec 2007
This year's MEDEA+ annual forum in Budapest, Hungary (Nov. 26-28) reviewed final projects for the eight-year pan-European collaborate program for microelectronics R&D, set to expire in 2008 after overseeing three generations of CMOS technology and making the European industry a world leader in such sectors as automotive electronics, smart card technology, and image sensing.

IMEC reports record in tall triple-gate device SRAM cell for 45nm node

Mon, 12 Dec 2004
December 13, 2004 - At today's IEEE International Electron Devices Meeting in San Francisco, IMEC is expected to announce that it has achieved the smallest triple-gate device SRAM cell reported to date. IMEC's device is a fully working 6-transistor SRAM cell with an area of only 0.314 x 0.314 mm.

ASML, Micronic ink maskless litho deal

Tue, 12 Dec 2004
December 21, 2004 - Micronic Laser Systems AB, Taby, Sweden, has agreed to license its patents relating to spatial light modulator (SLM) and datapath technologies to ASML Netherlands BV for use in optical maskless lithography for semiconductor applications.

SEMATECH North reduces defects in mask blanks at 80nm

Tue, 12 Dec 2004
December 21, 2004 - Researchers at SEMATECH North have reached a milestone in reducing deposition tool-generated defects in mask blanks used for extreme ultraviolet lithography (EUVL). They have deposited EUV multilayers with as few as one defect/mask at 80nm resolution, which translates into 0.005 defects/square centimeter.

Researchers tout III-V silicon achievement

Thu, 11 Nov 2004
November 4, 2004 - Scientists from Royal Philips Electronics and the Kavli Institute of Nanoscience at Delft U., The Netherlands, claim they've achieved the first successful integration of III-V nanowires on germanium and silicon substrates.

Happy Thanksgiving!

Wed, 11 Nov 2004
The staffs of Solid State Technology, Microlithography World, and WaferNews wish you a happy thanksgiving.

Renesas Tech to merge subsidiary unit Trecenti

Wed, 12 Dec 2004
December 22, 2004 - Renesas Technologies Corp., the world's fifth-largest chipmaker, said Tuesday it will merge its wholly-owned unit, Trecenti Technologies Inc., into its parent entity in March 2005, according to the Nihon Keizai Shimbun America.

UMC enhances 90nm manufacturability using Synopsys technology

Tue, 12 Dec 2004
December 21, 2004 - Synopsys Inc. and UMC have announced that UMC is using Synopsys' alternating aperture phase-shift mask (AA-PSM) technology to enhance manufacturability for its 90nm process.

Coherent Inc.'s Lambda Physik to discontinue future litho product development

Thu, 12 Dec 2004
December 16, 2004 - Coherent Inc. today announced its Lambda Physik subsidiary would discontinue future product development and investments in the semiconductor lithography market due to market conditions. Lambda will continue to support its installed lithography base.

EV Group launches global consortium on nanoimprint litho

Tue, 12 Dec 2004
December 7, 2004 - EV Group today announced the launch of a global consortium, NILCom, dedicated to commercializing advanced nanoimprint lithography (NIL) technologies. The consortium will have a technology platform supported by an established infrastructure and qualified processes, including leading technology companies and research centers.

EV Group, Komag Inc. collaborate on high-volume nanoimprint lithography

Fri, 12 Dec 2004
December 3, 2004 - EV Group (EVG) has said that it has signed an agreement with Komag Inc. to develop, license, and sell a high-volume nanoimprint lithography (NIL) application for mass data storage.

Applied Materials, ASML bring immersion litho to Maydan Technology Center

Thu, 12 Dec 2004
December 2, 2004 - Applied Materials Inc. and ASML intend to collaborate to speed the development of 65nm and below process equipment technology for the semiconductor industry, the companies said.

Applied Materials, DuPont Photomasks collaborate for 90nm, 65nm Masks

Thu, 12 Dec 2004
December 2, 2004 - Applied Materials Inc. and DuPont Photomasks Inc. have agreed to a joint development program (JDP) for advanced photomasks supporting 90nm and 65nm technology.

IMEC strengthens support for 45nm research

Tue, 10 Oct 2004
October 12, 2004 - European research consortium IMEC, Leuven, Belgium, has added a roster of equipment makers to its sub-45nm CMOS research platform.

IMEC, KLA-Tencor set sights on sub-65nm metrology

Thu, 10 Oct 2004
October 7, 2004 - KLA-Tencor Corp., San Jose, CA, and Belgium-based research center IMEC have begun a joint development project to accelerate adoption of optical critical-dimension (CD) metrology technology for sub-65nm semiconductor applications.

Exclusive Feature: ATOMIC LAYER DEPOSITION

ALD: A market and technology update

Tue, 10 Oct 2004
Dr. Paula Doe, Contributing Editor
High-k films for DRAM capacitors look poised to create real volume production demand for atomic layer deposition (ALD) tools. But furnace makers with new batch ALD furnaces may challenge the leading ALD suppliers' single-wafer cluster tools for the business. Samsung has started using batch ALD in its 90nm memory production, reportedly with tools from several different suppliers.

DuPont Photomasks expands Round Rock, TX, facility

Fri, 10 Oct 2004
October 29, 2004 - DuPont Photomasks Inc. said it is installing at its advanced photomask production facility in Round Rock, TX, a leading-edge photomask production line to support semiconductor devices at volume production with 90nm design rules and prototype devices with 65nm design rules. The total investment represents more than $30 million.

JMAR awarded additional $2.1 million x-ray mask funding

Thu, 9 Sep 2004
September 30, 2004 - JMAR Technologies Inc.'s systems division has received an additional $2.1 million in funding from the US government Naval Air Warfare Center to procure sub-100nm feature x-ray masks for next-generation lithography, and to produce Zone Plate optics for x-ray microscopes and x-ray nanoprobes.

Intel invests again in EUV

Wed, 2 Feb 2004
February 25, 2004 - Intel Corp., Santa Clara, CA, has agreed to make an equity investment in Media Lario International SA, an Italian developer of optical components for extreme ultraviolet (EUV) lithography.

Nikon, TEL accelerate 193nm immersion plans

Thu, 2 Feb 2004
February 19, 2004 - Nikon Corp. and Tokyo Electron Ltd. are accelerating their co-development of 193nm immersion lithography tools with a sooner-than-expected mass production start date of late 2H05.

Toshiba, Synopsys pair for chip design

Tue, 2 Feb 2004
February 3, 2004 - Toshiba Semiconductor Company has licensed phase-shift mask technology from Synopsys Inc., Mountain View, CA, to help it ramp to volume production of 65nm process chips.

Nikon opening worldwide training center

Thu, 2 Feb 2004
February 5, 2004 - Nikon Corp. is building a $70 million worldwide training center in the US, following entrenched efforts from rivals ASML and Canon.

Dow takes aim at 193nm litho

Tue, 1 Jan 2004
January 20, 2004 - Dow Corning, Midland, MI, has unveiled new lithographic materials for use in developing 193nm photoresists and anti-reflective coatings used in 65nm processes.

Nikon aims for EUVL in '04

Wed, 1 Jan 2004
January 14, 2004 - Nikon Corp., Tokyo, Japan, plans to start full-scale production of extreme ultraviolet (EUV) lithography systems this year, with a planned launch in 2006 for use with 45nm and 32nm chips.

Intel opens wallet for EUV litho

Mon, 1 Jan 2004
January 26, 2004 - Intel Corp., Santa Clara, CA, will invest $20 million over three years in Cymer Inc., San Diego, CA, to help develop extreme-ultraviolet (EUV) lithography.

IMEC, ASML extend litho pact to 193nm

Wed, 1 Jan 2004
January 21, 2004 - ASML and European research center IMEC have extended their collaboration on immersion lithography with the planned launch of an industrial affiliation program for 193nm liquid immersion lithography.

SEMATECH revs up 193nm work

Wed, 7 Jul 2004
July 7, 2004 - Fresh from shuttering its 157nm immersion lithography efforts, International SEMATECH has formed a 193nm Immersion Technology Center (iTC) to support development of the technology, and an initial project to focus on development of the world's first ultrahigh-NA (NA=1.3) 193nm wavelength immersion lithography tool.

Applied takes wraps off sub-65nm CVD system

Thu, 7 Jul 2004
June 8, 2004 - Applied Materials, Santa Clara, CA, has unveiled what it calls a "breakthrough" in chemical-vapor deposition technology: a CVD system that meets requirements for 65nm and below.

SEMATECH spins off R&D wafer fab

Thu, 7 Jul 2004
July 8, 2004 - International SEMATECH, Austin, TX, has created an independent subsidiary of its R&D wafer fab and associated analytical laboratories, to offer a range of services including custom development and prototyping, wafer-processing, and analytical and electrical testing.

TEL, IMEC to work on 193nm immersion litho

Fri, 7 Jul 2004
June 9, 2004 - While SEMATECH turns its attention to 193nm immersion lithography development, Tokyo Electron Ltd. and European research consortium IMEC have expanded their collaboration on lithography technology to include 193nm immersion.

Novellus nabs Angstron, takes ALD steps

Mon, 4 Apr 2004
April 12, 2004 - Novellus Systems Inc., San Jose, CA, has acquired Angstron Systems Inc., Santa Clara, CA, a supplier of atomic layer deposition (ALD) technology, for an undisclosed amount.

TSMC rebrands offerings

Tue, 4 Apr 2004
April 13, 2004 - TSMC has realigned its process technologies into two classes of "technology platforms" in order to add other features and services, and claims to have produced the industry's first fully-functional 65nm SRAM module.

TEL, CEA Leti extend work on 300mm, advanced nodes

Mon, 8 Aug 2004
August 9, 2004 - Tokyo Electron Ltd. (TEL) and European research organization CEA Leti have agreed to jointly research and develop front-end-of-line CMOS process technology, focusing on new materials for CMOS gate stacks.

Intel reports EUV progress, future plans

Mon, 8 Aug 2004
August 2, 2004 - Intel Corp. said it has finished installation of the world's first pilot line for extreme-ultraviolet (EUV) lithography at its 300mm Hillsboro, OR, facility, in an effort to move the technology out of R&D and on track for 32nm IC production by 2009.

DuPont Photomasks begins commercial production in Dresden

Thu, 5 May 2004
May 13, 2004 -- DuPont Photomasks Inc. has begun commercial production at its advanced photomask production facility in Dresden, Germany. The new facility will support semiconductor devices with design rules of 65nm and below.

ORA wins $1.7M ATP award for advanced litho modeling

Tue, 5 May 2004
May 10, 2004 -- The National Institute of Standards and Technology (NIST) has awarded Optical Research Associates, Pasadena, CA, a $1.7 million Advanced Technology Program award for the development of advanced lithography modeling algorithms, reported the company.

Litho project gains $36M funding

Wed, 5 May 2004
May 5, 2004 - A proposed $36 million JV to develop nanoimprint lithography has received approval by the National Institute of Standards and Technology's (NIST) Advanced Technology Program.

SEMATECH inks state research deal

Mon, 3 Mar 2004
March 29, 2004 - SEMATECH and the state of Texas have agreed to launch a five-year, $200 million project to accelerate the development of next-generation semiconductors, as well as support projects for nanotechnology and other related areas.

Bye-bye, SiGe BiCMOS in cell phones, says TI

Thu, 2 Feb 2004
Silicon-germanium BiCMOS has been relegated to the status of a niche technology at Texas Instruments Inc., now that the Dallas-based company has demonstrated a single-chip CMOS concept for next-generation radio circuits used in cellular phones and other portable wireless applications.

A (very) small measure of success

Wed, 2 Feb 2004
February 11, 2004 - A device created at MIT makes the most precise measurement device of all: the Nanoruler, with "ticks" a few hundred-billionths of a meter apart.

Photronics installing 65nm manufacturing capability

Mon, 6 Jun 2004
June 21, 2004 - The first tools should be arriving shortly at Photronics Inc.'s Austin, TX, facility, the company said today, as it outlined its plans and timing for the installation of advanced reticle manufacturing and process technology necessary to support semiconductor manufacturers building ICs with feature sizes for the 65nm node.

Cadence and ASML agree to develop advanced DFM solutions

Tue, 6 Jun 2004
June 8, 2004 -- Cadence Design Systems Inc. and ASML MaskTools have agreed to a multi-year, multimillion dollar software licensing and joint development agreement for advanced RET software solutions.

SEMATECH picks Carl Zeiss for 193nm development

Wed, 6 Jun 2004
June 9, 2004 -International SEMATECH has selected German lithography firm Carl Zeiss SMT to develop a defect review tool for 193nm immersion lithography photomasks.

ASML, Nikon settling patent claims

Thu, 9 Sep 2004
September 2, 2004 - ASML Holding NV, Veldhoven, The Netherlands, and Tokyo-based Nikon Corp. have mutually agreed to suspend legal proceedings in the US and Asia concerning disputed IP for lithography systems.

EV Group opens second center in Japan

Tue, 8 Aug 2004
August 31, 2004 - EV Group (EVG), a supplier of wafer-bonding and lithography equipment, has opened a second customer-support center in Japan with a significant increase in engineering staff to better serve its growing customer base in that country.

EV Group expands UV-nanoimprint consortium

Wed, 8 Aug 2004
August 25, 2004 - EV Group today announced that a major Canadian research organization has joined its nanoimprint lithography (NIL) consortium formed to commercialize this technology.

Researchers extend thermal nanolithography process

Mon, 8 Aug 2004
August 30, 2004 - Researchers from the Georgia Institute of Technology and Naval Research Laboratory have improved upon a method to directly write nanometer-scale patterns onto various surfaces.

Intel readies 65nm process technology for 2005

Mon, 8 Aug 2004
August 30, 2004 - Last week, Intel presented highlights of its 65nm process technology, which the company has demonstrated on fully functional 70Mbit SRAM chips containing more than 0.5 billion transistors (each cell contains six transistors). The news comes only nine months after the company's disclosure of its first 0.57 sq. micron SRAM logic cell at 65nm.

Albany nanotech facility begins 300mm/193nm work

Thu, 8 Aug 2004
August 26, 2004 - Albany Nanotech, the nanotechnology center located at the U. of Albany/State U. of New York, said that its College for Nanoscale Science and Engineering (CSNE) has installed and begun qualifying for 300mm wafers using a 193nm preproduction immersion lithography system.

UMC powers up 0.18-micron high-voltage process

Wed, 8 Aug 2004
August 18, 2004 - Taiwanese foundry United Microelectronics Corp. (UMC) has made available its 0.18-micron embedded high-voltage technology process, used with portable LCD products to power transistors for applications such as cell phone displays.

UMC: We'll spend more in Singapore

Fri, 5 May 2004
May 7, 2004 - Taiwanese foundry UMC wants to boost its $850 million capex budget for its Singapore operations, but that depends upon the speed and availability of obtaining new equipment.

ASML unveils 193nm litho tool

Tue, 4 Apr 2004
April 20, 2004 - ASML, Veldhoven, The Netherlands, has taken the wraps off of its Twinscan XT:1400 lithography tool, used for 65nm volume production as well as development at the 45nm node.

Synopsys, Photronics join for photomask DFM

Wed, 9 Sep 2004
September 14, 2004 - Synopsys Inc., Mountain View, CA, and Photronics Inc., Brookfield, CT, are forming a joint program to improve design-for-manufacturing (DFM) and mask synthesis for advanced photomasks.

Micron, ASML MaskTools team for litho tools

Wed, 9 Sep 2004
September 15, 2004 - ASML MaskTools, Santa Clara, CA, and Micron Technology Inc., Boise, ID, have signed a multiyear deal to develop applications for resolution-enhancement techniques.

DoD taps Lucent to provide MEMS-based spatial light modulators

Thu, 9 Sep 2004
September 9, 2004 - DARPA has awarded Lucent Technologies a $9.5 million contract to develop an advanced microsystem that will make the design, engineering, and fabrication of next-generation advanced silicon ICs faster, more economical, and with increased security for military apps such as homeland security.

ASML, Zeiss to pay Nikon $145 million

Wed, 9 Sep 2004
September 29, 2004 - ASML and Nikon have finalized details of their patent settlement, announced in early September, regarding lithography equipment.

IMEC sees nano in industry's post-CMOS future

Thu, 9 Sep 2004
September 30, 2004 - The Interuniversities Microelectronics Center (IMEC) has launched a new program to find ways nanotechnology can replace and/or extend the life of advanced CMOS manufacturing technologies.

Synopsys, Photronics pursue DFM links for advanced masks

Wed, 9 Sep 2004
September 14, 2004 - A new joint development program between Synopsys Inc., Mountain View, CA, and Photronics Inc., Brookfield, CT, aims to tighten the links between design software and the production of advanced photomasks for 65nm and below processes.

Order round-up: Akrion, Mattson, Synopsys, Ultratech

Wed, 5 May 2005
May 25, 2005 - A round-up of recent industry activity shows new orders for Akrion, Mattson Technology, Synopsys, and Ultratech products.

Winbond awards contract to ASML

Wed, 5 May 2005
May 18, 2005 - ASML Holding NV (ASML) today announced it was awarded a customer contract from Winbond Electronics Corp. to equip its 300mm fab in Taiwan. No financial details are being disclosed. ASML will install systems from its TWINSCAN platform starting next month.

Photronics launches strategy to drive advanced photomask R&D

Mon, 5 May 2005
May 9, 2005 - Photronics has announced its strategy to drive advanced photomask R&D through a network of global corporate R&D centers. Photronics said its photomask R&D center in Austin, TX, and the recently launched Photronics-PKL R&D center in Cheon-an, Choong-nam, Korea, are working to develop next generation fabrication processes to manufacture high performance IC products down through the 45nm node.

SPIE Report: Canon, Nikon prep multistage immersion platforms

Mon, 3 Mar 2005
New hyper-NA tools aim to boost throughput over ASML's Twinscan

By J. Robert Lineback, Senior Technical Editor

With no "showstoppers" identified yet in immersion lithography, rival scanner makers ASML, Canon, and Nikon are accelerating efforts to take 193nm "wet" exposure tools to the next level, quickly pushing numerical aperture lenses to their feasible limits in systems using water to boost depth of field and resolution for 65nm and 45nm processes.

STEAG HamaTech expands US activities

Tue, 6 Jun 2005
June 7, 2005 - STEAG HamaTech USA Inc., a wholly owned subsidiary of STEAG HamaTech, Sternenfels, Germany, will be expanding its presence in Austin, TX, with an initiative to strengthen US infrastructure capabilities for installed base customer support for photomask process equipment, as well as product development for niche wafer applications.

SEMATECH elevates planar transistor scaling to extend use of conventional CMOS devices

Tue, 5 May 2005
Can SEMATECH Inc. help find new ways to squeeze more life out of conventional planar bulk transistors while delaying the need for nonclassical CMOS devices, such as FinFETs or other multigate FETs? That's the newest objective being added to SEMATECH's list of top 10 technical challenges for 2006, which will be used to formulate and focus about 75 R&D programs next year.

SPIE REPORT: Will market demand catch up to fast immersion developments?

Mon, 4 Apr 2005
TSMC preps 193nm immersion 'risk' production; others still see no technical showstoppers

By J. Robert Lineback

The first wave of production-worthy 193nm immersion scanners now appears to be a shoo-in for at least part of the 65nm process generation and probably the entire 45nm node at decade's end, but industry managers and researchers speaking at the annual SPIE International Symposium on Microlithography attempted to rein in some of the unbridled enthusiasm with...

May 2005 Exclusive Feature: SPIE 2005

Immersion lithography's next wave of tools targets 'hyper-NA' and high 300mm throughput

Fri, 4 Apr 2005
By J. Robert Lineback, M. David Levenson, Senior Editors, Solid State Technology magazine

With no 'showstoppers' identified yet in immersion lithography, rival scanner makers ASML, Canon, and Nikon are accelerating efforts to take 193nm 'wet' exposure tools to the next level, quickly pushing NA lenses to their feasible limits in systems using water to boost DOF and resolution for 65nm and 45nm processes.

Toppan completes acquisition of DuPont Photomasks

Mon, 4 Apr 2005
April 25, 2005 - Toppan Printing Co. Ltd. has announced the successful completion of the acquisition of DuPont Photomasks Inc. Under the terms of the definitive agreement previously announced on Oct. 5, 2004, DuPont Photomasks shareholders will receive US$27 in cash/share. The equity value of the transaction is approximately US$650 million (approximately 68 billion yen) on a diluted basis. The acquisition was approved by shareholders of DuPont Photomasks on March 28, 2005.

Sematech identifies top technical challenges for 2006; adds transistor scaling

Tue, 4 Apr 2005
April 19, 2005 - Sematech has announced its top technical challenges for 2006, continuing to underscore advanced gate stack, 193nm immersion and EUV lithography, mask infrastructure, and low-k dielectrics with process compatibility. Consortium leaders also placed planar bulk transistor scaling on the list for the first time.

Ultratech receives multiple-system orders for litho systems

Tue, 6 Jun 2005
June 14, 2005 - Ultratech Inc. has announced that it has received multiple-system orders from several southeast Asian customers for its NanoTech 190 lithography systems. The NanoTech 190 tools, specifically designed for thin-film head (TFH) applications, will be utilized for back-end rowbar processing -- the processing step required to add the aerodynamic surface to rows of TFH devices before wafer singulation.

TSMC exec promotes 'gigafabs' and 2x tool productivity

Wed, 11 Nov 2005
November 2, 2005 - At International SEMATECH Manufacturing Initiative's (ISMI) 2nd Symposium on Manufacturing Effectiveness, Austin, TX, TSMC's VP of operations Mark Liu told participants he believes that the consumer electronics era may drive IC manufacturers to build more flexible "gigafabs" and persuade equipment makers to double tool productivity.

Eight new SEMI standards cover FPDs and MEMS

Fri, 10 Oct 2005
October 13, 2005 - Semiconductor Equipment and Materials International (SEMI) has published eight new technical standards for the semiconductor, flat-panel display (FPD), and microelectromechanical systems (MEMS) manufacturing industries.

Litho-aware design inspection solution improves device yield

Wed, 10 Oct 2005
October 5, 2005 - KLA-Tencor has formally unveiled DesignScan, the industry's first full-chip process window inspection system for post-RET (resolution enhancement technology) reticle design layout inspection. DesignScan enables chipmakers to reduce the number of mask design respins needed to achieve a high-yielding design, resulting in better parametric design performance and faster time-to-market.

SEMATECH, Synopsys to develop OPC models for 45nm immersion litho

Wed, 10 Oct 2005
October 5, 2005 - Synopsys Inc. and SEMATECH will jointly develop advanced optical proximity correction (OPC) models for the extension of optical lithography. A key goal of the program, part of SEMATECH's 193nm Immersion Lithography Extendibility Project, is to facilitate better understanding of the challenges in process nodes beyond 45nm so participants can develop appropriate software and manufacturing processes. Synopsys will provide its Proteus mask synthesis stoftware.

SMIC, Luminescent enter JDP on 65nm and below nodes

Thu, 10 Oct 2005
October 6, 2005 - Semiconductor Manufacturing International Corporation (SMIC), a Chinese semiconductor foundry, and Luminescent Technologies Inc., a provider of lithography enhancement systems, have announced a joint development program to evaluate Luminescent's inverse lithography technology (ILT) products in SMIC's production environment for its 65nm and below process nodes.

Brion, Crolles2 alliance partners to develop litho process window apps

Mon, 10 Oct 2005
October 3, 2005 - Brion Technologies has announced a joint development agreement with STMicroelectronics, Philips Semiconductors, and Freescale Semiconductor, R&D partners in the Crolles2 Alliance. Brion has delivered RET/OPC process window-enabled applications that run on the company's hardware-accelerated Tachyon platform.

March 2005 Exclusive Features
SPECIAL REPORT: 2004 ITRS Update

Wed, 2 Feb 2005
Roadmap update sharpens industry's future course

Solid State Technology has collaborated with leaders in various technical working groups of the 2004 International Technology Roadmap for Semiconductors (ITRS) to highlight the most significant updates in the new edition of the Roadmap, as well as major challenges to be addressed in the 2005 revision.

STEAG HamaTech, SEMATECH partner on mask cleaning technology

Fri, 2 Feb 2005
February 11, 2005 - STEAG HamaTech announced today that it will work with SEMATECH to develop cleaning technology for 30nm soft defect removal, concentrating on EUV masks and advanced PSM for 193nm immersion lithography, in collaboration with material suppliers, research institutes. and other equipment suppliers.

What's next after IBM, TSMC immersion lithography tests?

Fri, 1 Jan 2005
J. Robert Lineback, Senior Technical Editor

The next big step for development of 193nm immersion lithography will be fully equipped R&D pilot lines, expected to be operational in early 2005. These pilot lines will define immersion-related defectivity issues in functioning devices.

IBM says immersion works - at least in one microprocessor layer

Fri, 1 Jan 2005
J. Robert Lineback, Senior Technical Editor

Out of the blue comes an unexpected milestone in immersion lithography. IBM Corp. has plunged ahead and used a 193nm immersion scanner to print an interconnect layer on fully functional 64-bit microprocessors to prove that adding water to lithography really works.

Europe looks to lead in nanoelectronics

Fri, 1 Jan 2005
Brian Dance, Contributing Editor (Europe) Illustrating the need to ensure European technological and industrial competitiveness in the nanoelectronic sector as essential for industrial and economic growth, the MEDEA+ (Microelectronics Development for European Applications) annual forum in Paris (Nov. 23-24) revealed successes of many pan-European collaborative projects carried out under its umbrella.

IMEC shows 193nm immersion progress on ASML system

Fri, 9 Sep 2005
September 16, 2005 - At the recent 2nd International Symposium on Immersion Lithography, held in Brugges, Belgium, the Interuniversity MicroElectronics Center (IMEC) presented the first conclusive exposure results on its newly upgraded ASML XT:1250i immersion lithography tool.

IBM, Applied, Albany NanoTech forge $300M pact

Thu, 9 Sep 2005
September 29, 2005 - IBM Corp., Applied Materials, and Albany NanoTech in New York have agreed to begin a five-year, $300 million R&D and economic outreach program, bringing in more than 100 engineers to work on six areas of next-generation chip technology: 300mm epitaxial substrates, ultralow-k dielectrics, atomic-layer deposition, chemical-mechanical polishing, copper plating, and ultrafine ion implantation technology for nanoscale semiconductor devices (e.g. ultrashallow junctions).

IMEC, TEL prep EUV, immersion lineup

Thu, 12 Dec 2005
December 8, 2005 - European R&D consortium IMEC is installing two 300mm coater/developer tools from Tokyo Electron Ltd. for use in EUV and 193nm immersion lithography work.

ASML receiving EUV parts, sets 2006 litho tools schedule

Thu, 12 Dec 2005
December 8, 2005 - ASML said it plans to ship 20-25 immersion lithography systems in 2006, including shipments to Japan, and is now receiving components for its first EUV alpha tools being delivered next year to IMEC and Albany NanoTech.

Toppan Photomasks delivers EUV masks to ASML

Thu, 12 Dec 2005
December 1, 2005

Soitec partners with Sematech to develop multigate FETs for 45nm and below

Tue, 1 Jan 2005
January 4, 2005 - In an effort to accelerate the development of new-generation transistors, Soitec has announced its participation as the SOI substrate supplier in a development program led by the Advanced Technology Development Facility (ATDF), the new independent subsidiary of Sematech for advanced semiconductor R&D in Austin, TX.

Euro EUV program touts power output milestone

Fri, 12 Dec 2005
December 9, 2005 - A European Commission-sponsored research project said it has achieved a significant breakthrough with development of a 800W EUV light source.

NanoDynamics seeks to market nanowires

Thu, 12 Dec 2005
December 2, 2005 - NanoDynamics Inc. and New Zealand-based partner Nano Cluster Devices Ltd. (NCD) say they will commercialize new nanowire fabrication technology, for use in semiconductors and nanoscale electronic devices.

Cymer partners with IMEC on immersion litho

Tue, 1 Jan 2005
January 25, 2005 - Cymer Inc. has announced the integration of a Cymer XLA 105 argon fluoride (ArF) light source on a 0.85 numerical aperture (NA) immersion lithography tool at IMEC's 300mm wafer fab facility in Leuven, Belgium.

Photronics acquires additional shares of PKL Ltd. in Korea

Mon, 1 Jan 2005
January 24, 2005 - Photronics Inc., a supplier of imaging technology solutions for the global electronics industry, on Friday reported that it has acquired an additional 6.5% interest in PKL Co. Ltd. in Korea. As a result of this transaction, Photronics now owns approximately 87% of PKL.

DuPont Photomasks to close Kokomo, IN, facility

Wed, 1 Jan 2005
January 19, 2005 - DuPont Photomasks Inc. has said that as part of a consolidation plan designed to reduce costs and improve capital productivity, operations in its trailing-edge photomask production facility in Kokomo, Indiana, will begin to ramp down immediately. The equipment within the Kokomo site will be disposed of or relocated to other DuPont Photomasks sites, and the facility is expected to close during the 4QFY05, ending June 30.

Maskless lithography industry parses business, technical challenges

Tue, 2 Feb 2005
By M. David Levenson, Senior Editor, Lithography

Will an industry that expects optical exposure tools to print more than 100 300mm wafers/hour embrace $20 million lithography systems with throughputs below 5 wafers/hour if they don't require costly masks? If so, at what node? These were two of the questions that 110 participants tried to answer at the first Sematech Maskless Lithography (ML2) workshop, held January 17-19 in San Jose, CA.

DuPont Photomasks receives Spansion award for yield improvements

Fri, 3 Mar 2005
March 25, 2005 - DuPont Photomasks Inc. has received a Spotlight Award from flash memory device maker Spansion LLC for helping Spansion's FAB25 in Austin, TX, enhance wafer yield. Spansion's award recognizes DuPont Photomasks' role in a joint-development project aimed at boosting yield by targeting improvement of layer-to-layer registration when chip designs are etched on wafers. Spansion, formerly known as FASL LLC, is the flash memory subsidiary of AMD and Fujitsu Limited.

Photronics expands FPD mask fabrication, service into Taiwan

Tue, 3 Mar 2005
March 22, 2005 - Photronics Inc. has announced plans to expand its flat panel display (FPD) mask capacity through the construction of a state-of-the-art FPD mask fabrication facility in Taichung, Taiwan. This new 10,100 sq. m. facility will support Taiwan's rapidly expanding FPD fabrication industry.

New priorities reshape DFM landscape:

Integration issues pose challenges for fabs, foundries, and fabless

Tue, 7 Jul 2005
Read the beginning of this article.

Lower-k dielectrics struggle toward volume production

Tue, 7 Jul 2005
By Bob Haavind, Editorial Director

Fabs are filling dielectrics with air bubbles, sunning them under UV lamps, and putting on caps to keep molecules in place, but after a decade of development, really low-k (k<3) still has not made it into volume production.

Strategic Business Forum: Why simulation could push designers to start using DFM

Tue, 7 Jul 2005
By: Dr. Paula Doe, Contributing Editor

Narrowing process windows, emerging tools for statistical analysis of design, and model-based simulations of yield results may soon push designers to actually design for manufacturability, argued experts at Semi's Strategic Business Forum in Welches, OR, May 9-11.

Nikon develops advanced immersion system for 45nm process development

Fri, 7 Jul 2005
July 1, 2005 - Nikon Corp. said yesterday that it has developed a stepper capable of fabricating semiconductor chips with a linewidth of 50nm or smaller, for launch late this year, according to JIJI and other press reports. The NSR-S609B, an ArF immersion scanner with an NA projection lens of 1.07, is targeted at mass production of 55nm and development of 45nm devices.

JMAR awarded $7.5 million more by NAVAIR for x-ray mask program

Fri, 7 Jul 2005
July 1, 2005 - The US government's Naval Air Warfare Center (NAVAIR), under DARPA sponsorship, has granted JMAR Technologies Inc. a two-year extension valued at $7.5 million to its existing three-year $10 million contract to continue development of sub-100nm feature x-ray masks for next generation lithography and production of Zone Plate optics for x-ray microscopes and nanoprobes.

KLA-Tencor, Aprio to collaborate on advanced mask design inspection and repair tools

Mon, 7 Jul 2005
July 25, 2005 KLA-Tencor and Aprio Technologies today announced their intent to collaborate on the development of an integrated advanced mask design inspection and repair tool. Both companies assert that this partnership will encourage better collaboration between their customers' design and manufacturing teams. As part of this collaboration, Aprio will provide new functionality to products under development at KLA-Tencor that address automated mask layout inspection.

Ultratech names new senior VP of engineering for lithography

Fri, 7 Jul 2005
July 22, 2005 - Ultratech Inc. has announced the appointment of Andrew Hawryluk, Ph.D., to the position of senior VP of engineering for lithography and laser processing. Hawryluk, 51, has over two decades of experience in the semiconductor industry, including high-level positions at Photon Dynamics and KLA-Tencor Corp.

Ushio to acquire half of German chip equipment maker

Mon, 7 Jul 2005
July 18, 2005 - Ushio Inc. said Friday it will acquire an equity stake of 50% in Xtreme Technologies GmbH of Germany, a developer of lithography devices used to make semiconductor chips, from Lambda Physik AG of Germany, reports Jiji news.

Intel, Corning enter JDA for EUV photomask substrates

Thu, 7 Jul 2005
July 7, 2005 - Intel Corp. and Corning Inc. have entered into a joint development agreement (JDA) to develop ultra-low thermal expansion (ULE) glass photomask substrates required for extreme ultraviolet (EUV) lithography technology. The JDA will help to enable chip production using EUV technology starting in 2009.

ASML licenses technology to Toshiba

Tue, 9 Sep 2005
September 20, 2005 - ASML Holding NV today announced that electronics giant Toshiba Corp. purchased a license for its patented lithography technology that helps manufacturers increase their chip yields. Toshiba joins more than 20 chipmakers and foundries in adopting ASML's Scattering Bar Technology. Toshiba will use the technology in the production of semiconductor devices.

SEMATECH receives key litho tool to develop advanced ICs

Fri, 9 Sep 2005
September 2, 2005 - SEMATECH has received a key tool for exploring the extension of immersion lithography to produce advanced semiconductors at the 45 nm half-pitch lithography generation and beyond. The tool, an interference immersion exposure system from Amphibian Systems, will be placed in the Immersion Technology Center, which focuses on extending immersion lithography beyond pure water-based approaches.

DNP, ST enter photomask alliance

Tue, 5 May 2002
Tokyo, Japan, and Geneva, Switzerland - Dai Nippon Printing Co. Ltd. (DNP), a manufacturer of photomasks, and STMicroelectronics, a supplier of semiconductor devices, have formed a strategic alliance for the development and supply of leading edge and high-end photomasks.

Japan's chip industry to develop lithography tech with gov't backing

Wed, 5 May 2002
Tokyo, Japan - Major Japanese semiconductor makers and makers of related equipment will join together to develop EUV technology with the support of the government, industry sources said.

DuPont Photomasks, Infineon, AMD lay out ambitious photolith plans

Thu, 5 May 2002
Dresden, Germany -- Infineon Technologies AG, Advanced Micro Devices Inc., and DuPont Photomasks Inc. plan to establish and operate a new advanced photomask facility in Dresden, with investments of around EUR 360 million over the next five years.

Hard evidence for the increasing importance of materials

Thu, 5 May 2002
Despite the overall industry's worst year ever, sales remained relatively stable at a range of suppliers of enabling materials, as users kept buying photomasks, slurries, and compound semiconductor substrates even if they weren't equipping fabs. But the damage in the volume-dependent silicon wafer business was staggering.

ASML expects to sell 140 To 180 litho systems in '02

Fri, 5 May 2002
Dutch toolmaker ASML Holding NV expects to sell between 140 and 180 lithography systems in 2002, down from 197 systems last year, ASML spokesman Tom McGuire said Friday.

Applied-Canon PMTC targets 100nm interconnect

Mon, 6 Jun 2002
A recently announced collaboration between Applied Materials Inc., Santa Clara, CA, and Canon Inc., Tokyo, Japan, will possibly benefit the entire semiconductor industry by improving the time to market for devices, but the lithography firm hopes the agreement will specifically allow it to spot and address any tool issues that pop up - before the equipment is installed at a customer's site.

CaF2 debate: Flat vs. round, 121nm litho?

Mon, 7 Jul 2002
The Bridgman-Stockbarger method of growing CaF2 has been around for decades. Now that the semiconductor industry has an escalating need for the material - a "must have" for lens systems in 157nm lithography tools - debate has focused on the adequacy of supply and the technique used to obtain it.

Building in China, one relationship at a time

Wed, 4 Apr 2002
What's the key to unlocking the door to the China market? In a word, guanxi - relationships - according to Photronics CEO Dan Del Rosario.

A futuristic AVS conference

Fri, 4 Apr 2002
From air gaps, to ALD (atomic layer deposition) at room temperature, to CVD vs. SOD (spin-on dielectrics) and VICs (vertically integrated circuits) - the recent AVS Conference on Microelectronics and Interfaces was a voyage into the future.

JMAR receives $5.3M to complete integrated X-ray powered lithography system

Thu, 6 Jun 2002
June 20, 2002 - San Diego, CA - JMAR Technologies Inc., a developer and provider of compact point-source, laser plasma lithography systems and sources, has received a contract for $5.3 million from the US Army Robert Morris Acquisition Center in Adelphi, MD, to finance the completion of the first of its integrated proprietary point-source laser plasma lithography systems.

Samsung develops new process integration technology for high-k dielectric films

Wed, 6 Jun 2002
June 12, 2002 - San Jose, CA - Samsung Semiconductor Inc. unveiled its first successful development of a next-generation wafer processing technology in which a hafnium dioxide-aluminum oxide laminate film is fabricated on the silicon wafer using Atomic Layer Deposition.

DuPont Photomasks enters development and supply agreements with Cypress

Mon, 6 Jun 2002
June 17, 2002 - Round Rock, TX - DuPont Photomasks Inc. has signed an agreement with Cypress Semiconductor Corp. to jointly develop advanced photomask technologies supporting the production of high-performance ICs.

ASML enters ALD market

Wed, 4 Apr 2002
Veldhoven, Netherlands - ASML has entered the market for atomic layer deposition (ALD) technology through an exclusive technology licensing agreement with Integrated Process Systems (IPS).

Photronics acquires additional shares of PKL in Korea

Thu, 4 Apr 2002
April 4, 2002 - Jupiter, FL - Photronics Inc. has acquired an additional 859,730 shares, or 28% interest, in PKL Co. Ltd. in Korea.

Schott Lithotec acquires DuPont Photomasks' photoblanks unit

Mon, 4 Apr 2002
DuPont Photomasks Inc., Round Rock, TX, and Schott Lithotec AG, Jena, Germany, have announced that Schott Lithotec USA Corp., has acquired DuPont Photomasks' photoblank business unit in a deal worth up to $42 million.

SEMATECH goes EUV

Tue, 4 Apr 2002
International SEMATECH, Austin, TX, has placed the first purchase order for an MS-13 EUV Microstepper, to be built by Exitech, Oxford, England, and installed in SEMATECH's Resist Test Center.

Intel combines 300mm, low-k, copper, strained Si in 90nm process

Tue, 8 Aug 2002
Hillsboro, OR - Intel Corp. has unveiled several technology developments that it has integrated into its new 90nm process, which it says it has already used to build "record-breaking" silicon structures and memory chips.

Hoya to start SiC wafer biz

Thu, 8 Aug 2002
Tokyo, Japan - Hoya Corp., an advanced glass products manufacturer, plans to establish a new company, Hoya Advanced Semiconductor Technologies Co. Ltd., at Akishuma-shi, Tokyo, for the development and production of silicon carbide wafers.

Dai Nippon Printing, Hoya team up on mask blank development

Thu, 8 Aug 2002
Aug. 8, 2002 - Tokyo, Japan - Dai Nippon Printing Co. and Hoya Corp. have penned a cooperative agreement in the field of mask blanks.

TSMC: Planned China fabs aimed at local market

Tue, 5 May 2002
Hsinchu, Taiwan - Taiwan Semiconductor Manufacturing Co (TSMC) said its planned manufacturing facilities in China will be aimed at the growing mainland market and not exports.

X-wafers printed

Fri, 5 May 2002
In another step towards freeing chip architects from the tyranny of Manhattan geometries, The X Initiative and ASML have announced the first 0.25-micron diagonal features printed on wafers. An ASML PAS 5500/750 DUV step-and-scan tool equipped for annular illumination successfully patterned diagonally oriented interconnect structures characteristic of 0.18-micron node design rules.

DuPont Photomask looks to design automation to cut mask costs

Tue, 5 May 2002
DuPont Photomask doesn't want to be just a maskmaker any more. Instead CEO Peter Kirlin's broader vision is to become a "microimaging solutions supplier." And it looks like it has taken a big step in that direction with its recent acquisition of design automation supplier BindKey Technologies.

Bulky mask data sets create storage problems

Wed, 9 Sep 2002
As mask data sets become more complex and data-intensive, maskmakers face the challenge of how to manage large amounts of data that must be moved from design to mask.

Nanotechnology: Still too early for tool industry's attention?

Mon, 7 Jul 2002
RAVE LLC CEO Barry Hopkins attended the NanoBusiness Spring 2002 conference in hopes of discovering the next generation of customers and applications for his company's photomask-repair tools - hopefully customers in the emerging field of nanotechnology, which could possibly run counter-cyclical to the chip industry's peaks and valleys.

SEMATECH and U. at Albany-SUNY to form strategic alliance

Thu, 7 Jul 2002
Austin, TX, and Albany, NY - Plans for a joint five-year $320 million program to accelerate the development of next generation lithography were announced by International SEMATECH (ISMT), a global consortium of semiconductor manufacturers, and the U. at Albany-SUNY (UAlbany).

Top three toolmakers hold firm; others jockey about VLSI list

Wed, 3 Mar 2002
VLSI Research Inc.'s 2001 Top 10 Equipment Suppliers list saw no movement at the top three spots, but companies four through 10 were jumbled about in the industry's worst year ever.

KLA-Tencor announces new CD analysis systems

Mon, 3 Mar 2002
KLA-Tencor has unveiled a new set of automated tools for process window construction and analysis. The Process Window Monitor series automates the construction of process windows based on focus exposure matrices analyzed using KLA-Tencor CD or optical CD metrology tools.

ASML denies Nikon patent claims

Wed, 2 Feb 2002
Feb. 27, 2002 - Bilthoven, Netherlands - Dutch semiconductor equipment maker ASM Lithography issued a formal denial that it has infringed upon any patents of its major rival, Nikon Corp. of Japan.

E-beam update: Nikon steadily forges ahead with tool for contact layers

Thu, 2 Feb 2002
Nikon reports progress on both the optics and the infrastructure for its e-beam projection lithography, and argues it may still be the best available option for printing critical contact layers at 70 to 35nm, even with low throughput.

Photronics takes fast boat to China

Fri, 3 Mar 2002
Shanghai, China - Photronics Inc. detailed plans to expand into Shanghai, China during a land grant signing ceremony with officials from the Zhangjiang Hi-Tech Park Development Corp.

Intel claims world's first one square micron SRAM cell

Fri, 3 Mar 2002
Researchers at Intel Corp., Santa Clara, CA, have reportedly built the world's smallest SRAM memory cell, measuring only one square micron.

Canon collaborates with AMAT to support process module strategy

Tue, 4 Apr 2002
April 16, 2002 - San Jose, CA - Canon Inc. has signed an agreement with Applied Materials Inc. to collaborate in the development of semiconductor device patterning technology to support Applied Materials' process module strategy for 300mm wafer manufacturing.

Downturn? What downturn? Some companies see improvement, 4Q00 to 4Q01

Tue, 3 Mar 2002
For the most part, 4Q was a painful quarter to cap off what's largely been a painful year. Several companies, however, stood out for one simple fact: Their revenue actually increased from 4Q00 to 4Q01. FEI Co., PDF Solutions Inc., and Numerical Technologies Inc. all saw increases in revenue. Brewer Science doesn't release statements, but the firm said numbers released for the last quarter show overall sales revenue increased by 38% in 2001.

USITC to investigate Nikon claims against ASML

Fri, 1 Jan 2002
Washington, DC - The US International Trade Commission decided has decided to investigate whether Nikon's patents have been infringed upon by Dutch company ASM Lithography.

Mask tech advances attract new members to Leepl consortium

Mon, 1 Jan 2002
Two more potential big users have signed on to the Low Energy E-Beam Projection Lithography consortium (Leepl). Matsushita Electric Industrial and Sharp will now join Sony, Rohm, NEC, and Texas Instruments in working on developing the low-cost alternative next generation lithography technology.

Veeco, Photronics form relationship in next-generation photomask technology

Tue, 1 Jan 2002
Jan. 8, 2002 - Woodbury, NY- Veeco Instruments Inc. and Photronics Inc. have formed a strategic relationship focused on accelerating the development of advanced manufacturing technologies required to fabricate enhanced reticle and next generation lithography mask technologies.

Toshiba's tools for the mini-fab hit the market

Thu, 1 Jan 2002
Toshiba Semiconductor's novel plan to rethink the fab to make small runs of systems chips without big capital investment may not be so far out after all.

Diagonals: A shorter path for interconnect

Thu, 1 Jan 2002
Increased complexity and functionality in semiconductor devices has placed a greater emphasis on interconnects, where delays have become one of the most significant factors affecting chip performance.

Cymer launches ELS-7000 excimer light source

Thu, 1 Jan 2002
Jan. 10, 2002 - San Diego, CA - Cymer Inc. has unveiled its latest krypton fluoride (KrF) production light source-the ELS-7000.

Helium supply: Not up, up, up

Mon, 2 Feb 2002
The word "over" has been used recently to describe current problems within the semiconductor industry - oversupply, overcapacity, etc. But in some areas, too much isn't the problem - too little is. Over the next few years, the industry will be dealing with a shortage in helium, and while it's not a major crisis, it is a source of concern, especially for the lithography sector.

2002 capex: A mixed bag

Wed, 2 Feb 2002
Announcements of decreased capex for 2002 were no surprise to most analysts who regard the new year as one for slow recovery, though Intel's announced cut did fluster a previously upbeat Wall Street.

ASML, Carl Zeiss confirm 193nm capability

Thu, 2 Feb 2002
Netherlands & Germany -- ASML Holding NV and lens partner Carl Zeiss confirmed the availability of 193nm imaging systems in 2002 to satisfy increased market demand for leading edge 0.10-micron ArF imaging solutions.

DuPont Photomasks plans upgrades in Shanghai

Thu, 2 Feb 2002
Shanghai, China - DuPont Photomasks Inc. plans to upgrade the capability of DuPont Photomasks Co. Ltd., Shanghai, its joint venture photomask manufacturing facility.

SPECIAL STAFF REPORT: An OASIS by the sea at BACUS 2002

Fri, 11 Nov 2002
The atmosphere of the 22nd BACUS Photomask Symposium, held recently in Monterey, CA, was oddly upbeat, with a record 156 papers and high attendance, in spite of depressed industry conditions. The mask industry has been hard hit by the slow shift to 130nm and beyond, since most of industry revenue comes from such advanced reticles.

Shipley Co., Numerical partnership for low K1 lithography imaging

Fri, 11 Nov 2002
Nov. 1, 2002 - Marlborough, MA - Shipley Company L.L.C., a provider of electronic materials and process innovations for advanced circuit board technology, semiconductor manufacturing, and advanced packaging, has established a partnership for low k1 lithography imaging with Silicon Valley-based Numerical Technologies Inc.

Cymer to open new facility

Fri, 10 Oct 2002
Cymer Inc. is to build a new manufacturing facility for its advanced lithography light sources, and will implement a new organizational structure. The new facility is designed to accommodate the high-volume production of the company's light source portfolio. This will include the new XL Series product line, which utilizes the dual-gas-discharge-chamber Master Oscillator Power Amplifier (MOPA) architecture.

Sematech and DuPont forge test photomask cross-licensing agreement

Tue, 10 Oct 2002
Oct. 22-Austin and Round Rock, TX-Through a recently signed cross-licensing agreement, International Sematech (ISMT) and DuPont Photomasks have combined their intellectual property (IP) for producing test photomasks. The goal is to use test masks based on the combined IP to strengthen industry standards for photomask inspection and repair systems at the leading-edge technology nodes.

Nikon files complaint in US

Mon, 10 Oct 2002
Oct. 21, 2002 - Belmont, CA - Nikon Corp. and Nikon Precision Inc., a wholly-owned subsidiary located in Belmont, have filed a patent infringement action against ASML Netherlands BV, a Dutch corporation and ASM Lithography Inc., a US company in the US District Court for the Northern District of California, asserting infringement of eight Nikon patents relating to primary structures in stepper and scanner machines.

Corning gets CaF2 lens blank patent

Tue, 10 Oct 2002
Oct. 8, 2002 - Corning, NY - Corning Inc. has received a US patent for a calcium fluoride (CaF2) lens blank that supports the advancement of CaF2 materials for the 193nm and 157nm microlithography systems.

DuPont Photomasks reduces headcount

Wed, 12 Dec 2002
Dec. 4, 2002 - Round Rock, TX - DuPont Photomasks Inc. plans to streamline its European operations by consolidating trailing-edge photomask production in Rousset, France and Hamburg, Germany, into its manufacturing facility in Corbeil, France. These initiatives are expected to reduce the global workforce by approximately 8%, or 140 positions, once fully implemented.

SEMATECH urged to guide industry on immersion technology

Wed, 12 Dec 2002
Dec. 18, 2002 - Austin, TX - More than 100 of the world's top lithography experts attending an International SEMATECH (ISMT) workshop to review the state of immersion lithography technology urged the consortium to help coordinate and accelerate a feasibility study on the technology.

Numerical Technologies licenses phase-shift technology to Samsung

Tue, 12 Dec 2002
Dec. 17, 2002 - San Jose, CA - Numerical Technologies Inc., the provider of subwavelength lithography-enabling technology to the semiconductor industry, today announced that Samsung Electronics Co. Ltd. has signed an agreement to license Numerical's phase-shifting technology for the production of its newest and most advanced SRAM product.

Lithography equipment supplier ASML to cut 1,450 jobs

Wed, 12 Dec 2002
Dec. 18, 2002 - Veldhoven, Netherlands - Chip equipment maker ASML has announced that it will cut 1,450 jobs and sell or close loss-making US businesses, as it strives to reach break-even in the chip industry's worst-ever slump.

ASML restructuring announcement expected

Tue, 12 Dec 2002
Dec. 17, 2002 - Veldhoven, Netherlands - Lithography equipment supplier ASML Holding NV will shortly unveil details of a large restructuring program, according to a person close to the company.

FSA announces fabless supply chain research results

Mon, 4 Apr 2003
April 7, 2003 - San Jose, CA - The Fabless Semiconductor Association (FSA), a semiconductor trade organization, has announced the results of a joint research effort focused on identifying supply chain issues impacting fabless success. The Fabless Supply Chain Study was commissioned by the FSA and conducted by Lions Peak LLC and Santa Clara U.'s Center for Innovation and Entrepreneurship.

Veeco, Schott Lithotec ink photomask deal

Tue, 6 Jun 2003
June 17, 2003 - Veeco Instruments, Woodbury, NY, and Schott Lithotech, Jena, Germany, have signed an agreement to develop advanced photomask technologies.

Photronics cuts work force by 10 to 12%

Wed, 3 Mar 2003
March 26, 2003 - Brookfield, CT - Photronics Inc. will cut its work force by between 10 and 12% and cease manufacturing operations in Phoenix, in an effort to return to profitability by July.

Numerical collaborates with AMAT to develop 193nm lithography processes

Thu, 2 Feb 2003
Feb. 27, 2003 - Santa Clara, CA - Numerical Technologies Inc. has signed a joint development agreement with Applied Materials Inc. to address resolution enhancement technologies (RETs) for 193nm lithography processes.

Exclusive Feature: LITHOGRAPHY

Automated micro-defect monitoring for 300mm lithography

Mon, 2 Feb 2003
By: Kay Lederer, Infineon Technologies SC300, Dresden, Germany
Barry Saville, Ingrid Peterson, KLA-Tencor, San Jose, CA

As the semiconductor industry continues to push toward the 90nm node, controlling defect density in the lithography cell becomes ever more critical to the success of the overall manufacturing process. MORE

Shipley opens new Advanced Technology Center

Wed, 2 Feb 2003
Feb. 5, 2003 - Marlborough, MA - Shipley Company LLC, has opened its Advanced Technology Center (ATC), a facility dedicated to the development of lithography, interconnect, low-k dielectric and other critical materials.

FSI exits resist processing market

Mon, 3 Mar 2003
March 17, 2003 - Minneapolis, MN - FSI International Inc., a manufacturer of capital equipment for the microelectronics industry, said that it intends to discontinue its microlithography business operations and focus exclusively on its surface conditioning business.

IMEC begins construction of 300mm research fab

Tue, 1 Jan 2003
Jan. 28, 2003 - Leuven, Belgium - IMEC's board of directors has announced the construction of a new 300mm cleanroom.

ISMT and UAlbany close deal on EUV lithography program

Tue, 1 Jan 2003
Jan. 28, 2003 - Austin, TX, and Albany, NY - The U. at Albany (UAlbany) and International SEMATECH (ISMT), a global consortium of semiconductor manufacturers, have completed negotiations on a joint five-year program to accelerate the development of next generation lithography.

Seiko Instruments to join LEEPL consortium

Mon, 1 Jan 2003
Jan. 20, 2003 - Tokyo, Japan - Seiko Instruments Inc. will join the LEEPL Technology Consortium, formed by a group of companies from Japan and overseas to develop technology for a next-generation stepper that uses an electron beam as the light source for lithography.

INFICON acquires New Vision Systems

Tue, 1 Jan 2003
Jan. 7, 2003 - Syracuse, NY and Zurich, Switzerland - INFICON Holding AG, a manufacturer of vacuum instrumentation and process control software, has acquired the privately held company, New Vision Systems, a provider of APC and lithography analysis for semiconductor manufacturing.

Exclusive Feature: LITHOGRAPHY

Positive versus negative resist

Fri, 1 Jan 2003
T.A. Brunner, C. Fonseca, IBM SRDC, Hopewell Junction, NY

Simulations imply that narrow resist lines print best with a positive tone resist process while narrow trench geometries are best with a negative tone process, even if the resist performance parameters are unequal. Simple development bias models appear to capture... MORE

ASML inks another litho deal

Thu, 12 Dec 2003
November 25, 2003 - A week after announcing a similar partnership with Dainippon Screen, ASML NV, Veldhoven, The Netherlands, has signed a deal with Tokyo Electron Ltd. to link the companies' lithography and track systems.

ASML, Dainippon Screen sign litho deal

Thu, 12 Dec 2003
November 21, 2003 - ASML NV, Veldhoven, The Netherlands, and Dainippon Screen Manufacturing Co. Ltd., Kyoto, Japan, have agreed to co-develop methods for linking their track and lithography systems.

Nikon sets sights on immersion litho

Thu, 12 Dec 2003
December 2, 2003 - Nikon Corp., Belmont, CA, has unveiled plans to introduce ArF immersion lithography equipment, based on its NSR-S307E 193nm lithography tool.

Canon receives AMD award

Thu, 11 Nov 2003
November 5, 2003 - Canon USA's Semiconductor Equipment Division has received a 2002 Spotlight Award from AMD for its role in servicing and supporting AMD's lithography needs.

SEAJ: Global equipment orders hot, domestic orders not

Fri, 10 Oct 2003
Global orders in August of Japanese semiconductor equipment achieved levels not seen in nearly 15 months, according to the latest figures from the Semiconductor Equipment Association of Japan (SEAJ). Results from a broader perspective, however, appear to be mixed.

AMI Semiconductor aims to lower mask costs with structured ASICs

Wed, 12 Dec 2003
By combining pre-processed wafers from TSMC -- up to metal level 2 -- and then providing custom programming for as many as five metal levels, AMI Semiconductor says it can cut the cost of reticles to about one-quarter of the usual cost.

Sematech qualifies low-k material

Thu, 12 Dec 2003
November 28, 2003 - International Sematech, Austin, TX, says it has qualified an ultra-low-k material for dual damascene copper processing at 0.13-micron features, using 193nm lithography on 300mm wafers.

Canon: Immersion is the future

Thu, 12 Dec 2003
November 17, 2003 - Immersion lithography could replace super-high NA 193nm lithography for 65nm and 45nm production, according to an executive in Canon USA Inc.'s semiconductor equipment division.

ASML MaskTools, Photronics forge alliance

Wed, 12 Dec 2003
December 17, 2003 - ASML MaskTools, Santa Clara, CA, a subsidiary of Netherlands-based ASML, and Photronics Inc., Brookfield, CT, have agreed to co-develop a maskmaking infrastructure for ASML MaskTools' CPL technology, a technique that enables low-k lithography.

JMAR achieves sub-100nm litho

Fri, 12 Dec 2003
December 12, 2003 - JMAR Technologies, San Diego, CA, says its has achieved sub-100nm imaging using its collimated plasma lithography has x-ray source and wafer exposure system.

Sigma-C introduces EUV software

Thu, 12 Dec 2003
December 11, 2003 - Sigma-C GmbH, Munich, Germany, has developed new software to help determine the printability of defects on EUV masks.

Sematech, Asahi Glass shake hands for EUV litho

Thu, 7 Jul 2003
July 3, 2003 - International Sematech (ISMT) and Asahi Glass Co. have signed an agreement to co-develop advanced mask technology and materials for use in EUV lithography.

ETEC wins DARPA funding for litho project

Thu, 7 Jul 2003
July 14, 2003 - ETEC Systems, Hayward, CA, has been awarded a three-year, $13.5 million contract by the Defense Advanced Research Projects Agency (DARPA) to develop sub-45nm lithography systems.

New ASML 193nm tool: 70nm resolution for 200mm fabs

Fri, 10 Oct 2003
ASML's latest 193nm Twinscan XT:1250 stepper makes little incremental improvements to get ordinary old optical lithography down to 70nm half-pitch line resolution with ordinary old binary masks -- for ordinary old 200mm fabs, as well as 300mm.

Micronic unveils mask metrology system

Fri, 10 Oct 2003
October 23, 2003 - Micronic Laser Systems AB, Taby, Sweden, has introduced a new registration measurement system for TFT-LCD photomasks.

Mitsubishi, Fuji Xerox join for optical chips

Thu, 10 Oct 2003
October 8, 2003 - Mitsubishi Heavy Industries and Fuji Xerox have agreed to jointly develop technology combining the functions of optical switches and transformers into a single component.

ATMI unveils process monitoring system

Thu, 10 Oct 2003
September 25, 2003 - ATMI Inc., Danbury, CT, has introduced an RFID-based process monitoring system for liquid materials in a fab, aimed at replacing similar barcode-based systems.

Cymer names litho VP

Thu, 10 Oct 2003
September 29, 2003 - Cymer Inc., San Diego, CA, a supplier of excimer laser light sources, has named Anthony Yen as senior VP of lithography market development.

Chartered takes wraps off 90nm

Fri, 9 Sep 2003
September 18, 2003 - Singapore's Chartered Semiconductor Manufacturing has taken the wraps off its "NanoAccess" 90nm SoC process technology, based on its development work with IBM.

AMAT steps into SEM metrology

Thu, 9 Sep 2003
September 9, 2003 - Applied Materials, Santa Clara, CA, has unveiled a new tool for 65nm-generation mask metrology, adding to its line of pattern generation, etch, and inspection tools.

ASET develops mask for EUV litho

Tue, 7 Jul 2003
July 7, 2003 - The Tokyo-based Association of Super-Advanced Electronics Technologies (ASET), a government-funded electronics research cooperative, says it has developed a way to fabricate high-performance masks for extreme ultraviolet (EUV) lithography.

Varian, Tegal tops in wafer-processing rankings

Fri, 7 Jul 2003
July 18, 2003 - Customers of both large and small wafer-processing companies gave kudos to a wide range of vendors, but overall rankings were lower than in previous years, according to a new report from VLSI. The ratings are calculated based on customer surveys in which suppliers were ranked on a ten-point scale, covering thirteen categories describing equipment performance and customer service.

FASL, GES source Japan fab equipment

Mon, 8 Aug 2003
August 18, 2003 - FASL Japan Ltd., the Japanese arm of a joint venture between AMD and Fujitsu, and GE Global Electronic Solutions have completed a $100 million sale and leaseback of equipment, including machines for lithography, metrology, deposition and tech, and furnace equipment.

Five major chipmakers join IMEC's sub-45nm research platform

Mon, 10 Oct 2003
IMEC, the independent microelectronic research center based in Leuven, Belgium, announced at its annual research review meeting on Oct. 13 that five major chipmakers have joined the center's sub-45nm research platform.

Dai Nippon, STMicro open Italy plant

Thu, 10 Oct 2003
October 15, 2003 - Japan's Dai Nippon Printing Co. and STMicroelectronics have opened a joint photomask plant in Agrate, Italy.

Schott inks EUV deals

Thu, 10 Oct 2003
September 26, 2003 - Schott Lithotec, Jena, Germany, has signed EUV lithography agreements with a pair of industry groups.

SUSS Microtec unveils litho products

Mon, 6 Jun 2003
June 23, 2003 - SUSS Microtec, a supplier of production, process, and test technologies, has introduced a new line of lithography technologies for use in wafer-level packaging, MEMS, and optoelectronics.

Newport targets laser industry with new beam shaper

Fri, 6 Jun 2003
June 20, 2003 - Irvine, CA - Newport Corp. has unveiled a new refractive beam shaper that it claims converts Gaussian laser beam input to produce a collimated, flat-top beam with nearly 100% efficiency.

Exclusive Feature: PHOTORESIST LIMITATIONS

Finding the limits of chemically amplified photoresists

Fri, 8 Aug 2003
By Dar

ASM to relocate Finland R&D

Tue, 8 Aug 2003
August 25, 2003 - ASM International, Amsterdam, The Netherlands, plans to relocate its R&D facilities in from Espoo, Finland, to the University of Helsinki, where the two organizations will jointly develop atomic layer deposition technologies.

China mask firm sets production date

Mon, 8 Aug 2003
August 14, 2003 - Allied Integrated Patterning Co. (AIPC) says it will complete equipment move-in and begin mass production of TFT-LCD photo masks by 2Q04. The affiliate of Allied Materials Technology Corp. (AMTC) hopes to generate sales of $130.8 million in sales by 2008, after an initial capital investment of $52.3 million.

Elpida, Toppan ink photomask deal

Tue, 9 Sep 2003
August 27, 2003 - Elpida Memory, a Tokyo, Japan JV between Hitachi and NEC, and Toppan Printing Co. have agreed to co-develop photomasks for sub-100nm DRAM chips. The photomasks will be used on chips produced at Elpida's 300mm facility in Hiroshima.

With planned FINLE buy, KLA-Tencor gets litho simulation, analysis

Fri, 2 Feb 2000
In an effort to enhance its lithography module control offerings, KLA-Tencor plans to acquire FINLE Technologies, a 10-year old developer of lithography simulation and data analysis software.

Hitachi raises 2000 capex to $1.4B

Thu, 2 Feb 2000
In yet another boost to capital spending, Japan chipmaker Hitachi said it will invest 150 billion yen (about US$1.4 billion) in the semiconductor field in fiscal year 2000.

Lithographers narrow NGL options

Mon, 10 Oct 2000
Austin, Texas--Oct. 16, 2000--Lithographers attending a recent International SEMATECH Next-Generation Lithography (NGL) Workshop recommended that the global industry narrow the NGL options to two technologies--extreme ultraviolet (EUV) and electron projection lithography (EPL)--for commercialization.

JMAR reports lithography technology advancement

Tue, 11 Nov 2000
San Diego, California--Nov. 14, 2000--JMAR Technologies, Inc. recently reported that a series of technological advances in its Picosecond X-ray Light Source (PXS) program now qualify the company's semiconductor lithography product as the enabling technology for a faster, most cost-effective alternative to the direct-write, electron beam sources currently used to produce advanced, sub 0.13-micron gallium arsenide (GaAs) semiconductor ICs.

NIST funds advanced wafer inspection technology development

Thu, 11 Nov 2000
Gaithersburg, Maryland--Nov. 9, 2000--The U.S. National Institute of Standards and Technology's (NIST) Advanced Technology Program (ATP) has awarded $13.7 million in funding for a project to develop advanced wafer inspection technology for next-generation lithography (NGL) applications at the 50-nm and 70-nm nodes.

ASML unveils 193nm lithography tool

Tue, 11 Nov 2000
Veldhoven, The Netherlands--Nov. 7, 2000--ASML Lithography has developed a new 193nm Step & Scan lithography tool for high-volume production of semiconductor devices at the 100nm technology node.

AZ Electronic Materials licenses polymer platforms for 193-nm lithography

Wed, 11 Nov 2000
Somerville, New Jersey--Nov. 1, 2000--AZ Electronic Materials, a business of the Clariant Corp., has licensed polymer platforms from both Fujitsu and Hyundai for its 193-nm photoresists. By leveraging these two polymer platforms, AZ plans to provide solutions for the first critical photoresist layers migrating to 193-nm technology.

IBM, Infineon, and UMC building chips with 0.13-micron technology

Wed, 11 Nov 2000
East Fishkill, New York--IBM, Infineon, and UMC recently announced that they have begun building chips with the most advanced 0.13-micron foundry process technology currently available.

ASML introduces dual wafer stage technology

Wed, 12 Dec 2000
Tokyo, Japan--ASML today introduced dual wafer stage technology for new i-line and deep ultraviolet (UV) imaging systems, extending the product offerings of its TWINSCAN 300mm technology platform. This dual wafer stage system optimizes the lithographic processing of 300mm wafers by parallel operation of two independent wafer stages, according to ASML.

300mm semiconductor processing tool sales may reach $11B in 2001

Wed, 12 Dec 2000
New Tripoli, Pennsylvania--The semiconductor industry's rush to build 300mm fabs for first silicon in 2002 will spur sales of 300mm processing tools to $11 billion in 2001, according to a recently published report, 'The Global Market for Equipment and Materials in IC Manufacturing,' by The Information Network, a New Tripoli, Pennsylvania-based market research company.

Micronic aquires direct write license for semiconductor applications

Mon, 12 Dec 2000
Sweden--Micronic Laser Systems AB, a developer of semiconductor and display laser pattern generators for the production of photomasks to worldwide electronic industries, today announced that it has extended its partnership with Fraunhofer Institute for Microelectronic Circuits and Systems (IMS) to include all semiconductor direct write applications based on Micronic's use of the spatial light modulator (SLM) technology.

Consortium Targets Debugging of Advanced Device Designs

Thu, 9 Sep 2000
San Jose, California--Sept. 28, 2000--International SEMATECH, a consortium of semiconductor manufacturers, has chosen Knights Technology, a division of Electroglas, Inc., to commercially develop an advanced software tool for locating the physical origins of faults in integrated random-logic circuits.

UMC and Dai Nippon Printing enter long-term photomask supply, development agreements

Tue, 12 Dec 2000
Hsinchu, Taiwan--United Microelectronics Corp. (UMC), a leader in the semiconductor foundry industry, and Dai Nippon Printing Co., Ltd. (DNP), a leader in photomask manufacturing, have announced the finalization of a multi-year agreement for UMC to secure advanced mask services from DNP. The agreement also includes a joint specification optimization effort for masks at the 0.10-micron generation, generally considered to be the next major milestone in semiconductor process technologies.