Compugraphics International is widening its line of photomasks to include larger-area products up to 16 in2, responding to customer demand for wafer-level packaging and other semiconductor and optical applications.
The Unifire 7900IR provides 3D inspection of wafer-scale packaging features as well as registration for wafer-to-wafer bonding applications for use in advanced wafer scale packaging process control.
CEA-Leti, in a multi-partner project with SET, STMicroelectronics, ALES and CNRS-CEMES, will demonstrate high-alignment-accuracy chip-to-wafer structures made by direct metallic bonding. Such structures are required for high-performance 3D ICs, and possibly microelectronics, optoelectronics, or MEMS.
Haruo Matsuno, president and CEO of Advantest Corporation (TSE:6857, NYSE:ATE) shares the company's major goals, including expansion into new measurement applications, utilization of cloud computing, and more.
All the major semiconductor players are embracing 3D integration, says Simon Deleonibus. The CEA-Leti scientist and IEEE Fellow wants to see TSV mature and new technologies develop based on wafer bonding. He speaks with Debra Vogler.
Ushio Inc. debuted a 200mm wafer full-field projection lithography tool UX4-3Di FFPL 200 for high-volume manufacturing of advanced LSI devices incorporating 3D integration technologies, such as TSVs and silicon interposers and bumps.
CEA-Leti has installed multiple EVG tools in its 300-mm cleanroom dedicated to R&D and prototyping for 3D integration applications. EVG's equipment will be used in 3D technology demonstrations for Leti's global customer base, as well as low-volume pilot production on 300mm wafers.
LORD Corporation launched the ME-555 underfill encapsulant for semiconductor packaging and assembly. LORD ME-555 is a high-purity, semiconductor-grade epoxy underfill for encapsulating flip chips.
STATS ChipPAC says integrating through-silicon vias with passive devices and its eWLB technology addresses complex design issues, shrinking lithography nodes, and increased performance demands for mobile and consumer applications.
Jae-Woong Nah, researcher at IBM's Thomas J. Watson Research Center, briefed ElectroIQ on his IMAPS conference paper: "Mask and mask-less injection molded solder (IMS) technology for fine-pitch substrate bumping." IMS is a variation of C4NP for solder deposition on fine-pitch laminates. Nah explains how the researchers injected 100% pure molten solder instead of solder paste with a reusable film mask for forming high-volume solder on fine-pitch substrates.
The VectorGuard stencil portfolio from DEK now includes the double layer Platinum stencil, a stencil technology that is said to offer performance benefits over conventional screens. VectorGuard Double Layer Platinum stencils suit semiconductor applications and component manufacture, solar cell manufacture, low-temperature co-fired ceramic (LTCC) manufacture, as well as other production challenges requiring fine line or mixed feature sizes.
The Surface Mount Technology Association (SMTA) will host two 90-minute online sessions with Bob Willis, ASKbobwillis.com, on package-on-package (PoP) applications and implementation. The Webtorials will take place February 4 and February 11, 2010 from 1:00 to 2:30 pm EST.
USHIO Inc. is introducing the large-field stepper lithography tool
CEA-Leti and Replisaurus Technologies will begin applying Replisaurus' ElectroChemical Pattern Replication (ECPR) metallization process to customer target products, following a near-100% yield master.
Canon Inc. made its first foray into the semiconductor back-end packaging equipment market with the new FPA-5510iV for through silicon via (TSV) and bump lithography.
A standing-room crowd gathered at SEMI for a special NCCAVS usergroup meeting to hear about issues relevant to 3D packaging, including CMP for through-silicon vias (TSV), a DFM methodology for 3D TSV packaging designs, and TSV process integration challenges.
Süss MicroTec's Stojan Kanev tells SST/AP about the company's new addition to its toolset for 3D integration: a probe station targeting 300mm wafer-level 3D stacked structures.
Infinite Graphics Incorporated (IGI) debuted the IGI Phototooling Toolbox for niche applications with specialized requirements not addressed by traditional mainstream PCB and IC products.
Ultratech, lithography and laser-processing system supplier to semiconductor manufacturers and packaging providers, added Michael C. Child to its Board of Directors. Child served on Ultratech
SUSS MicroTec has acquired Tamarack Scientific Co. Inc. in a share purchase of $9.34 million. Tamarack makes UV projection lithography tools and laser micro-structuring systems.
Intel, SEMATECH, and other top chip makers, suppliers, and research organizations will send speakers to SEMICON West, July 10-12 in San Francisco. The event will single out new transistor architectures, advanced lithography, 450mm wafers, and other major developments.
Himax Technologies placed a repeat order for an IQ Aligner UV nanoimprint lithography (UV-NIL) system from EVG.
At the recent Common Platform Technology Forum -- produced by Global Foundries, Samsung and IBM -- Simon Segars, executive vice president and general manager of the physical IP division at ARM, spoke about the impact of the internet of things and mobile computing on the way electronics are designed and used.
The 2011 International Technology Roadmap for Semiconductors (ITRS) has been publicly released. Several areas of advancement are highlighted in the 2011 ITRS: DRAM and Flash memory, and MEMS.
The electronics industry will edge out coal-fired boilers as the biggest purchaser of ultrapure water systems and consumables in 2012, according to the McIlvaine report: Ultrapure Water World Markets.
EVG uncrated the EVG620HBL Gen II fully automated mask alignment system for volume LED manufacturing. The second generation tool offers 55% higher wafer output per square meter of cleanroom space occupied, EVG reports.
Worldwide silicon wafer revenues improved 2% YOY, shows the SEMI Silicon Manufacturers Group. Worldwide silicon wafer area shipments, however, decreased 3%, indicating a loss of momentum in H2 2011, said Kazuyo Heinink, SEMI SMG.
Gigaphoton uncrated the GT63A next-generation ArF excimer laser for multi-patterning immersion lithography scanners.
James Word and Christian Zunia, Mentor Graphics, explore the current capabilities of model-based OPC software to model and correct for the shadowing distortions unique to extreme ultra-violet lithography (EUVL).
VLSIresearch released its 2011 Top Semiconductor Equipment suppliers rankings, noting important acquisitions and strong spending in lithography tools in 2011. Semiconductor equipment spending was driven by aggressive capacity expansion in the foundry and logic sectors.
Execs from Samsung, IBM, GlobalFoundries and ARM looked to the future at The Common Technology Platform Forum in Santa Clara. They focused on the innovation pipeline for 20nm and 14nm technology nodes, and the role that EUV, FinFETs, TSVs, CNTs and DSA will play.
Worldwide sales of semiconductor manufacturing equipment totaled $43.53 billion in 2011, representing a year-over-year increase of 9%, shows SEMI. North America surpassed Taiwan as the region with the highest amount of spending.
Barclays Capital compiled its 2011 analysis of semiconductor wafer fab equipment (WFE) spending, with a look at the top players and underlying trends by process step.
Barclays Capital compiled its 2011 analysis of semiconductor wafer fab equipment spending, with a look at the top players and underlying trends by process step. Here, Barclays’ CJ Muse considers lithography’s current state and future.
Barclays Capital looks at wafer fab equipment trends in 2011, based on Gartner data. Top 5 takeaways? The top 5 vendors continue to gain market share, Intel is a key customer, segment-leading vendors strengthened their holds, intensity edged higher, and changes are in store in 2012.
The Optical Systems Division of Zygo Corporation recorded a $2+ million order from a major semiconductor manufacturer to produce EUV optics for advanced lithography.
Osaka University’s Photonics Advanced Research Center in Japan installed a NanoInk NanoFabrication Systems DPN 5000 System for patterning various materials with nanoscale accuracy and precision. Osaka University scientists will develop and fabricate nanoscale plasmonic and nanophotonics devices.
North America-based manufacturers of semiconductor equipment posted $1.16 billion in orders in December 2011, $1.32 billion in billings, and a book-to-bill ratio of 0.88, according to SEMI. The book-to-bill ratio has been climbing since September 2011. In December, bookings climbed back above the $1 billion mark.
IMS Nanofabrication, Dai Nippon Printing Co., Ltd. (DNP), Intel Corporation, and Photronics Inc. are commencing a joint electron multi‐beam mask writer tool collaboration.
Intel plans $12.5 billion semiconductor capital expeditures in 2012; Samsung plans $12.2 billion. Watch for wide and growing separation between these two companies and their competition, says IC Insights.
Researchers at INCDTIM in Romania will use NanoInk's NanoFabrication Systems Division's DPN 5000 system for supramolecular structure fabrication, molecular recognition and self-assembling process applications.
Michael A. Fury, Ph.D., Techcet Group, reports from SEMI’s International Semiconductor Strategy meeting, with a closing day focused on innovation and new applications.
36% of semiconductor fabs are in high-risk zones, finds Semico, noting the industry disruptions caused by the Japan earthquake and tsunami and Thai flooding and the challenges these presented to chip makers in the regions.
Day 2 of SEMI’s Industry Strategy Symposium (ISS) 2012 included talks by Mike Splinter of Applied Materials, Mark Thirsk of Linx Consulting, Tim Hendry of Intel, David Lazovsky of Intermolecular, a panel session on could computing run by Harvey Frye of TEL, Handel Jones of IBS and another panel session focused on 450mm, moderated by G. Dan Hutcheson of VLSI Research. Michael A. Fury of Techcet reports.
After attending SPIE Advanced Lithography, Barclays Capital came away with a lower lithography tool shipments forecast, more hope for EUV lithography, and expectations of a litho buying spree at Intel.
Brewer Science uncrated the next generation of its OptiStack system of patterning products for semiconductor manufacturing, targeting emerging and existing lithography processes.
Tokyo Electron Ltd. (TEL) will join research organization CEA-Leti's IMAGINE open, collaborative industrial program on advanced lithography for semiconductor manufacturing.
RAVE N.P. Inc. established a new division, Advanced Technical Instruments or ATI, comprising SEM, AFM, and other analysis tools, as well as custom semiconductor and photomask services such as haze generation systems.
Lithography light source maker Gigaphoton, Inc. achieved 7W of extreme ultra violet (EUV) power on its mass-production laser-produced plasma (LPP) light source, scheduled to be shipped in 2012.
Pixelligent and Brewer Science Inc. developed a spin-on hardmask technology for advanced lithography, combining nanocrystal and microelectronic coating technologies.
The eBeam Initiative, a forum for new IC manufacturing approaches based on electron beam (e-beam) lithography, will unveil its latest roadmap at the SPIE Advanced Lithography Symposium.
ASML's Brion Technologies debuted Tachyon Flexible Mask Optimization, which enables use of multiple OPC techniques in a single mask tapeout for 2Xnm lithography.
CEA-Leti reports that the MAPPER Lithography massively parallel direct write technology resolves 22nm dense lines and spaces and 22nm dense contact holes in positive chemically amplified resist. The maskless lithography tech meets semiconductor requirements for 14nm and 10nm logic nodes.
imec successfully implemented a 300mm directed self-assembly (DSA) semiconductor manufacturing process line in its fab, with TEL equipment, AZ Electronic Materials consummables, and research from the University of Wisconsin.
The Industry Strategy Symposium (ISS) kicked off today in Half Moon Bay, CA under blustery skies with choppy seas, an apt metaphor for the information about to be shared inside, says blogger Michael A. Fury, Techcet.
Taiwan became the region with the largest share of installed wafer capacity in 2011, according to IC Insights' Global Wafer Capacity 2011-12 report. This is the first time Taiwan has led the global wafer capacity rankings, with 21% of total in mid-2011.
Wuhan National Laboratory for Optoelectronics at the Huazhong University of Science and Technology (Wuhan, China) has signed off its Vistec Lithography electron-beam lithography system Vistec EBPG5000pES.
Semiconductor sales were weaker than expected in Q3 2011, and Q4 shows weak guidance, prompting chip makers to reduce production. Gartner expects this inventory correction to work out in early 2012.
Former SEMI president and CEO Stanley T. Myers was named a director emeritus of the association by itsl Board of Directors. Myers led SEMI for 15 years, was a board member for 24, and has been part of the semiconductor industry for more than 50.
Key points from SEMI's 2012 semiconductor fab equipment spending forecast include a predicted decline of 11% to $35 billion, steady growth in 300mm installs, and an H1 dip/H2 surge format.
EV Group signed a joint-development and licensing agreement with Eulitha AG, integrating Eulitha's PHABLE mask-based UV photolithography technology with EVG's automated mask aligner platform.
20nm production will be done with 193nm ArF immersion lithography. The workhorse lithography technologies will be double-patterning, source mask optimization, or some combination of the two, says Franklin Kalk, Toppan Photomasks.
Solid State Technology asked top analysts and technologists to provide insights on the transition to 22nm semiconductor devices. Read through the whole 10-forecast series, or check out the individual articles as you have time to see perspectives on lithography, device architecture, and more.
The global semiconductor market will see a slow 2012, reports IHS, with economic uncertainty and semiconductor inventory not moving enough to stimulate new production. Expect negative growth in Q1 2012, a nascent rebound in Q2, and strong growth in Q3 2012, IHS reports.
Texas Instruments (TI, NASDAQ:TXN) will close 2 older semiconductor manufacturing facilities in Hiji, Japan and Houston, TX over the course of the next 18 months. Production from these analog chip sites will be moved to more advanced TI facilities.
President Barack Obama visited the Intel Ocotillo campus in Chandler, AZ. The President spoke about Intel's technological innovation, and manufacturing jobs in America.
ABB Robotics introduced an ISO 5 (Class 100) Cleanroom version of the IRB 120, its smallest multipurpose 6-axis robot. Any source materials in the IRB 120 prone to particle generation were modified to eliminate contamination potential in the manufacturing area.
Vistec Electron Beam GmbH sold a Variable Shaped Beam system SB251 to the Institute of Electronic Materials Technology in Warsaw, Poland, for R&D on micro-optical and diffractive elements, new materials, and masks for optical lithography.
Carl Zeiss won orders for its EUVL actinic aerial image metrology system, AIMS EUV, from 2 of the 4 members of SEMATECH’s EMI partnership. The tool allows chip makers to review defects in advanced masks needed for EUVL.
Inpria, chemical materials supplier for thin-film deposition, joined the consortium SEMATECH’s Lithography Program. Inpria and SEMATECH will tackle on critical issues for resist in extreme ultraviolet (EUV) lithography.
Strong lithography spending, as well as several acquisitions and divestures in the space, brought changes to the critical subsystems of semiconductor/related markets sector, says VLSIresearch.
With a book-to-bill ratio of 1.13, North America-based manufacturers of semiconductor equipment saw a sixth climb in the ratio, which has steadily improved since it hit 0.71 in September 2011, shows SEMI.
The 23rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2012) will be held May 15-17 in Saratoga Springs, New York. The conference will feature presentations of more than 85 peer-reviewed manuscripts covering critical process technologies and fab productivity. This year’s event features a panel discussion on “Competing for R&D Dollars,” moderated by Solid State Technology Editor-in-Chief Pete Singer.
Barclays Capital is raising its total lithography units forecast by more than 10 systems, from 234 to 251 in 2012. As many as 260 litho tools could be purchased, as foundries are seeing high demand for 28nm chips.
The eBeam Initiative will present at Photomask Japan (PMJ), through member companies, improved photomask critical dimension uniformity (CDU) and wafer yields thanks to eBeam technologies.
Entegris (NASDAQ:ENTG), contamination control and handling system supplier to the semiconductor and microelectronics industries, will build the Entegris i2M Center for Advanced Materials Science in Bedford, MA, near its headquarters in Billerica. i2M denotes ideas to market.
Intel Corporation announced its 2011 Intel Preferred Quality Supplier (PQS) awards, selecting 19 of its thousands of suppliers. Two suppliers received Intel’s Achievement Award.
Wright Williams & Kelly, Inc. (WWK) opened its 2012 semiconductor industry survey on equipment and process timing. Only participants will receive the full results, free of charge.
IC manufacturers closed 49 wafer fabs between 2009 and 2011, according to IC Insights. Smaller wafer fabs (≤200mm) suffered the most closures, and Japan and North America led the way.
President Barack Obama toured the SUNY - Albany Nano-Tech Complex today, speaking about the economy and education in the CNSE NanoFab Extension Building.
The Heterogeneous Technology Alliance in Europe is focusing on high-performance organic electronic circuits through 2 projects: COSMIC to develop p- and n-type OTFTs for complementary logic, and POLARIC for shrinking critical dimensions of OTFTs.
Gigaphoton Inc., lithography light source manufacturer, began operations at its wholly owned subsidiary, Gigaphoton Korea Inc. Gigaphoton points to Korea as “one of the most important regions in the global semiconductor industry.”
SENSIRION introduced the SLQ-QT105 semiconductor-grade flow sensor for flow rates below 2cc/sec (120ml/min) of hydrocarbon-based liquids, such as photoresists and solvents.
Arkema and CEA-Leti, with the help of Professor Hadziioannou’s team of LCPO, have successfully patterned a 20nm pitch and reduced the diameter of contacts down to 7nm with nanostructured polymers.
North America-based manufacturers of semiconductor equipment posted $1.18 billion in orders, $1.24 billion in billings, and a book-to-bill of 0.95 in January 2012, according to SEMI.
SEMI’s International Strategy Symposium (ISS) meets for its Europe session February 26-28 in Munich, Germany. Following are some of the 450mm wafer presentations scheduled to take place.
SUSS MicroTec will work with GenISys, provider of high-performance software solutions for nano scale fabrication, to combine the SUSS MicroTec mask aligner tools with the GenISys simulation software Layout LAB.
Dr. Vivek Bakshi, President of EUV Litho, Inc., reports on the SPIE Advanced Lithography conference. He says that this year even the loudest criticism of EUVL was not about “if” but “when,” and the predicted range of insertion for EUVL in high volume manufacturing (HVM) is now 2013-15.
GLOBALFOUNDRIES appointed Magnus Matthiasson, formerly of Philips Lumileds, as chief procurement officer (CPO), reporting to CFO Dan Durn.
North America-based manufacturers of semiconductor fab equipment posted $1.60 billion in orders and $1.45 billion in billings in April 2012 for a book-to-bill ratio of 1.10, according to SEMI.
Indian River State College in FL will be the first college in the southeastern US to offer students access to the instrumentation and curriculum provided by the NanoProfessor Nanoscience Education Program from NanoInk.
Stefan Wurm, director of lithography, SEMATECH will present “EUV Lithography Manufacturing Introduction: Infrastructure Readiness” in the session Technology Trends in Semiconductor Manufacturing at The ConFab 2012, June 3-6 in Las Vegas.
The Dow Chemical Company (NYSE: DOW) inaugurated its Dow Seoul Technology Center, a global R&D center with focus on technological advances in display and semiconductor applications.
Lithography light source maker Gigaphoton Inc. opened its new U.S. Regional Headquarters and Training Center in Beaverton, OR.
Gudeng Precision will use VICTREX PEEK-ESD 101 to make its first commercialized extreme ultraviolet (EUV) lithography pod. The material will help prevent contamination.
Worldwide semiconductor manufacturing equipment spending is projected to total $38.9 billion in 2012, an 11.6% decline from 2011 spending of $44 billion, according to Gartner Inc.
CEA-Leti has introduced the “LETI-3S” concept, for “Silicon Specialty Solutions.” The research is oriented to start-ups, component integrators, fabless or fablite chip companies, and equipment/consumable suppliers.
Solid State Technology and SEMI will present the 2012 Best of West product awards at SEMICON West 2012, July 10-12 in San Francisco. Best of West recognizes important product and technology developments in the microelectronics industries.
CEA will extend its collaboration with Arkema beyond photovoltaics into microelectronics and organic electronics, setting up two joint public-private research projects in CEA-Leti and CEA-Liten.
Photronics, Inc. (NASDAQ:PLAB) purchased its US nanoFab building from Micron Technology Inc., paying approximately $35 million. PLAB expects to save $5 million annually after the deal.
Ventex performed a major deep ultra violet (DUV) lithography stepper refurbishment and installation project for a tier-one chip manufacturer in Germany.
Semiconductor fab equipment spending will remain flat in 2012, says SEMI. But look for a record spend from semiconductor makers in 2013, jumping from $38.85 billion spent in 2012 to $45 billion in 2013.
After only 2 months, semiconductor foundries are already considering raising their 2012 capex budgets, says Terence Whalen, Semiconductor Equipment analyst for North America at Citi.
A group of partners in Europe summarize results from their completed project to deliver the first EUV lithography optics, with progress in several optics components and in mask handling, cleaning, and repair.
In case anyone needed a reminder or a wake-up, new data from SEMI reiterates chip tool sales are slumping badly in the latter part of this year.
In the fifth installment in a series called Process Watch, the authors discuss the need for proper reticle cleaning and inspection. Authored by experts at KLA-Tencor, Process Watch articles focus on novel process control solutions.
At SEMICON Europa, European government representatives, consortia, and suppliers discussed programs to support and participate in the 450mm wafer-size transition -- including a comprehensive presentation from ASML about its roadmap for 450mm EUV platforms.
Pulling Cymer's EUV source technology in-house is hoped to accelerate progress in the technology's long slow march toward production readiness.
Intel spoke of caution in end markets when discussing its 3Q12 results, but a big dip in capex and lack of 2013 visibility will likely cause concern in the semiconductor manufacturing ecosystem.
SEMI has extended the deadline to submit proposed papers to next spring's China Semiconductor Technology International Conference 2013, and added a new symposium on circuit design, system integration, and application.
In the seventh installment in a series called Process Watch, the authors discuss cycle time and the impact of inspection. Authored by experts at KLA-Tencor, Process Watch articles focus on novel process control solutions.
With this week's IEEE International Electron Devices Meeting (IEDM 2012) now underway, here are four of the papers that were accepted late: on 90nm integrated silicon photonics, ZnNO for next-gen displays, and III-V TFETs for the 7nm node.
Semiconductor equipment demand is persistently sluggish as the industry takes a break from a "multiyear expansion period" to digest recent investments and wrestle with a broader economic slowdown, acknowledges SEMI in its updated year-end forecast. But make no mistake: leading-edge technology investments are still happening, and growth will return in the typical cyclical pattern.
In news from Semicon Japan, a Nikon spokesperson said that the company plans to ship high-volume manufacturing (HVM) lithography tools in 2017, and Intel officially announced a 450mm Japan Metrology Center.
Swiss firm Adlyte, a developer of high-brightness laser-produced plasma (LPP) EUV light source for actinic mask inspection, is outlining its current expansion efforts, which includes appointing a longtime industry exec to its strategic advisory board.
EV Group has completed its expanded cleanroom IV facility at its corporate headquarters in Austria, which doubled its cleanroom space for process development and pilot production services.
A reference book from the Global Semiconductor Alliance (GSA) and IC Insights puts foundry information at the fingertips of those who need it the most.
The latest monthly numbers for semiconductor manufacturing equipment demand aren't pretty: lows in both orders and sales not seen since the last major downcycle three years ago, and the short-term comparisons continue to widen.
Industry watchers have been lowering their outlooks for 2013 over the past few weeks, but there's one set of opinions that still see optimism for an industry rebound in 2013 -- chip industry executives themselves.
Nikon and the Singapore A*STAR IME are jointly setting up a R&D lab to develop optical ArF lithography technology for semiconductor manufacturing to and below the 20nm device node.
Global spending on wafer fab equipment (WFE) is now on pace to finish 2012 with a -17% annual decline, and 2013 now looks like it'll only be slightly better at a -10% dropoff, before the next cyclical spending upturn begins in 2014, according to an updated forecast from Gartner.
Samsung's reaffirmation of its planned $4B investments in its Austin, TX facilities don't offer much extra info, but do serve as a message to the market about its future plans -- with or without Apple.
The Annual SPIE/BACUS Symposium, serving the worldwide photomask industry, will take place September 10-14, with the theme of successful integration and optimization of design, mask-making, and wafer fabrication in the deep sub-wavelength era.
TSMC took a 5% stake in ASML, worth EUR 838 million, as part of the ASML Holding N.V. Customer Co-Investment Program to accelerate development of EUV lithography and 450mm wafer processing. TSMC will also commit EUR 276 million to ASML’s R&D programs.
Germany has launched a new project, EUV projection optics for 14nm resolution, or ETIK, led by Carl Zeiss and 6 other German companies and research institutes. The aim is to improve extreme ultraviolet (EUV) lithography resolution to the 14nm node.
The ConFab, Solid State Technology’s invitation-only event for the semiconductor industry, took place in June, with presenters from top companies and analyst firms. If you couldn’t be there, check out all the coverage from the event -- reports, presentations, video interviews and more.
Crossing Automation, Inc. announced three new options for the Spartan 300 that deliver an end-to-end contamination-free sorter environment. The new options target high volume manufacturing at 32nm and below.
Solid State Technology and SEMI today announced the finalists for the 2012 “Best of West” awards, recognizing important product and technology developments in the microelectronics supply chain.
DFMSim announced a distribution agreement with a leading US process control OEM that involves the integration of DFMSim’s SMARTlitho manufacturing software into new tools for advanced metrology.
Barclays Capital checks in on the EUV lithography market potential and which semiconductor manufacturers will press adoption. The analysts also update their expectations for lithography tool suppliers on the EUV front.
SEMICON West is taking place July 10-12 in San Francisco, CA. Following are new products for lithography, including photoresist coaters and ashers.
North-America-based manufacturers of semiconductor fab equipment posted $1.61 billion in orders worldwide in May 2012, $1.54 billion in billings, and a 1.05 book-to-bill ratio, shows SEMI.
The Semiconductor Industry Association (SIA) presented its 2012 University Researcher Awards to Stanford University professors Krishna Saraswat and Bruce Wooley as well as its 2012 Congressional Leadership Awards to Sen. Carl Levin, Sen. John McCain, Rep. Kevin Brady and Rep. Wally Herger.
At the recently concluded 2012 EUVL Workshop (held June 4-8 in Maui, HI), attendees shared their latest technology developments and discussed ways to address the challenges of EUVL insertion into high-volume manufacturing (HVM).
Maxim is spending $200 million to upgrade and expand its US semiconductor manufacturing facilities in San Antonio and Dallas, TX; Beaverton, OR; and San Jose, CA. Maxim manufactures about 50% of its products in the US.
Semiconductor manufacturers identified key factory productivity challenges that need to be addressed and shared effective solutions they will need to stay leading-edge and competitive amid turbulent industry transitions during the recent ISMI Manufacturing Week.
SEMICON West kicked off with a surprise announcement regarding Intel's investment in ASML, but generally the event highlighted trends “as expected” in the fab supply chain, say Barclays analysts.
Cymer is seeing adoption of its focus drilling technology for ArF immersion light sources and SmartPulse data management tool for light source performance monitoring, both introduced in 2011.
The overriding message for 2012 is that the roadmap has been largely
stabilized with the significant changes that were input last year in the
2012 publication,” said Intel’s Alan Allan, speaking at Semicon West.
Newport Corporation introduced a line of high-performance air bearing stages specifically designed for the 450mm semiconductor wafer initiative.
Barclays Capital is seeing various reasons for a Q3 2012 semiconductor fab order/shipment pull-back, following meetings around SEMICON West 2012. The analysts expect strong orders in Q4.
After meeting with various semiconductor manufacturing tool suppliers -- Applied Materials, KLA-Tencor, Lam Research, Tokyo Electron, Teradyne and Cymer -- at SEMICON West, Citi analysts share impressions on foundry spending plans and tool choices.
Sanjay Rajguru, director of ISMI, will present “Tool Obsolescence and the Impact on 200mm Manufacturing” at The ConFab 2012’s final session, Maximizing the Longevity of Investments.
Dr. Vivek Bakshi blogs about trends he expect to see at the upcoming 2012 International Workshop on EUV Lithography, in Maui Hawaii.
Stanford University researchers, sponsored by Semiconductor Research Corporation (SRC), have created contact hole patterns for logic and memory semiconductors using a next-generation directed self-assembly (DSA) lithography process.
Mike Fury reports on Day 2 of the 15th IITC (International Interconnect Technology Conference), from San Jose, CA.
At The ConFab 2012, fabless companies and foundries have a common goal: reduce power, increase performance and reduce price (not necessarily in that order).
Naoya Hayashi, research fellow for electronic device operations at Dai Nippon Printing, speaks with Solid State Technology chief editor Pete Singer during The ConFab 2012. Hayashi presented “NGL Mask Readiness” in The ConFab’s session on technology trends.
Chip scaling will go on for the foreseeable future, enabling new product with more compute power, more memory, faster on-chip communication. That was one of the conclusions put forth by imec’s An Steegen, speaking on technology trends at The ConFab 2012.
The 15th IITC (International Interconnect Technology Conference) opened Monday, June 4 at the Doubletree Hotel in San Jose, CA. Recurring themes this year were variations on 3D and TSV, novel systems and packaging, and back end memory. Mike Fury reports.
At The ConFab’s opening session, “The Economic Outlook for the Semiconductor Industry,” capex was a major point of interest. Jackie Sturm of Intel, Dan Hutcheson of VLSIresearch, and Jim Feldhan of Semico all touched on it, with Hutcheson expanding on the idea of capex trends to present an entire ecosystem of semiconductor business management.
Cymer presented at Barclays Capital’s TMT Conference, providing information on semiconductor makers’ transition from deep ultra violet (DUV) to extreme ultraviolet (EUV) lithography, pre-pulse technology demonstrations, and more.
At imec's International Technology Forum, An Steegen, Senior Vice President Process Technology at imec, discusses the three technology knobs that are key for a further system scaling.
At imec's International Technology Forum, the research consortium's CEO, Lec van den Hove, draws attention to the need for the industry to solve the world's health problems.
At imec's International Technology Forum, Greg Bartlett, CTO of GLOBALFOUNDRIES, said the key to survival in the semiconductor industry is adaptability and collaboration.
THE BEST rankings from VLSIresearch identify the highest-rated suppliers of wafer processing, assembly, and test equipment. Check out the top-rated suppliers of wafer processing equipment, by company size and customer ranking.
VLSIresearch polled semiconductor manufacturers about their tool suppliers, asking chipmakers to rank equipment providers on customer satisfaction. This year’s results show renewed focus on fab needs.
Blogger Michael A. Fury, Ph.D., Techcet Group, reports on Day 2 of SEMICON West with insights from the Sokudo Lithography Forum and NCCAVS CMPUG meeting, and -- sadly -- none on SEMICON West’s Happy Hour.
Barclays Capital analysts share observations from meetings with semiconductor manufacturing tool suppliers at SEMICON West, noting the enthusiasm and concrete deals around EUV lithography and transitioning to the 450mm wafer size.
Luc Van den hove, president and CEO, imec, spoke with Solid State Technology, covering imec’s major announcements and research presentations to take place during SEMICON West 2012.
ATMI introduced BrightPak, its next-generation liquid containment and delivery system for high-value liquid material transfers during advanced photolithography processes in semiconductor, FPD, and LED manufacturing.
Semiconductor equipment sales will reach $42.4 billion in 2012, according to the mid-year edition of the SEMI Capital Equipment Forecast, released at SEMICON West 2012.
Michael A. Fury, Ph.D., reports from the pre-opening day (July 9) of SEMICON West at the Moscone Center in San Francisco, CA. The first day hosts SEMI’s press conference on semiconductor revenues and the SEMI/Gartner Market Symposium.
ASML established a program to enable its largest customers to make minority equity investments in the semiconductor manufacturing tool maker. The program includes commitments to fund ASML's R&D spending, accelerating development of EUVL and 450mm technology for 2015-2020 timeframe.
Following are some of the new and flagship products that will appear this week at SEMICON West, July 10-12 in the Moscone Center of San Francisco, CA.
Gigaphoton Inc. will uncrate “s” series hardware and software products in Q3 2012, enhancing lithography exposure performance and reducing operating costs and downtime of the GT6xA ArF excimer laser series for multi-pattern immersion lithography scanners.
We at Solid State Technology have compiled the best conference reports so far this year, in the lead up to SEMICON West 2012, next week in San Francisco.
Gigaphoton Inc. reached a maximum of 5.2% EUV coversion efficiency (CE), beating the semiconductor manufacturing industry’s target of 5.0% for a first-generation EUV lithography scanner. These data show an average of 4.7% CE.
Dr. Vivek Bakshi blogs about an upcoming SPIE journal, the Journal of Micro/Nanolithography, MEMS, and MOEMS (JM3), which has a focus on EUV sources.
In the second installment in a series called Process Watch, the author provides tips on how to make sure you’re reviewing the yield killing defects and not wasting time reviewing nuisance events. Authored by experts at KLA-Tencor, Process Watch articles focus on novel process control solutions for chip manufacturing at the leading edge.
Speaking at The ConFab 2012, Sanjay Rajguru, director of ISMI, pointed out that more than half the current fab capacity today comes from facilities that are more than ten years old, which is creating a problem with equipment obsolescence.
Tom Jefferson, G450 Consortium, shares an update on 450mm wafers for semiconductor manufacturing. The consortium is adding staff and ramping its silicon supply, and getting ready for equipment selection.
Bill Tobey, president of ACT International Consulting, speaks about the evolution of extreme ultra violet (EUV) lithography at The ConFab 2012.
Bill Ross, ISMI, is moderating a session today at The ConFab 2012 on managing legacy semiconductor fabs and dealing with tool and materials obsolescence at 200mm and smaller. He speaks with Pete Singer about coping with these changes.
Fab equipment spending has improved in 2012, breaking the barrier into positive growth for the year, shows SEMI. Semiconductor makers will invest $39.5 billion in fabs, up 2% from 2011 spending. Fab capex will hit a record in 2013, $46.3 billion or 17% above 2012.
Optomec’s Aerosol Jet deposition tools are being used for printed sensor, display, solar cell, CMOS and passive devices, and other development areas, with new installations at CEA Liten (France), Innovation Lab (Germany) and the University of Sheffield (UK).
SEMI recently conducted a survey of semiconductor fab equipment and materials suppliers, finding that 60+% of respondents say that IP challenges have had an adverse impact on their companies.
RED Equipment’s Carl McMahon suggests a different model for handling secondary semiconductor equipment for greater efficiency, cost reduction and quality control: full turnkey services engineered to the fab’s needs without the expense of customization.
Rudolph Technologies Inc. (NASDAQ:RTEC) acquired the assets of NanoPhotonics GmbH, adding inspection technology and an intellectual property (IP) portfolio to serve its advanced package inspection tool customers.
The 2012 TechConnect World Summit, Expo & Showcase opened Tuesday, June 19, 2012 at the Santa Clara Convention Center. The event serves as host to the National Innovation Showcase, whose mission is to accelerate the commercialization of “the world’s top innovations.”
Canon U.S.A. Inc. introduced the FPA-6300ES6a DUV stepping scanner, a lithography tool with a KrF excimer laser light source for the high-volume production of memory, logic and image-processing devices.
Older production facilities face equipment obsolescence; skills obsolescence; scarce availability of parts, software, and support; and equipment capability extension and tool re-use. At the ConFab 2012 Executive Roundtable, representatives from Sematech/ISMI, IDMs, OEMs, equipment dealers, and industry consultants gathered to have an open discussion on concerns, roadblocks, and possible solutions.
Semiconductor manufacturing equipment billings and bookings were virtually tied in Q1 2012, reports SEMI, with $10.61 billion in billings and $10.07 in bookings. This is a 13-14% improvement sequentially, and 9% below the same quarter last year.
As the dust settles after the launch of the iPhone 5, analysts tally which suppliers in the semiconductor ecosphere are most likely to gain the most.
Global demand for semiconductor manufacturing equipment slipped -4% in 2Q12 with softness in just about every region -- except Taiwan which stepped on the pedal during the quarter, according to updated data from SEMI and SEAJ.
A team led by University of Toronto physicists has developed a simple new technique using Scotch poster tape that has enabled them to induce high-temperature superconductivity in a semiconducto.
Semiconductor Research Corporation (SRC) recognized two outstanding professors in SRC-supported, chip-related research and education for 2012.
Analysts weigh the reasons behind Intel's downwardly-revised 3Q12 results, from macroeconomic sluggishness to tablet-PC cannibalization -- and whether its pullback in 2012 capex plans spells trouble for the market overall.
While various industry segments appear to be tapping the brakes, others are revving their engines, observes SEMI's Christian Gregor Dieseldorff -- and a 2012 stall could pave the way for a record-breaking 2013.
Spending on R&D by semiconductor companies worldwide is expected to grow 10% in 2012 to a record $53.4 billion, as companies all across the ecosystem try to keep up with more complex IC designs and new process technologies, according to data from IC Insights.
Laser nanofabrication can now meet the needs of submicron and nanoscale feature size manufacturing, and can operate in air, vacuum, or liquid processes. Sister publication Industrial Laser Solutions recently published Laser nanofabrication: A route toward next-generation mass production.
In this SEMI News and Views blog, Karen Savala covers EUV lithography, 450mm wafers, and 3D IC developments, based on her recent presentation at SEMICON West, “Supply Chain Readiness in an Era of Accelerated Change.”
EUV Symposium host imec and a pair of industry analysts gauge the pace of improvements in EUV lithography and its long march toward production readiness.
Four of the leading micro- and nanoelectronics regions in Europe are joining forces to form a cluster alliance called “Silicon Europe.”
Imec, the research consortium in Leuven, Belgium, plans to start construction of a 450mm pilot line next year, with early production focused on sub-10nm devices starting at the end of 2016.
Learn about the changes in semiconductor manufacturing as well as related markets -- photovoltaics, displays, LEDs, etc -- at the 2012 Strategic Materials Conference (SMC), to be held on October 23-24 in San Jose, CA. SEMI reports.
ASMC 2013, the leading international technical conference for exploring solutions to improve collective microelectronics manufacturing expertise, has issued a call for papers.
"Bookings and billings for North American semiconductor equipment in July are close to values reported exactly one year ago," said Denny McGuirk, SEMI, noting seasonally slow investment activity.
Semiconductor Research Corporation (SRC), a university-research consortium for semiconductors and related technologies, is poised to celebrate its 30th anniversary at its annual TECHCON conference Sept. 10-11.
SEMI's new "450 Central" information portal offers news and perspectives about the 450mm wafer-size transition.
Lithography leader ASML completes its Co-Investment Program, tallying €3.85 billion in equity funds and €1.38B to support R&D into EUV and 450mm.
TSMC joined IMS’s multibeam mask writer development collaboration to develop an electron multi-beam mask writer for use in advanced mask lithography applications, joining founding members DNP, Intel, and Photronics.
SEMATECH researchers have deposited EUV multi-layers with as few as 8 defects per lithography mask, at 50nm sensitivity. The milestone shows that tool-generated defects during multi-layer deposition of mask blanks used for EUV lithography can be reduced enough to enable high-volume manufacturing.
Fab equipment spending continues to soften in 2012, and hopes for a reprieve in 2013 are waning, warns one analyst.
Even though semiconductor manufacturers in Japan are consolidating and transitioning to a "fab-lite" strategy, the region still represents a large installed fab capacity and a major market for equipment and materials suppliers.
Researchers at the U. of Illinois have devised a method to monitor a semiconductor surface as it is etched, in real time, with nanometer precision.
Researchers at Cornell have developed a new laser-based method for ultra-fast anneal of thin photoresist films. The research, sponsored by Semiconductor Research Corporation (SRC), has shown that the new anneal outperforms state-of-art hotplate bake for both 193nm and EUV lithography applications.
Researchers have begun to investigate a new 2D material—molybdenum sulfide (MoS)—which has similar characteristics but offers something graphene doesn’t: a wide energy bandgap, enabling transistors and circuits to be built from it directly.
At the upcoming International Electron Device Meeting, Macronix researchers will describe how they built flash memories that could heal themselves by means of tiny onboard heaters that provide thermal annealing just at the spots where it is needed.
In an invited paper at the International Electron Devices Meeting, researchers from Everspin Technologies will describe how they built the largest functional ST-MRAM circuit ever built, a 64-Mb device with good electrical characteristics.
At the International Electron Devices Meeting (IEDM) in December, a team led by IBM will report on the world’s first high-performance hybrid-channel ETSOI CMOS device.The researchers built a ring oscillator circuit to benchmark performance that worked even better than FinFETs.
In the fourth installment in a series called Process Watch, the authors discuss overlay registration and new capabilities to align to buried layers. Authored by experts at KLA-Tencor, Process Watch articles focus on novel process control solutions.
ProPlus Design Solutions, Inc. unveiled NanoYield, yield prediction and optimization software for memory, logic, analog and digital circuit design.
During sessions at this month's SEMICON Taiwan, execs from TEL, Lam Research, Applied Materials and KLA-Tencor revealed the latest developments in 450mm technology.
Demand for chip tools fell again in August and is off by -30% from its peak in early summer, fulfilling fears that the second half of 2012 will be sluggish for chipmaking investments, according to the latest data from SEMI.
SK Hynix has joined SEMATCH's EUV Mask Infrastructure (EMI) partnership to help develop metrology tools for reviewing defects in advanced masks needed for extreme ultraviolet lithography (EUVL).
At this year’s International Electron Devices Meeting (IEDM), foundry TSMC will describe a heterogeneous epitaxial growth process which for the first time enables Ge to be directly grown on Si.
The first working 3D NAND flash memory at sub-40nm feature sizes will be described by Macronix researchers at this year’s International Electron Devices Meeting (IEDM).
At this year’s IEDM, a team led by Korea’s Gwangju Institute of Science and Technology will detail a high-speed pattern-recognition system comprising CMOS “neurons” and an array of resistive-RAM (RRAM)-based “synapses,” which demonstrated STDP, a brain-like function.
A book-to-bill of 1.08 means that $108 worth of orders were received for every $100 of product billed for the month.
Outlook for semiconductor equipment market improves, but remains soft in the short term.
Through a series of lectures and workshops, SEMATECH will address R&D challenges and closing key infrastructure technology gaps from July 8–12 at SEMICON West in San Francisco, CA.
Rozich, who previously was a member of the company’s board, succeeds Michael R. Polcari, who served as chairman since November 2009.
Total inventory held by semiconductor suppliers declined significantly in the first quarter as excess stockpiles created during the global economic malaise of 2012 were cleared away, done in anticipation of a resurgence in consumer demand for electronic products expected by the second half of 2013.
A team of researchers has found a way to make the manufacture of crystalline silicon materials faster and more affordable.
IBM and United Microelectronics Corporation, a global semiconductor foundry, today announced that UMC will join the IBM Technology Development Alliances as a participant in the group's development of 10nm CMOS process technology.
Much has been said of the 450mm transition. But the description of this inflection is something of a misnomer.
At next week's 50th Design Automation Conference in Austin, Texas, GLOBALFOUNDRIES will unveil a comprehensive set of certified design flows to support its most advanced manufacturing processes.
In advance of the 2013 SEMICON West TechXPOTs on lithography and nonplanar transistors beyond 20nm, SEMI asked some of the speakers and industry experts to comment on the challenges they wanted to highlight. Many of the inputs focused on the need for precision in the processes used to form transistors, as well as how EDA can contribute to mitigating variability.
Fab equipment spending will grow two percent year-over-year (US$ 32.5 billion) for 2013 and about 23 to 27 percent in 2014 ($41 billion) according to the May edition of the SEMI World Fab Forecast.
This year’s SEMICON West front-end processing TechXPOTs on lithography and transistors below 20nm will provide critical updates on how technologists are coping with the next scaling challenges.
Foundry hires former ASML’s Keith Best as director of photolithography; tasked with driving roadmap to 0.15 microns
Just as a boxer avoids a surprise shot to the head or torso by using a “duck and weave” maneuver, so to must front-end technologists confront the challenges associated with extending optical lithography while planning for EUV lithography’s eventual high-productivity solution.
The critical processes and technologies necessary to continue Moore’s Law are currently more uncertain than ever before in the history of advanced semiconductor manufacturing.
More than 100 representatives from government and the photonics industry convened in Washington, D.C., on February 28 to identify focus areas for a national photonics initiative (NPI), engaging academia, industry, and government in a collaboration to address barriers to continued U.S. leadership in photonics.
Over 2,000 industry professionals attended last week’s SPIE Advanced Lithography, where important progress reports were revealed on extreme ultraviolet (EUV), lithography, directed self-assembly (DSA), metrology, and related topics. The event ran February 24-28 in San Jose, California.
Semiconductor technology leaders ST and CMP help universities, research labs and companies prototype next generation of Systems-on-Chip.
Following a healthy expansion in 2012, the growth of the global automotive semiconductor market will decelerate slightly this year because of a slowdown in the aftermarket and portable navigation device (PND) segments.
While investments and capital spending in Asia-Pacific garner much of the attention regarding semiconductor manufacturing, spending on equipment and materials in North America has totaled more than $100 billion over the past decade as leading device manufacturers expand capacity and invest in new facilities.
SRC and NIST will provide a combined $5 million in annual funding for three multi-university research centers tasked with demonstrating non-conventional, low-energy technologies that outperform current technologies on critical applications in 10 years and beyond.
Intel Corporation today took the wraps off its brand new, low-power, high-performance microarchitecture named Silvermont.
Qualcomm, TSMC, and SK Hynix each register greater than 20 percent year-over-year growth.
Samsung Electronics Co., Ltd. today announced the industry’s first production of ultra-high-speed four gigabit (Gb) low power double data rate 3 (LPDDR3) mobile DRAM, which is being produced at a 20nm-class process node.
SEMI today announced that Philip Yeo, chairman of SPRING Singapore, and Lee Kok Choy, country manager of Micron Technology Inc. Singapore, have been voted by the SEMI Singapore Regional Advisory Board as recipients of two prestigious awards recognizing their contributions to the development and success of the Southeast Asian semiconductor industry.
Cadence Design Systems, Inc. announced today that GLOBALFOUNDRIES has collaborated with Cadence to provide pattern classification data for manufacturing processes of 20 and 14 nanometers.
Morgan Advanced Materials has joined SEMATECH’s International SEMATECH Manufacturing Initiative (ISMI), a program designed to improve semiconductor equipment manufacturing productivity, yield, and cost.
Infineon Technologies and GLOBALFOUNDRIES Inc. today announced a joint technology development and production agreement for 40nm embedded flash (eFlash) process technology.
Global macroeconomic developments and technological advances, personal computers, and memory markets are expected to drive demand over the forecast period, Research and Markets predicts in their report, “Global Semiconductor Industry 2012-2017: Trend, Profit and Forecast Analysis.”
Sales in March 2013 were up slightly compared to February 2013 and March 2012.
The semiconductor chip giant revealed plans to branch out beyond PCs. Will it work?
North America-based manufacturers of semiconductor equipment posted $1.14 billion in orders worldwide in March 2013 (three-month average basis) and a book-to-bill ratio of 1.14, according to the March Book-to-Bill Report published today by SEMI.
Error correction code and redundant addresses are both techniques well-known in memories as a way of optimizing yield. But new data from the University of Ferrara shows that these common techniques may be overused. By classifying erratic bits more carefully, it’s possible to use less ECC and up to 35 percent less redundancy.
The ability of a resistive RAM device to maintain its resistance state, otherwise known as retention time, can be impacted by the electrode materials used.
New flash memory chips are replacing the floating gate with thin layers of material that "trap the charge." The charge trap is a sandwich of materials such as silicon-oxide-nitride-oxide-silicon (SONOS), metal-oxide-nitride-oxide-silicon (MONOS) and tantalum-aluminum oxide-nitride-oxide-silicon (TANOS), all of which are substantially smaller than the floating gate.
At the International Reliability Physics Symposium (IRPS), being held April 14-18, 2013 at the Hyatt Regency Monterey Resort & Spa in Monterey, CA, imec will present new research focused on the stress induced breakdown between the tungsten trench local interconnects (M1, M2) and metal gate in a 28nm CMOS technology. Imec’s Thomas Kauerauf will present a paper titled “Reliability of MOL local interconnects.”
New finFETs feature high-k dielectrics, which are better than conventional silicon nitride dielectrics in that they can be thinner, yet still enable good control of the transistor’s channel region from the gate.
It’s well-known that transistors generate heat when they’re operating, and that can have a significant impact on the chip’s reliability and longterm longevity. A small increase of 10°C–15°C in the junction temperature may result in ∼ 2× reduction in the lifespan of the device.
FinFETs offer several advantages compared to traditional planar transistors, but it’s not yet clear what kind of new reliability problems might arise as FinFETs are scaled to smaller dimensions.
Several years ago when the challenges to 450mm wafer processing, EUV development and novel transistor designs were first being discussed, SEMI commissioned a study that predicted the industry could face an R&D funding gap that could exceed $9 billion if current technology and economic trends continue.
In semiconductor manufacturing, 450mm is the next big opportunity. Issues of economic scale and complexity will force fab designers, OEMs and process integrators to investigate all open avenues in the search for solutions to the huge challenges that accompany 450mm.
The development of innovative technologies that solve the critical issues for the transition and adoption of 450-mm manufacturing will be the defining factor for whether a company merely survives or thrives.
It is becoming increasingly clear that new MEMS and 3D high-volume, low-cost manufacturing technologies will accelerate a radical change to society’s cyber skyline.
The SEMI Consensus Forecast and the SEMI World Fab Forecast, with data collected from two different methodologies, point to the same conclusion: 0% growth for 2013.
Microelectromechanical (MEMS) devices are shaping the competitive landscape in the global medical device industry.
Worldwide silicon wafer revenues declined by 12 percent in 2012 compared to 2011, according to the SEMI Silicon Manufacturers Group (SMG) in its year-end analysis of the silicon wafer industry.
Hoi-Jun Yoo, subcommittee chair of ISSCC 2013, writes on the focus of technology directions in the field of large-area and low-temperature electronics.
In the second of two installments, Linx Consulting reports a steady growth in semiconductor production, as released in The Econometric Semiconductor Forecast.
In the first of two installments, we examine the global issues facing the semiconductor industry, as released by Linx Consulting in The Econometric Semiconductor Forecast.
A new econometric semiconductor industry forecast predicts semiconductor wafer area production to grow slightly less than 6% in 2013, according to Linx Consulting.
Dr. Steffen Schulz discusses the role of a flexible platform for computational lithography in a successful business strategy.
Spending on research and development by semiconductor companies grew 7% in 2012 to a record-high $53.0 billion, even though the semiconductor market declined 1% to $317.6 billion.
Scientists at RTI International are advancing the state of science in electronic devices for optical systems by using superlattice structures to optimize the performance of germanium optical detectors on silicon chips.
C. Grant Willson and Jean M.J. Fréchet won the Japan Prize, an international award similar to the Nobel Prize, for their work on chemically amplified resists.
Gigaphoton, Inc., a major lithography light source manufacturer, announced today that the company has achieved EUV light output equivalent to maximum of 20W for its laser-produced plasma, or LPP light sources for EUV lithography scanners.
The rise in mobile computing, changes to the fabless-foundry model, uncertainties in technical innovation, and global macroeconomic trends are becoming the dominant forces in 2013 and beyond, according to industry leaders speaking at this week's SEMI Industry Strategy Symposium (ISS).
GlobalFoundries says it plans to build a $2 billion "Technology Development Center" R&D facility at its Fab 8 campus in Saratoga County, NY, for semiconductor technology development and manufacturing: EUV lithography photomasks to new interconnect and packaging technologies enabling 3D chip stacking, "and everything in between."
Several innovations in computational lithography have been developed in order to squeeze every possible process margin out of the lithography/patterning process. In this blog, Gandharv Bhatara of Mentor Graphicsl talks about two specific advances that are currently in deployment at 20nm.
Klaus Schuegraf, former exec at Applied Materials responsible for the company's semiconductor products technology roadmap, will now lead Cymer's EUV engineering and development programs.
We are in an age where chemistry is center stage in the race to advance Moore’s Law and More Than Moore.
The International Data Corporation is forecasting that semiconductor revenues worldwide will improve by 4.9% to $319 billion in 2013 and log a compound annual growth rate (CAGR) of 4.1% from 2011-2016.
Based on current indications, capital spending would seem to be flat in 2013. However, Semico predicts healthy revenue growth this year, which may encourage more spending, particularly in the second half of the year. This may bring total capex for 2013 into the positive range.
Predictions for 2013 show several notable trends: overall silicon area growth for 2013 should average approximately 6%; the first quarter and the second half are likely to show slower growth than the second quarter; and the modest growth forecast for 2013 is predominantly demand driven.
Newport Corporation introduced long-lived deep ultraviolet (UV) excimer laser mirrors with projected lifetimes greater than 30 billion pulses.
A particle as small as three microns in diameter, attached to the back side of the wafer—the dark side, if you will—can cause yield-limiting defects on the front side of the wafer during patterning of a critical layer.
Stretched-out clothing might not be a great practice for laundry day, but in the case of microprocessor manufacture, stretching out the atomic structure of the silicon in the critical components of a device can be a good way to increase a processor's performance.
SPIE Advanced Lithography, the annual forum for discussions on state-of-the-art lithographic tools, resists, metrology, materials characterization, and design and process integration, will bring the community together in San Jose, California, next week to address those challenges.
Papers showcase EUV extendibility and metrology techniques for defect inspection and 3D TSVs.
New metrology and inspection products facilitate advanced patterning techniques for manufacturing sub-20nm memory and microprocessor chips.
Molecular Imprints, Inc. (MII), a developer of advanced semiconductor lithography, has announced the delivery of an advanced lithography platform which uses Xaar 1001 inkjet printheads to pattern 450mm silicon wafer substrates.
Luminescent Technologies Inc., a provider of computational metrology and inspection solutions for the global semiconductor manufacturing industry, and Dai Nippon Printing Company, Ltd. announced today the successful completion of the first phase of a three-year joint development program for computational metrology and inspection using Luminescent’s Automated Image Processing Hub (LAIPH) platform.
EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today announced that it is developing equipment and process technology to enable covalent bonds at room temperature.
New 200 mm diameter wafer enhances photolithography capability.
Worldwide sales of semiconductors were $24.05 billion the month of January, up 3.8% from January 2012 and down 2.8% from December 2012, according to the Semiconductor Industry Association (SIA).
After reaching a worrisome high in the third quarter of 2012, global semiconductor inventories held by chip suppliers fell at a surprisingly fast rate in the fourth quarter, led by dramatic reductions for market leader Intel Corp.
STM, Imec, CEA-LETI, ASML, Soitec and EU representatives discussed directions at ISS Europe 2013 in Italy.
Joe Kwan is the Product Marketing Manager for Calibre LFD and DFM Services at Mentor Graphics. He is also responsible for the management of Mentor’s Foundry Programs. He previously worked at VLSI Technology, COMPASS Design Automation, and Virtual Silicon. Joe received a BA in Computer Science from the University of California Berkeley and an MS in Electrical Engineering from Stanford University.
Over the past five years, revenue dipped and spiked from the impact of the global recession; in the five years to come, increased offshoring will detract from the growth in global demand from an improved economy.
Researchers sponsored by Semiconductor Research Corporation (SRC), a university-research consortium for semiconductors and related technologies, today announced development of a modeling process designed to simulate atomic-level etching with chemicals that are effective alternatives to widely used perfluorocarbon (PFC) gases.
Zvi Or-Bach, President & CEO of MonolithIC 3D Inc. and Benjamin S. Louie of Zeno Semiconductor blog about dimensional scaling as it relates to EUV and future per transistor device cost.
Most electronic systems that power our digital life are inflexible and flat. Rigid electronic designs work for our computers and phones but not for our bodies. Humans are soft and curved. Electronic systems capable of bending, twisting, and stretching have great potential for applications in which conventional, stiff semiconductor microelectronics would not suffice.
Brion Technologies, a division of ASML, announced a major milestone today in its partnership with GLOBALFOUNDRIES. The companies are collaborating to deliver high-volume computational lithography capabilities for 28 nm and 20 nm tapeouts, while also accelerating the development of future nodes, including extreme ultraviolet (EUV) lithography.
Semiconductor manufacturers, suppliers and academia to collaborate on real-world issues at SEMI event.
In an effort that will accelerate commercialization of extreme ultraviolet (EUV) lithography technology and the development of next-generation transistors, SEMATECH announced today that Intermolecular, Inc. has joined SEMATECH’s Lithography and Front End Processes (FEP) programs.
Solid State Technology is excited to announce that Mark Thirsk, managing partner at Linx Consulting, will be discussing the cost and technology needed to implement next-generation device technology at The ConFab 2013. Thirsk has over 20 years of experience in the chemical industry, working with a variety of materials and processes utilized in wafer fabrication.
Gigaphoton, Inc., a lithography light source manufacturer, announced today that as of April 2013, it has started business operations at the Gigaphoton Singapore Branch, its newly established branch in that country.
Fulfilling the promise of performance and power scaling at 16nm, ARM and Cadence today announced details behind their collaboration to implement the first ARM Cortex-A57 processor on TSMC's 16nm FinFET manufacturing process.
Kotura inks fab agreement; announces relationships with Mindspeed and BinOptics.
A joint industry/academia consortium, supported by the European Union's Seventh Framework Programme, has reported the successful conclusion of a three-year project and the release of its design-synthesis tool flow and related litho-friendly cell libraries and evaluation metrics.
Mentor Graphics User Conference 2013 speaker line-up boasts a host of industry bigwigs, including former foundry CTO, Dr. Chenming Hu. Hu will give the keynote address on April 25 in San Jose, California, addressing the future of FinFET.
Nanoplas, a global supplier of plasma processing equipment to the semiconductor industry, today announced a new dry-etch process offering virtually unlimited etch selectivity for removing dielectric films on microprocessors and memories at high throughput.
Intermolecular, Inc. today announced that Dr. Raj Jammy has joined the company as senior vice president and general manager of the semiconductor group.
The long-expected demise of optical lithography for manufacturing ICs has been delayed again, even though the technology itself has reached a plateau with a numerical aperture of 1.35 and an exposure wavelength of 193nm. Immersion lithography is planned for the 20/22nm node, and with the continued delay of EUV, is now the plan of record for 14nm.
ProPlus Design Solutions, Inc. yesterday launched NanoSpice, the next-generation high-capacity, high-performance parallel SPICE simulator for giga-scale circuit simulation.
ARM and TSMC today announced the first tape-out of an ARM Cortex-A57 processor on FinFET process technology. The Cortex-A57 processor is ARM's highest performing processor, designed to further extend the capabilities of future mobile and enterprise computing, including compute intensive applications such as high-end computer, tablet and server products.
The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing and design, today announced that worldwide sales of semiconductors reached $23.25 billion for the month of February 2013, an increase of 1.4 percent from February 2012 when sales were $22.93 billion. Effective government policies needed to spur stronger growth.
Analysts break down Intel's $6B-$8B pledge to build and expand its US facilities to accommodate 22nm process technologies: what sites get new tools (and who gets the old ones), and why the new R&D fab's name isn't logical.
Chip foundry giant Taiwan Semiconductor Manufacturing Co. (TSMC) has greenlighted investments in fab infrastructure, including a new 300mm gigafab -- but there may not be any immediate capex adjustment for it, and that may be a good thing.
Hashing out the complexity of both extending optical lithography and preparing multiple next-generation alternatives for high-volume manufacturing was the focus of a Confab talk (Tues. 5/18) by Naoya Hayashi, electronic device operations, Dai Nippon Printing Co.
Among key takeaways from SEMATECH's Litho Forum last week in NYC was a proposal to create a consortium to support multibeam mask writing efforts, similar to what's being done for EUV.
Execs from Texas Instruments and Luminescent Technologies describe a "source/design optimization" technique that blends source/mask optimization (SMO) techniques with design rules, and realizes significant improvements in overall die area.
Demand for semiconductor manufacturing equipment continues to surge as the industry emerges from its slumber, with some measurements showing strength not seen in several years, according to the latest monthly data from SEMI and SEAJ.
Breaking down the quarterly numbers and forecasts from top chip spenders TSMC and Samsung, analysts determine the main thrust is that the anticipated spending cycle isn't peaking in 1H10 after all, and could instead become heavier in 2H10 and spill into 2011.
Christopher Bencher, member of the technical staff at Applied Materials, gave a presentation at the IEEE Bay Area Nanotechnology Council’s Half-day Symposium on process and integration-based scaling for 15nm nodes. In an interview with Debra Vogler, senior technical editor, Bencher discussed the company’s development work at 15nm.
Techcet's Michael A. Fury concludes his observations from this year's IEEE International Interconnect Technology Conference (IITC) meeting near San Francisco. From Day 3: Intel's airgaps for 32-22nm, Si nanowires, more on 3D bonding and TSV schemes, electromigration in Au nano-junctions -- and enforcing "Zafiropoulo's Law."
The latest monthly sales & order data for US-based and Japanese semiconductor manufacturing equipment shows growth slowing down -- and possibly because except for some pockets, it may be time for things to pull back a little bit.
A talk by Intel's Fab 11X manager kicking off this week's the International Conference on Planarization Technology about "challenges of manufacturing" rang true for many sectors of the chipmaking ecosystem, reports Techcet's Karey Holland.
Rigaku Innovative Technologies announced further expansion into the optics market for extreme ultraviolet (EUV) lithography. RIT plans to continue supporting the industry by supplying Osmic Coatings, a line of multilayer coated optics that are essential to EUVL.
Laura Peters, contributing editor, discusses TSMC's HfZrO/TiN stack, fabricated by a novel multi-deposition, multi-anneal process. TSMC will present the results at the upcoming International Electron Devices Meeting (IEDM, San Francisco, CA, December 6-8, 2010) with researchers from the Nanyang Technological University (Singapore).
Nick Kepler, Globalfoundries presenter at the IEEE Bay Area Nanotechnology Council’s Half-day Symposium, described the company’s rationale for selecting the gate-first approach to HK+MG processing. Kepler also discusses EUV lithography (EUVL) use at 20nm.
A slew of announcements and developments out of this week's IMEC Technology Forum (June 7-8, Leuven, Belgium) span the gamut from facilities expansion to GE photovoltaics and gas sensor devices.
Touting extreme ultraviolet (EUV) lithography as the industry's best bet to extend Moore's Law below the 2Xnm generation, experts gathered at a recent event in Hawaii described "steady progress" in source power, resist performance, mask defect reduction, and other major EUVL challenges.
Samsung says it will spend nearly $10B in capex just for semiconductor manufacturing, and $B overall -- nearly double its initial plans, and two-thirds higher than in 2009. Analysts tell SST what's significant inside the numbers (foundry), and what it means for the rest of the industry -- and why 2011-2012 might now look a lot different.
SEMATECH's Dan Armbrust underscores the need to determine up-front what areas are truly important to keep pushing scaling and cost-effectiveness in the semiconductor industry.
Because of the limitations of 193nm lithography, much of the shrink capability comes from computational lithography, with software-driven advancements in optical proximity correction (OPC) and resolution enhancement technology (RET). James Word and Xima Zhang from Mentor Graphics discuss solving the computational load challenges that arise from the industry's increasing complex lithography roadmap.
Toshiba reportedly is prepping a ¥15B (US $157M) investment in a <25nm NAND flash test line, eyeing mass production in 2012, a move that not only tightens the NAND flash scaling wars, but also could narrow the insertion point for a next-generation lithography set.
An EU-funded project has come one step closer to its goal of building silicon photonics circuits, with the creation of a fully CMOS-compatible laser source coupled to a silicon waveguide.
Scientists at the US Defense Advanced Research Projects Agency (DARPA) are asking industry to come up with new ways of designing integrated circuits for affordable, low-volume nanofabrication for US Department of Defense (DOD) applications.
Carl Zeiss SMS and Synopsys will collaborate to support in–die metrology solutions for the 32nm technology node and below. Using CATS as a data preparation engine, mask engineers using PROVE can benefit from improved efficiency and usability of a registration metrology system that meets stringent overlay accuracy requirements.
In two exclusive interviews, Lode Lauwers, senior director of business development at IMEC, and Tom Jefferson, ISMI 450mm program manager, speak with Debra Vogler, senior technical editor, in advance of the SEMICON Europa 450mm session.
TowerJazz and Crocus Technology completed the first stage of integration of Crocus’ Thermally Assisted Switching (TAS)-based MRAM technology into TowerJazz’s 0.13-µm CMOS process. As a result of the collaboration, a special low temperature back-end process technology was developed.
The Extreme Ultraviolet Lithography System Development Association (EUVA) says it has surpassed 100W output at intermediate focus for an EUV light source, another big step to address a big hurdle facing EUV lithography as a production-viable candidate for next-generation semiconductor manufacturing.
Sanjay Kapasi from KLA-Tencor tells SST how the latest-generation PROLITH virtual lithography tool, PROLITH X3.1, takes aim at the skyrocketing R&D expenses being incurred at the 1X and 2Xnm nodes, by leveraging simulations rather than printed test wafers.
The SPIE Advanced Lithography Conference is where experts come to tell their advances in lithography, resists, metrology and design, and this week it appears to be heating up as a battle between optical and surging EUV, with other litho technologies offering a "sanity check," writes Griff Resor.
Progress has been made on double-patterning lithography and EUV, but in the end, chipmakers must decide which technology to use based on availability, cost, and product roadmap requirements, notes Stefan Wurm from SEMATECH.
Advantest Corporation released a SEM-based critical dimension (CD) measurement system for next-generation photomasks and patterned media. The E3630 is fully compatible with Advantest’s existing E3610/E3620 CD-SEM measurement systems and software, and boasts 30% improved linewidth repeatability.
EUVL introduces new challenges to the software used to correct pattern distortions introduced by exposure, resist, and etching processes. While the low k1 of EUVL would seem to provide a bit of an OPC vendor’s holiday, it’s shaping up to be quite the opposite situation. James Word, Mentor Graphics, shows us what next-gen litho pattern distortions are, and how to correct them.
Techcet's Michael A. Fury reports from the 7th International Surface Cleaning and Preparation Workshop put on by Northeastern and Hanyang universities in Boston, with early talks involving various themes: EUV mask cleaning and chemical mechanical planarization (CMP), crystalline silicon solar cell texturing, and even nano-chopsticks.
Eulitha developed a proprietary photolithography technology for low-cost and high-throughput fabrication of photonic nanostructures. The patented technology enables the formation of periodic nanostructures over large areas for such applications as LEDs, solar cells, and flat-screen displays.
Michael A. Fury continues with observations from IEDM 2010, looking at 2nd-day papers on a 90nm CMOS image sensor; an 11nm planar multi-gate CMOS design with self-assembled gates; SiC/GaN power electronics for auto systems; an update on future memory technologies; and a transparent photosensor array with triple oxide TFTs as both switches and sensor elements.
Brion Technologies, a division of ASML, debuted the Tachyon NXE software to optimize predictive modeling for ASML EUV scanners. EUV scanners enable smaller, faster, cheaper and more energy-efficient semiconductors. This article includes a podcast interview on the technology.
Authors from Synopsys and IMEC assess the readiness of rigorous physical resist model calibration for accurate EUV lithography simulation. They discuss pattern selection for calibration, illustrate the speed and robustness of model building, and examine model validation results. Predictability of the resist model is demonstrated across various flare levels, pitches and critical-dimension ranges.
Sidense, developer of logic non-volatile memory (LNVM) IP cores, announced that the USPTO granted Sidense Patent Number 7,755,162, "Anti-fuse Memory Cell." The '162 patent adds to the Company's patent portfolio covering its 1T-Fuse memory technology.
In these three video interviews from SEMICON West 2010, Leti research directors speak with senior technical editor Debra Vogler. Yannick Le Tiec discusses cleaning; Michel Brillouet speaks on 3D packaging work, and Didier Louis updates us on advanced lithography.
In this video, Hans Meiling, ASML, touches on EUV's three required three components: process (resist), mask infrastructure and metrology, and exposure tool.
Imec reports promising results in its extreme ultraviolet lithography (EUV) mask cleaning program for defect-free EUV masks that are crucial in achieving high chip manufacturing yield.
In this video interview, Franklin Kalk, Toppan Photomasks, comments on the big EUV news annouced at SEMICON West. Technical challenges of EUV remain defect management -- finding and fixing defects in masks. Pattern mask inspection may not be ready until 2016.
CEA-Leti's Laurent Pain and Didier Louis report from Sokudo's annual Lithography Breakfast at SEMICON West, where this year's forum addressed challenges and development needs for the 22nm node, and updates on 193nm and potential successors EUV and maskless.
Imec and ASML collaborated to qualify ASML’s Tachyon Source Mask Optimization and programmable illuminator system FlexRay, proving its potential with the demonstration of a 22nm SRAM memory cell. In October 2010, the ASML XT:1900i lithography scanner at imec will be equipped with FlexRay, enabling imec to explore the ultimate frontiers of immersion lithography.
Scientists from Singapore A*STAR’s Institute of Materials Research and Engineering, University of Cambridge, and Sungkyunkwan University created thin metallic lines with line width roughness below the 2010 targets. The researchers used an organometallic material and a combination of electron beam lithography and subsequent gas treatment to easily chip away the organic portions in a uniform manner, leaving the desired metallic patterns.
Based on talks and presentations from the SPIE Advanced Lithography Conference, the future for IC manufacturing is still very much unclear, writes Griff Resor. How close is optical litho to finally reaching its limits? Has the time has come to switch to a replacement technology like EUV, and what still needs to be accomplished?
Toppan Photomask's Franklin Kalk handicaps the litho field, mapping their abilities and potential to professional baseball teams as the new season approaches. (And yes, it comes down to the Red Sox and Yankees.)
Barclays Capital's CJ Muse came away from SPIE with the message that litho demand is strong, with a "heightened focus on EUV" due to increased costs associated with double patterning -- and why rumors about a delay in EUV adoption may not be accurate after all.
Several discussions and presentations at last week's SPIE Advanced Lithography Conference deserve special note -- from work with e-beam EUV mask inspection, to nanoimprint achievements (11nm!), an EUV tool platform roadmap, mask productivity and cost issues at 22nm, and more on SMO and tunable DOEs.
Entegris execs summarize two poster papers from the SPIE Advanced Lithography Conference that covered the company's methods to detect ppt levels of trimethylsilanol (TMS), and evaluating microbridging defects in which 5nm filtration was compared to 3nm filtration levels.
Christopher Wargo, Entegris, talks contamination control at 22nm and below. Lithography presents a suite of issues for contamination control. While the technology exists to confront new contaminants, commercialization is key.
Intel has given its nod to two dozen key partners from its roster of thousands of supply-chain contributors as the 2009 winners of its annual supply chain awards -- and within the listings is a interesting nugget about the chipmaker's lithography strategy.
Checks into key chipmakers in Korea and Taiwan suggest current demand for equipment is still on the rise, with planned capex increases imminent and capacities set to increase into 2011, according to one industry analyst.
Gary Green, co-chair of the yield enhancement/methodologies sessions at this week’s Advanced Semiconductor Manufacturing Conference (colocated with SEMICON West), reviews key themes discussed, including techniques aimed at faster root cause analysis, new methods in analyzing contact failures using e-beam and TEM tools, and increasing test coverage while reducing the number of test wafers.
ASML Holding NV (ASML) announced broad customer adoption of holistic lithography products that optimize semiconductor scanner performance and provide a faster start to chip production. All of ASML’s leading-edge scanners are now sold with one or more holistic lithography components.
Wrap-up of what we heard and saw at SEMICON West 2010. Lesson 4: The semiconductor/equipment/component supply-chain went from ice-cold to red-hot in a matter of months, which brings its own unique challenges to the industry.
Innovation drives everything -- and innovation spawned from the semiconductor and related industries is poised to do nothing less than change the world, or at least help everyone adapt better to it, as related by SEMICON West kickoff keynoter Bernie Meyerson of IBM.
Analysts break down some of the more important points of Applied Materials' 3Q10 numbers and discussions. Key takeaways: A few key marketshare wins, NAND flash is about to explode, and any macro sluggishness hasn't materialized yet in chip tool demand.
DRAM memory "turbulence" might rear its head in 2H10 with supplies falling short of demand, because of manufacturers' problems in migration to newer processes and unable to obtain key pieces of leading-edge equipment, according to iSuppli.
In a series of podcasts, 3 of the presenters at the SEMICON Europa Lithography session speak with senior technical editor Debra Vogler. Interviewees include consultant Wolfgang Arden, Rolf Seltmann of Globalfoundries, and IMEC's Roel Gronheid.
The Semiconductor front-end track of SEMICON Europa includes the 14th Fab Managers Forum; and sessions on lithography, automation and process control, metrology, new materials, secondary equipment/services, and a progress review of 450mm.
Toshiba details its use of bit-patterned media to fabricate a hard disk with an areal density of 2.5 terabits per-square-inch and a practical servo pattern. According to the company, BPM technology is a leading candidate to achieve terabit-class high density HDD recording. This article includes a podcast interview on the technology.
Dainippon/AMAT JV SOKUDO Co. Ltd., lithography coat/develop track, and process equipment company, will join the new industry/research multi-partner program IMAGINE (led by CEA-Leti), developing maskless lithography for IC manufacturing.
The eBeam Initiative has several members jointly presenting the latest breakthroughs in DFEB mask technology at the SPIE/BACUS Symposium. The collaborative results demonstrate the effectiveness of DFEB mask technology on advanced photomasks at the 22-nm node and beyond. This article includes a podcast interview with the presenters.
Which transistor structures and materials will garner the most support at 16nm and below? In this podcast interview, Dean Freeman, VP of research, Gartner, provides his perspective on the various paths: FinFETS, tri-gates, fully-depleted SOI (FDSOI), Ge/III-V, bulk CMOS, and so on.
PC makers are jamming cheap DRAM into systems, as pricing reaches critical levels. Watch for DRAM makers at 6x-nm and 5x-nm nodes to become inefficient, warns iSuppli. DRAM prices are expected to remain critical until at least H2 2011.
Under the agreement, a team of mask cleaning experts from Dai Nippon will work with experts from SEMATECH’s Mask Clean program at CNSE’s Albany NanoTech Complex to improve the cleaning yield on extreme ultraviolet (EUV) lithography patterned, non-patterned substrates and nanoimprint lithography (NIL) templates.
Oleg Kishkovich, Tom Kielbaso, David Halbmaier, Entegris Inc., present analysis of a method for controlling AS haze, maintaining 193nm reticles in low-humidity lithography environments in HVM fabs. Critical reticle haze control elements and limiting factors are delineated.
Actinic EUV inspection preserves the production paradigm with acceptable cost-per-inspection despite higher capital costs. Its development path is clear and achievable in time to meet technical and economic requirements for 16nm-hp production in 2015. Brian Haas, Gregg Inderhees, KLA-Tencor Corp., explain key elements of mask inspection and what actinic EUV inspection provides.
In this video interview, Bryan Rice, SEMATECH, discusses the readiness of EUV. SEMATECH is partnering with Carl Zeiss for EUV process development. The next phase will be a blank inspection phase, beginning a few months after SEMICON West.
Accelerated capital spending, process technology roadmaps, and customer adoptions were among several key trends gleaned by Credit Suisse analyst Satya Kumar from GlobalFoundries' recent technology conference.
Applied Materials (AMAT) launched its new Applied Centura Tetra X Advanced Reticle Etch system capable of etching photomasks needed for challenging device layers at 22nm and beyond. Expanding the capabilities of AMAT's Tetra III platform, the Tetra X breaks the 2nm critical dimension uniformity (CDU) barrier across all feature sizes.
Franklin Kalk, Toppan Photomask, examined the photomask industry structure and how it determines industry profitability. Consider: the threat of new entrants (that is, other firms entering the market to compete against the incumbents), the bargaining power of suppliers and of customers, the threat of substitutes (that is, products that might replace photomasks), and rivalry among the existing lithography firms. This article includes an in-depth podcast about the photomask industry.
AMO GmbH and SUSS MicroTec AG are developing applications for substrate conformal imprint lithography (SCIL) with UV curing material. Due to unique sequential contacting and separation technology, a distortion-free replication of a stamp at high throughput is now possible with UV-SCIL.
Advances in lithographic patterning critically depend on the timely availability of enabling resists and materials, say Warren Montgomery and Stefan Wurm, SEMATECH. They detail the toolset and collaborative approach of SEMATECH, which helps bridge the lapse between basic research and wafer fab production processes to keep lithography moving forward. What has the research organization's attention in 2010?
Answering the growing demand for a high resolution, Dr. Schenk has developed an enhanced version of the Pollux Particle Detection System for Photomasks. Pollux-Enhanced automated particle detection system enables fabs to perform a complete inspection on each reticle prior to its use.
DRAM manufacturing costs are on the rise for the first time in four years, raising questions about production expenses in the memory industry, but things should improve in a few quarters, according to a new report from research firm iSuppli.
GLOBALFOUNDRIES teamed with Cadence Design Systems to create an open-access 28nm Analog/Mixed-Signal (AMS) production design flow development kit.
Ludo Deferm, IMEC, came to SEMICON West with several major announcements, from the system level to the layers of semiconductors. IMEC's major interests include scaling with 3D technologies, selective epitaxy, RRAM, lithography, and more.
SEMICON West may not be the big-iron displayfest it once was, but there are still plenty of new product introductions to go around. Here's just a brief rundown of some of the ones we tracked from this year's show.
SEMATECH announced a 450mm imprinted wafer, accomplished by EV Group (EVG). Markus Wimplinger, EVG, described the timeline for the 450mm effort and how the company decided to make a strategic move.
Lithography light source maker Gigaphoton Inc. verified its original technology for mitigating debris with magnetic fields for laser-produced plasma (LPP) light sources, clearing a hurdle for mass-production use.
Intermolecular's George Mirth reports on interesting keynote speeches and comments from the Sokudo Lithography Breakfast at SEMICON West, in talks from ASML, Nikon, Mapper, Xtreme, and imec.
In an SST-exclusive series of blogs, imec reports from its International Technology Forum this week in Brussels. Geert Vandenberghe talks about how EUV lithography is at a readiness crossroads, but he feels "fairly secure" about its current capabilities.
Bob Krakauer, CFO of GlobalFoundries, summarized industry trends in manufacturing and end-applications, a changing foundry landscape, and his company's own long-term investments in semiconductor manufacturing, in his Confab presentation.
New innovative processes and materials could be the least costly way to get to <10nm lithography, says Lori Nye, Brewer Science, at The ConFab. With the right use of materials, one can go 2 or 3 nodes beyond currently accepted lithography limits on exposure tools.
Harvey Frye, vice-chairman of TEL America, summarized the new supplier landscape in his Confab talk, taking both a macro point of view of trends, and how his company as a top supplier is addressing them: collaboration among suppliers, and an increasing focus on consumer needs.
Photoresist revenues will grow at about 5% for the next several years, says Techcet Group. Consolidation is long overdue among resist suppliers, and EUV may be the last straw. For materials, supply is abundant.
KLA-Tencor will join SEMATECH-led efforts to identify and eliminate defects in EUV lithography, including mask metrology infrastructure and metrology source development.
IBM researchers built an integrated circuit (IC) fabricated from wafer-scale graphene on SiC, integrating a graphene transistor with other electronics circuits.
David Lam summarizes how the industry does not have to "throw out" optical lithography as it proceeds to more advanced nodes -- complementary e-beam lithography (CEBL) is part of the overall solution, "complementary lithography," that can overcome the resolution limitations of 193i technology.
Tien Wu, ASE; Rama K. Shukla, Intel; and Luc Van den hove, imec, are the honored presenters for SEMICON West 2011.
At CEA-Leti's Annual Review, STMicroelectronics CTO Jean-Marc Chery reviewed the challenges facing IDM companies focused on SoC markets, and the three primary challenges for IDMs: FinFETs, EUV lithography, and 450mm.
At CEA-Leti's Annual Review, Leti lithography program manager Serge Tedesco described the IMAGINE industrywide project to assess maskless multi e-beam technology, including the system's expected capabilities within two years.
The semi industry faces major cost challenges in patterning advanced ICs in high volumes. A cost-effective solution remains elusive. David K. Lam, Multibeam Corporation, addresses lithography cost-of-ownership.
Heidelberg Instruments optioned University of Colorado Boulder's technique for shrinking copper circuits by zapping a substrate with two separate colors of light beams.
Two TechXPOT sessions at SEMICON West will address the new architectures needed to continue scaling both logic and memory devices, as well as the major challenges facing lithography both for EUV and options for extending 193nm immersion.
Dick James, ChipWorks, speaks about Intel's presentations on strain engineering and lithography masks for trigate transistors, and the industry split between FDSOI and trigates.
SUSS MicroTec unveiled MaskTrack Pro InSync, a holistic in-fab EUVL mask management product that synchronizes mask cleaning, handling, inspection, and storage.
Nigel Farrar, Cymer, provides a status report on EUV lithography source technology, extensions to ArF lithography, the laser crystallization process from the company's TCZ display equipment product division, and Cymer's newest DUV source product the OnPulse Plus data monitoring system.
Stefan Wurm, SEMATECH, discusses EUV lithography's infrastructure. Want milestones? The first EUV litho beta tools have been delivered, and now the motivation is increasing throughput and reducing defects.
At SEMICON West 2011, Phil Bryson, SEMATECH, covers the top challenges in semiconductor metrology at advanced nodes.
ASML has added three extensions to its Twinscan NXT 1950i tool, to improve imaging, overlay, and system throughput.
The Conformal Film Deposition (CFD) suite of dielectric films consists of oxide, doped oxide and nitride films that are deposited below 450
Suss Microtec and imec are expanding a research collaboration in mask cleaning to develop an in-fab approach to EUV lithography mask integrity, aiming to develop a sophisticated approach to preserving mask integrity prior to exposure.
ASM International's Bob Hollands discusses the challenges of making FinFET structures using both epitaxial and high-k/metal gate (HKMG) atomic layer deposition (ALD) processes.
CEA-Leti's Serge Tedesco and Didier Louis summarize key themes from the Sokudo lithography breakfast forum held last week at SEMICON West.
Franklin Kalk, Toppan Photomasks, covers the major lithography demands of distinct semiconductor technologies: Logic, Flash, and DRAM. He also gives an update on fabless/foundry options, and Japan's earthquake recovery.
Accurate mask-wafer double simulation is a new, required step for lithography at the 20nm node and beyond because corner rounding becomes the dominant effect, explains Aki Fujimura, D2S.
The updated "Garment System Considerations for Cleanrooms and Other Controlled Environments" document includes new sections on measuring footwear, frocks and other garments, as well as a new subsection for tracking system use, such as RFID chips and barcodes.
Asahi Kasei E-Materials Corporation purchased an IQ Aligner UV nanoimprint lithography (UV-NIL) system from EV Group (EVG).
Tokyo Electron Limited (TEL) and ASML Holding NV (ASML) will accelerate joint development activities in extreme ultraviolet (EUV) and argon fluoride (ArF) immersion lithography clusters.
Under new CEO Ajit Monocha's realignment plan, GLOBALFOUNDRIES named new CFO, CTO, and customer engineering and quality leaders. The CTO position is a new one at the semiconductor foundry. The moves are meant to separate technology strategy from technology development.
Dr. John Chen, VP of technology and foundry operations at Nvidia, and Thomas Jefferson, ISMI's 450mm project manager, are among the updated speaking roster of ConFab 2012, which will address the economics of semiconductor manufacturing and associated industries (LEDs, MEMS, displays).
Cymer Inc. (Nasdaq:CYMI) revealed the third-generation Gas Lifetime eXtension (iGLX) control system for argon fluoride (ArF) immersion light sources used in semiconductor lithography.
Mentor Graphics and JEOL will collaborate on multi-resolution mask writing for shot count reduction of up to 30% compared to the conventional writing technique for IC lithography masks.
"The recent period
Intermolecular Inc. (Nasdaq:IMI) priced its initial public offering of 9,650,000 shares of common stock at a public offering price of $10.00 per share.
North America-based manufacturers of semiconductor equipment posted $973.3 million in orders in November 2011, $1.17 billion in billings, and a book-to-bill ratio of 0.83, according to the November Book-to-Bill Report from SEMI.
SEMI reports worldwide semiconductor manufacturing equipment bookings fell 38% year-over-year in Q3 2011; billings dropped 5% for the same quarter.
Nikon Corporation released its NSR-S320F argon fluoride (ArF) lithography scanner for advanced 20nm node semiconductor device manufacturing. It boast high productivity and high accuracy, with stable operation in the field, Nikon reports.
A number of big-name frontend equipment firms highlight TSMC's annual supplier awards in 2011, as the foundry expands its list of top suppliers.
Historically countercyclical-investing Intel is up to its old tricks, pledging a massive record spending spree in 2011. We break down all the numbers and what they mean, from exec statements and Q&A comments to what key industry analysts think.
The last day of this week's SEMI/IEEE Advanced Semiconductor Manufacturing Conference (ASMC) featured talks on EUV readiness and hurdles, CMOS image sensors' increasing complexity, embedded memory failure analysis to improve yields, and a coming shift from chip technology efficiency back to innovation.
Intermolecular's John Behnke offers his impressions from Day 1 of this year's SEMI/IEEE Advanced Semiconductor Manufacturing Conference (ASMC) in New York. Highlights: a keynote from a suddenly famous GlobalFoundries exec, on-the-fly edge inspection, equipment health monitoring, and a TSV overview.
Describing work being done at Albany Nanotech, IBM's Dave Medeiros listed the new anticipated due-date for EUV lithography (11nm), and what other lithography option might be ready as an alternative technique around that same time.
imec's An Steegen outlined the requirements to continue Moore's Law and new technologies being pursued to that end. Perhaps most important is lithography, where she provided an update on EUV tool productivity, resist benchmarking, and mask defect results.
High performance and low power consumption are expected of today's chips and LEDs. Today's chip makers still expect to keep their costs down. The key to making this work, says Brian Trafas, KLAC, is yield optimization. Trafas, speaking at The ConFab 2011 in Las Vegas, touches on tool supplier/user collaborations as well.
An Steegen, imec, shares how imec is helping enable Moore's Law's continuation to <10nm. Moore's Law through 19nm could be lithography-enabled, Steegen says, but past that point we need to rely on materials, such as high-k, and new device architectures. She also provides an update on imec's EUV progress.
Ultratech, Inc. (Nasdaq: UTEK) announced an Asia Technology Center (ATC) in Taiwan to develop processes for HB-LED manufacture on its Sapphire 100 lithography system.
Novellus Systems (NASDAQ: NVLS) subsidiary Peter Wolters GmbH introduced innovative gap measurement technology for double-side silicon prime wafer polishing. New high-resolution sensors and software algorithms increase control of wafer quality, as well as throughput for the AC2000-P3 system.
"You can't approach the future by predictions. You approach the future by making it happen," Terry Brewer, founder/president of Brewer Science, says. And this mindset carries over into real-world results for the semiconductor industry, he points out: "EUV will happen if we want to make it happen."
What does the industry have to show so far from its mountainous investments in EUV? Reporting from the SPIE Advanced Lithography conference, Franklin Kalk from Toppan Photomasks examines several papers summarizing EUV progress and challenges, and pins current work somewhere between "science project" and "a long way to go."
Nanometrics Incorporated (Nasdaq:NANO), advanced process control metrology provider, launched the Mosaic II turnkey image-based overlay metrology solution for advanced high-volume IC manufacturing. NANO reports an initial delivery to a leading Asian memory customer.
At SPIE Advanced Lithography, Kurt Ronse, director of lithography at imec, discussed with Debra Vogler the research center's new ASML pre-production EUV scanner, EUV readiness with source power (still a concern) and resists (practically there). He also discusses the perhaps overlooked topic of pattern collapse.
Franklin Kalk, CTO of Toppan Photomasks, tells ElectroIQ's Debra Vogler, senior technical editor, where the current hurdles are for EUV mask work, the pros and cons of EUV vs. e-beam direct write (EBDW), and why there hopefully is room for both technologies -- which isn't great news for foundries.
Cymer Inc. (Nasdaq: CYMI) introduced a focus drilling technology for its immersion light sources including the XLR 600ix, XLR500i, XLA 400 and XLA 300. Focus drilling provides up to a 2X improvement in the depth of focus on the wafer.
Nigel Farrar, Cymer, provides an update on EUV source technology, DUV lithography, laser lifetimes with gas improvements, and the company's product release at SPIE Advanced Lithography, Focus Drilling. He speaks with senior technical editor Debra Vogler.
Carl Zeiss introduced a new production tool aimed to improve registration and overlay of advanced photomasks. RegC is based on ZEISS femtosecond-laser technology. RegC enables correction on high-end photomasks for remaining registration errors after the pattern generation process. Current results show registration improvements over 50% in advanced lithography.
austriamicrosystems (SIX:AMS) conditionally released its advanced 0.18µm High-Voltage CMOS process technology "H18" to for volume production. It will be manufactured in IBM's 200mm Burlington wafer facility.
Every top-10 wafer-fab equipment supplier in VLSI Research's annual rankings remained on the list in the new 2010 version, but there were some position changes.
As a follow-up Intel's announcement of a new 22nm trigate transistor structure, we polled and tracked multiple industry watchers for their thoughts on the technology. Their key takeaways: Intel reasserts its manufacturing prowess, and could be setting up for plays in mobile and foundry.
ASM International N.V. (NASDAQ: ASMI) received multiple system orders for its plasma enhanced atomic layer deposition (PEALD) reactor from a leading memory customer in Asia. The company also qualified a new PEALD oxide application with a memory manufacturer for the 2X nm node.
Shyng-Tsong Chen, lead integrator for back-end integration at IBM (Albany Nanotechnology Center), will be presenting "64nm pitch Cu dual-damascene interconnects using pitch-split double-exposure patterning scheme" at the IITC 2011 Conference. This technology will be needed for BEOL interconnects beyond 22nm devices.
4DS will collaborate with engineers from SEMATECH's memory program to build a full transistor-memory, demonstrating a working prototype of a low-power RRAM device.
Two analyst reports review just how prosperous 2010 was for most (but not all) semiconductor capital companies, and how 2011 is shaping up to be even better -- even with ramifications from Japan's earthquake/tsunami disaster.
GLOBALFOUNDRIES, semiconductor foundry, signed a strategic long-term partnership on sub-22nm CMOS scaling and GaN-on-Si technology with the nanoelectronics R&D center imec.
Gigaphoton released the latest developments in its EUV source program at this week’s SPIE Advanced Lithography conference. The company reported achieving a 3.3% CE with tin droplets <20µm in diameter with its plasma-based LPP.
By transferring all ownership in the litho source JV with Komatsu, Ushio and Gigaphoton can go thier separate ways with EUV source development.
Imec researchers will present "Carbon nanotube interconnects: electrical characterization of 150nm CNT contacts with Cu damascene top contact" at IITC 2011. Dr. Marleen van der Veen, senior research scientist at imec discussed the research results and their significance.
Picosun Oy has launched production of plasma enhanced ALD (PEALD) systems based on a highly advanced ion-free remote plasma source, Picoplasma. Various excited species such as oxygen, nitrogen and hydrogen radicals with zero charge can be generated to broaden the range of ALD process chemistries.
Janice Golda, Intel, co-led a session at The ConFab 2011 on continued device scaling. EUV infrastructure will be a major topic, as well as transistor challenges. While lithography difficulties exist at tighter device densities, Golda reminds us that metrology obstacles must also be tackled.
Wafer fab capex in 2011 is expected to stick around 2010 levels. But don't despair of growth, says Dean Freeman of Gartner. For one thing, cutting-edge wafer fab equipment will be hot. On top of that, 2011 will be a brief respite, with a strong 2012/2013 waiting in the wings.
Toppan Printing Co. Ltd. extended a joint development agreement with IBM for leading-edge photomask process, covering the 14nm technology node for logic devices. Toppan and IBM will focus their joint development efforts on ArF immersion lithography for the 14nm node.
Single-exposure patterning schemes are unable to meet 22nm specifications, which leads fabs to use double-patterning like LELE. However, below 22nm, a simple multiplication of double-patterning is exceedingly difficult. Alternative processes like tone reversal, EUV, and resist freezing are under development, says Nick Pugliano, Dow Electronic Materials. This is an online exclusive essay in SST's Forecast for 2011: Back to Reality series.
The conditions and challenges at the 22nm technology node are becoming clear: double patterning, source-mask optimization are becomign pervasive, EUV is on the doorstep, and they will all have significant impact on mask manufacturers, writes Franklin Kalk from Toppan Photomasks.
Spacers are considered "conventional materials," and thus an odd topic for the cutting-edge IEDM. ASM CTO Ivo Raaijmakers points out that semiconductor fab below 22nm will require different processes for spacers: atomic layer deposition (ALD) and plasma-enhanced ALD (PEALD).
The amount of data that will need to be moved in the not-too-distant future motivates research into a better way to connect devices, said Intel Fellow and director of the Photonics Lab at Intel Labs, Mario Paniccia, at SEMI’s Industry Strategy Symposium (ISS). Paniccia discusses the manufacturing requirements for silicon photonics, including optical testers.
At the SPIE Advanced Lithography conference, Luc Van den hove, president and CEO of imec, announced during his keynote speech that imec has started the installation of ASML's pre-production extreme ultraviolet lithography (EUVL) scanner, the NXE:3100, in its Leuven, Belgium facility.
Arizona State University's Hongbin Yu and Hao Yan are exploring how to use top-down lithography combined with modified bottom-up self-assembling nanostructures to guide the placement of nanostructures on silicon wafers.
Sanjay Yedur et al, from Pivotal Systems and J.H. Lee et al from Samsung’s R&D Equipment Engineering Team discuss the use of a real-time gas flow monitoring system that allows for in-situ flow measurements, based on a highly accurate rate of pressure drop over a known volume and temperature. Using this system, insights are gained on the run-to-run repeatability of mass flow controller (MFC) transient and steady-state flow during wafer processing.
Eulitha AG and Dai Nippon Printing (DNP) say they have successfully patterned 4-in Si wafers with Eulitha's "PHABLE" technology, creating uniform photonic crystal patterns with 600nm period and hexagonal symmetry.
Aki Fujimura, chairman & CEO of D2S, provides an update of the eBeam Initiative roadmap. Speaking at SPIE Advanced Lithography with editor Debra Vogler, Fujimura recalls mask cost/yield and write time developments, summarizes the eBeam Initiative's meeting, and describes member Dai-Nippon Printing's impressive time results with an "impossible" mask.
Mattson Technology Inc. (NASDAQ: MTSN) introduced the SUPREMA XP5 photoresist dry strip system for high-volume production of current and future-generation logic, DRAM and flash memory devices.
At SPIE Advanced Lithography, David Lam, Multibeam chairman and former CEO of Lam Research, presented the complementary e-beam lithography (CEBL) concept. IC manufacturers will find CEBL beneficial as they search for ways to continue using their optical lithography equipment, says Lam.
Common Platform Technology execs have declared that they will switch from a gate-first approach to a gate-last approach starting with the 20nm process technology node, essentially reversing their position for the past few years. Analysts told SST why the CPA had a change of heart, why it's not unexpected, and why other concerns will very soon overshadow this switchover -- and likely resurrect the debate.
Dan Armbrust, SEMATECH, spoke about the role of collaboration in his SEMI Industry Strategy Symposium presentation. Significant technology transitions facing the semiconductor industry include lithography (introduction of EUV), interconnects (TSVs and 3D packaging), and productivity (450mm wafer manufacturing). Additionally, disruptive technology in logic and memory devices will challenge the industry.
The 2010 Update to the International Technology Roadmap for Semiconductors (ITRS), while not one of the scheduled major revisions, nevertheless includes substantial changes have occurred in 2010, including boosts in the timelines for NAND flash and DRAM device rollouts, backup plans for lithography forced by EUV delay, impending device and interconnect structural changes, and progress in 3D packaging.
Brewer Science launched the OptiStack system of advanced lithography products: a combination of materials, software and process support. In tandem, Brewer Science debuted the ARC 300 coating series, designed to work with OptiStack.
SoftJin Technologies, a provider of customized automation software for electronic design and manufacturing, enhanced NxDAT, its defect analysis software. The enhanced version of NxDAT is optimized for better speed and memory performance.
TSMC's Morris Chang has laid out a surprisingly bullish timeline for the foundry's 450mm wafer-size transition. Analysts weigh in on whether TSMC's goals are achievable, and what it means for the rest of the industry.
Reticle Labs released RS-Mini, an enterprise-class highly compact mask inspection defect management framework for mask and wafer fabrication plant infrastructure. It allows fabs to share inspection results, track defect trends, summarize inspection results from multiple systems, and more.
Synopsys introduced the Proteus LRC for lithography verification at the SPIE Advanced Lithography Conference. It is targeted for 28nm and below and includes EUV as well as double-patterning (DPT) capabilities. George Bailey, director, technical marketing at Synopsys, describes the data flow process.
Synopsys introduced Proteus LRC for lithography verification at SPIE Advanced Lithography. Proteus LRC provides process-window-aware checking features to identify locations in a design that are sensitive to process variations, enabling corrective actions prior to committing a semiconductor design to manufacture.
Luc Van den hove, president/CEO of imec, summarizes key themes from his keynote presentation at the SPIE Advanced Lithography symposium. Van den hove speaks about materials challenges, silicon photonics, and semiconductors in healthcare/medicine in an interview with Debra Vogler at the show.
Among the topics covered at KLA-Tencor’s annual Lithography Users Forum was extension of KLAC's Teron 600 platform for inspection of EUV blanks at the 16nm hp node. Here, Brian Trafas speaks with Debra Vogler about process control in advanced lithography.
Ron Kool from ASML reports on updates in EUV and other next-generation lithography technologies at this year's SPIE Advanced Lithography symposium.
Applied Materials integrated Magma's CAD-based navigation and yield analysis software with AMAT inspection systems; it's called Excalibur Litho and targets designs at 2xnm and below. Ankush Oberai, Magma and Erez Paran, AMAT, explain why hot spot identification and real line data for libraries will fuel better lithography processes.
Dr. David Lam from Multibeam reports on the Nikon LithoVision conference at this year's SPIE Advanced Lithography symposium, where Nikon and Intel tipped results and strategies for 1D gridded layouts, and hinted at mysterious "game-changer" litho efforts besides 193i and EUV.
Toppan Photomasks will expand its Shanghai manufacturing operation serving China's semiconductor industry. Costing about $20 million, the expansion will increase photomask production significantly, and enable more advanced photomasks made with feature sizes as small as 90nm.
Molecular Imprints Inc. will build a 450mm-capable lithography system for an undisclosed leading IC manufacturer.
Novellus Systems (NASDAQ:NVLS) debuted ceramic hard mask (CHM) materials for use in sub-22nm patterning applications. The CHM materials reportedly improve performance over TiN hard masks, and with easier integration onto the fab floor.
Yann Gallais, Leti, shares updates from Leti, TSMC, and Mapper on maskless lithography tools, processes, and cost. Gallais reports from the IMAGINE workshop held September 6 in Tokyo.
David K. Lam, Multibeam, summarizes the gap between today
Brion Technologies, a division of ASML, uncrated Tachyon MB-SRAF (Model-Based Sub-Resolution Assist Features) for its Tachyon computational lithography platform.
Applied Materials (AMAT) unveiled its Centura Tetra EUV advanced reticle etch system at the SPIE BACUS conference. Amitabh Sabharwal, GM, mask etch products, talks about the product's technical specs, and how it overcame EUV challenges.
Argonne Lab researchers have created an e-beam lithography process that boosts resist layers to eliminate the hard mask application. It results in more precise features and deeper etch for semiconductor, solar energy, and other products.
OPC technologies use aggressive assist features with sub-80nm features on the mask to offer improved process window, and therefore yield. MB-MDP, coupled with new-generation mask-writing equipment, produces overlapping e-beam shots that result in lower shot count.
Light source supplier Cymer Inc. (Nasdaq:CYMI) launched SmartPulse, which monitors light source parameters at the wafer, collecting data for a suite of reporting and analysis tools.
Jan Willis from the eBeam Initiative summarizes the group's annual event at SPIE BACUS 2011, with presentations on both improving wafer quality and mask write times at the 20nm node. Other presentations dealt with EUV masks and a lack of funding support.
Bryan Rice, SEMATECH's newly appointed director of strategic initiatives, tells SST what his new job entails: what he sees as his biggest challenges, which areas will keep SEMATECH's main attention (hint: the "once and future king" of resources), and what new areas are being explored.
Dr. Stefan Wurm, newly appointed director of SEMATECH's lithography program, tells SST what areas continue to be top-priority to SEMATECH, where progress is being made, and how SEMATECH's pursuits are changing along with its membership base.
Engineers at the NIST Center for Nanoscale Science and Technology (CNST) NanoFab have developed a plasma etch/argon process that improves etch rate, mask selectivity, and the sidewall profile of silicon structures.
Extreme ultraviolet (EUV) lithography introduces new patterning distortions -- flare along with proximity effects -- that must be accurately modeled and corrected on the reticle. James Word and Christian Zuniga of Mentor Graphics discuss an all model-based approach to flare compensation.
GLOBALFOUNDRIES successfully taped out a 20nm test chip using flows from Cadence Design Systems, Magma Design Automation, Mentor Graphics Corporation, and Synopsys Inc. GLOBALFOUNDRIES customers can now begin evaluating their 20nm semiconductor designs.
Robert Newcomb from Qcept explains the two types of customers for inspection technology and their different needs: those on the leading edge who want yield improvements, and mainstream fabs seeking a better yield/cost mix on older processes.
Scott Zafiropoulo explains Ultratech's business and positioning strategies in an interview at SEMICON West, including how the company weathers market cyclicality and prepares for a 450mm wafer-size transition.
Doug Anberg, VP of advanced stepper technology at Ultratech, discusses the physics behind improvements in the company's new Sapphire 100E HB-LED tool in a video interview at SEMICON West 2011.
Leti's Serge Tedesco, lithography program manager, provides an update on the research group's 193 optical lithography program for 22nm and below, and exploration of multi e-beam lithography techniques.
SEMATECH appointed Dr. Stefan Wurm as the consortium's director of lithography, responsible for the strategic direction of SEMATECH's Lithography program, particularly worldwide EUV infrastructure development.
Reporting from this week's SPIE BACUS Photomask Technology conference, Franklin Kalk from Toppan Photomasks picks through the "10 best" papers that were to have been presented at Photomask Japan earlier this year.
D2S announced a mask-wafer double simulation accelerated workstation, TrueMask DS, for R&D exploration, bit-cell design, hot-spot analysis and mask defect categorization. Aki Fujimura, CEO, D2S, speaks with ElectroIQ's Debra Vogler about the technology, and what makes 20nm different.
Materion Advanced Materials Technologies acquired EIS Optics Limited, adding a 97,000sq.ft. manufacturing site in Shanghai, China for optical coatings. EIS Optics makes optical thin film filters, glass processing, lithography and optical subassemblies.
JSR Micro and CEA-Leti will partner to develop sub-20nm next-generation lithography materials and processes, focusing on pitch division in 193nm optical lithography for <20nm logic applications and on direct-write maskless lithography (ML2) technology.
A deep dig inside ASML's 3Q11 results and execs' commentaries unearths insights into 4Q11 and 2012 projections, an updated EUV timeline, and some curious disconnect about the industry's 450mm readiness.
Imec and tool vendor ASML have signed a new 5-year deal to continue collaboration on lithography technologies, both immersion and EUV, as well as associated components -- including new sensors to help calibrate lens alignment and dose.
The Semiconductor Industry Association (SIA) elected Freescale Semiconductor CEO Rich Beyer as its 2012 chairman. This will be the SIA's 35th year.
USHIO INC.'s wholly owned subsidiary, XTREME technologies GmbH, achieved 30W output at an intermediate focus under a duty cycle of 100% for high-volume extreme ultraviolet (EUV) lithography.
Two Wall Street analysts report their impressions from last week's EUV Symposium (Oct. 17-19 in Miami), where companies in the EUV supply chain reported their latest results and planned progress through 2012. And don't look now but there's a competition brewing in source power.
Stefan Wurm, director of SEMATECH's lithography program, relayed highlights from last week's EUV Symposium (Oct. 17-19 in Miami), including results in defects (mask blanks and substrates) and an update on SEMATECH's EUV Mask Infrastructure (EMI) program.
Photomask costs are a painfully visible issue in today's competitive semiconductor market. This puts substantial pressure on the profitability of photomask makers. Since the "mask makers' vacation" ended some 15 years ago, it seems every paper you read has another exorbitant estimate of future mask costs.
Carl Zeiss says it has delivered "a complete optical system for production-ready EUV" in an ASML tool. The entire completed system with projected 60 wafers/hour throughput is expected in 2H10 targeting 20nm node manufacturing.
This article from Molecular Imprints describes how te addition of patterned media to HDD disk fabrication presents a number of new challenges to magnetic media manufacturers, and how J-FIL systems and materials can provide the foundation for successful high-volume manufacturing.
Ultratech execs Art Zafiropoulo and Jeff Hebb update SST on the status of laser-spike anneal (LSA) technology: readiness for 32nm, extendibility to 22nm, and evaluation for 16nm and beyond.
September 14, 2009 - KLA-Tencor exec Dan Lopez gives SST a preview of its new Teron 600 Series mask defect inspection system, with programmable scanner-illumination capability and improvements in sensitivity and computational lithography power to address a major transition in mask design at the 2Xnm logic (3Xnm half-pitch memory) node.
Several papers presented at last week's SPIE/BACUS Symposium described the mastering, replication and metrology challenges of patterned media, writes Toppan Photomasks' Franklin Kalk, reporting exclusively for SST.
Reporting exclusively for SST, Toppan Photomasks' Franklin Kalk reviews papers from the SPIE/BACUS Symposium that mapped nanoimprint lithography's intersection with patterned hard-disk media, and discussed how to resolve the key technical issues that have prevented its traction in semiconductor manufacturing.
E-beam direct write lithography using character projection capability has the potential to enable maskless production for systems-on-chip at leading-edge technology nodes. Advantest and D2S describe their collaborative work that yielded a 4× increase in the number of characters available on EBDW stencil masks, a key factor in achieving the throughput increase needed to make maskless SoCs practical.
Toshiba Corp. says it has developed a high-resolution photoresist specifically for extreme ultraviolet (EUV) lithography, viable to the 20nm-scale generation.
Microbubbles in leading-edge photoresist materials can distort the exposure pattern and affect yield, sometimes even if proper steps are taken. Entegris' Jennifer Braggin discusses results of a study in which positive pressure applied on the chemistry before the dispense nozzle reduces microbubbles in top anti-reflective coating (TARC).
Frank Bok Namgun and Philippe Cochet from Azores discuss the various cost-of-ownership merits of steppers vs. scanners in photolithography for flat-panel displays, including capital equipment and mask costs.
Microbridging defects have emerged as one of the top yield detractors in immersion lithography at the 32nm node and beyond. This study from Entegris, IMEC, and Sokudo examines the effect of point-of-use filtration and how it is best used to mitigate microbridging defectivity.
Scaling will continue to follow the Moore's Law pace and will continue to rely on silicon to the 11nm node and beyond, although the emergence of fully depleted devices will disrupt device architectures, predicted Ghavam Shahidi from IBM research division, in a talk at this week's International Electron Devices Meeting (IEDM).
ASM International NV has licensed key processes and material IP to the Air Liquide Group, related to deposition of advanced ultra-high-k insulator films such as yttrium-doped zirconia, STO, and BST, used most recently as gate insulator material in logic manufacturing.
Samsung Electronics says it has begun focusing its R&D on advanced logic process development for its foundry business, leveraging synergies with its memory development and work with partners and consortia.
Taiwan's Industrial Technology Research Institute (ITRI) will add Applied Materials to its partners for developing 3D chip stacking technology, by placing "a full line" of AMAT processing tools in its labs.
Enhancing flows when moving manufacturing into IC design
With the move to more advanced semiconductor manufacturing technologies, semiconductor companies are finding that modifications to physical design data meant to improve yield can seriously impact integrated circuit (IC) performance and functionality. As a result, IC design houses are focusing growing attention on manufacturing effects at the earliest possible stages of IC design....
Outlook for EUVL manufacturing insertion
Extreme ultraviolet (EUV) technology maturity must be demonstrated by the performance of the first EUV lithography (EUVL) alpha tools, by the readiness of EUVL infrastructure to support beta-level EUVL lithographic performance in the near future, and by the overall cost of ownership (CoO) of EUVL. ...
Processing and characterization of a positive thick photoresist
OVERVIEW There is increasing interest in the thick, positive, epoxy-based photoresist made of the material AZ P4620 because of its wide applications in micro-fluidic devices and micro-electromechanical systems (MEMS). The optimization of polymerization for this material under near ultraviolet (UV) lithography...
Japan: Addressing the challenges of next-generation litho track systems
Dainippon Screen Mfg. Co. Ltd. and Applied Materials Inc. formed the Sokudo semiconductor coat/develop track joint venture in July 2006 to develop new track technologies that will enable users to meet the challenges of next-generation lithography processing. Sokudo's goal is to offer users competitive and technically differentiated track products that can help keep the semiconductor industry on its roadmap to smaller linewidths.
Imaging of lines and contact holes using ArF immersion at 0.85NA
193nm immersion lithography has become the industry's prime choice for printing critical layers in 45nm node processes. In a research facility, through-pitch imaging solutions for 65nm lines and 80nm contact holes were explored using a preproduction 193nm immersion scanner with a numerical aperture (NA) of 0.85.
While exotic properties of materials in the nanozone (1-100nm) promise a host of new devices and applications, success in the marketplace will depend on making tough choices and focusing on developing products offering sustainable profits.
With 65nm production ramping, the focus at SEMICON Japan in December turned to cutting-edge technology for 45nm production and 32nm development, leaving lithography suppliers in the unenviable position of midwifing two new exposure technologies into production at once.
Each year, experts gather at the SPIE Advanced Lithography Symposium in San Jose to report on their pursuit of Moore's Law. Every two years, a new node in the ITRS is reached, and 2007 is the year for 45nm technology production. Many presentations at SPIE showed the 45nm node in production, as scheduled, using 193 immersion lithography, while other presentations looked further ahead...
March 13, 2007 - Kicking off the 20th annual Conference on Optical Microlithography last week during SPIE, TSMC's lithography guru Burn Lin wove a tale that began as a history lesson, but shifted to a modern message tackling today's top lithography challenges. The common thread throughout: "The devil is in the mask."
The traditional Exposure Systems and Components session on the last day of the SPIE Advanced Lithography Symposium gave vendors the opportunity to tout their latest hyper-NA immersion scanners and supporting technologies.
First-generation resist systems for immersion lithography employed a topcoat material to protect the resist and prevent leaching of resist components that might damage the optics. By making the topcoat surface hydrophobic and controllable, topcoat materials suppressed defects and facilitated rapid wafer scan.
The VLSI Symposium meeting this year (June 1214, Kyoto, Japan) revealed there will be not one, but many different solutions for the production implementation of hafnium-based oxides at the 45nm node and beyond, with Hf-based dielectric k values varying from a "medium"-k (812) up to a true high k of 2224. The gate electrode for some companies will remain poly ...
Arrays of 100nm contact holes can be printed with adequate depth of focus (DOF) through pitch using dry 193nm wavelength exposure and a special illuminator design.
Contact holes are among the most difficult IC structures to pattern. The design rule for nested holes patterns at the 65nm-node generation assumes a spacing almost the same as the wavelength used in ArF lithography.
The tradition of the ISMI Manufacturing Symposium as an "in the trenches" conference, by and for the people doing the actual day-to-day work in the fabs, continued Oct. 24-25 in Austin, TX. Particular attention was given to topics on yield improvement/productivity methodologies, ESH, and sustainability. Specific talks included how to fix litho "hot spots," cleaning wafer chucks without DI water or solvents...
ALD: A market and technology update
By J. Robert Lineback, Senior Technical Editor
With no "showstoppers" identified yet in immersion lithography, rival scanner makers ASML, Canon, and Nikon are accelerating efforts to take 193nm "wet" exposure tools to the next level, quickly pushing numerical aperture lenses to their feasible limits in systems using water to boost depth of field and resolution for 65nm and 45nm processes.
By J. Robert Lineback
The first wave of production-worthy 193nm immersion scanners now appears to be a shoo-in for at least part of the 65nm process generation and probably the entire 45nm node at decade's end, but industry managers and researchers speaking at the annual SPIE International Symposium on Microlithography attempted to rein in some of the unbridled enthusiasm with...
Immersion lithography's next wave of tools targets 'hyper-NA' and high 300mm throughput
With no 'showstoppers' identified yet in immersion lithography, rival scanner makers ASML, Canon, and Nikon are accelerating efforts to take 193nm 'wet' exposure tools to the next level, quickly pushing NA lenses to their feasible limits in systems using water to boost DOF and resolution for 65nm and 45nm processes.
Solid State Technology has collaborated with leaders in various technical working groups of the 2004 International Technology Roadmap for Semiconductors (ITRS) to highlight the most significant updates in the new edition of the Roadmap, as well as major challenges to be addressed in the 2005 revision.
The next big step for development of 193nm immersion lithography will be fully equipped R&D pilot lines, expected to be operational in early 2005. These pilot lines will define immersion-related defectivity issues in functioning devices.
Out of the blue comes an unexpected milestone in immersion lithography. IBM Corp. has plunged ahead and used a 193nm immersion scanner to print an interconnect layer on fully functional 64-bit microprocessors to prove that adding water to lithography really works.
Will an industry that expects optical exposure tools to print more than 100 300mm wafers/hour embrace $20 million lithography systems with throughputs below 5 wafers/hour if they don't require costly masks? If so, at what node? These were two of the questions that 110 participants tried to answer at the first Sematech Maskless Lithography (ML2) workshop, held January 17-19 in San Jose, CA.
Integration issues pose challenges for fabs, foundries, and fabless
Fabs are filling dielectrics with air bubbles, sunning them under UV lamps, and putting on caps to keep molecules in place, but after a decade of development, really low-k (k<3) still has not made it into volume production.
Narrowing process windows, emerging tools for statistical analysis of design, and model-based simulations of yield results may soon push designers to actually design for manufacturability, argued experts at Semi's Strategic Business Forum in Welches, OR, May 9-11.
Automated micro-defect monitoring for 300mm lithography
As the semiconductor industry continues to push toward the 90nm node, controlling defect density in the lithography cell becomes ever more critical to the success of the overall manufacturing process. MORE
Positive versus negative resist
Simulations imply that narrow resist lines print best with a positive tone resist process while narrow trench geometries are best with a negative tone process, even if the resist performance parameters are unequal. Simple development bias models appear to capture... MORE
Finding the limits of chemically amplified photoresists