Mentor-Graphics

Topic Index

A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 0-9


Looking for an integrated post-tapeout flow

Wed, 2 Feb 2013

Dr. Steffen Schulz discusses the role of a flexible platform for computational lithography in a successful business strategy.


Innovations in computational lithography for 20nm

Tue, 1 Jan 2013

Several innovations in computational lithography have been developed in order to squeeze every possible process margin out of the lithography/patterning process.  In this blog, Gandharv Bhatara of Mentor Graphicsl talks about two specific advances that are currently in deployment at 20nm.


DFM Services in the Cloud

Wed, 2 Feb 2013

Joe Kwan is the Product Marketing Manager for Calibre LFD and DFM Services at Mentor Graphics. He is also responsible for the management of Mentor’s Foundry Programs. He previously worked at VLSI Technology, COMPASS Design Automation, and Virtual Silicon. Joe received a BA in Computer Science from the University of California Berkeley and an MS in Electrical Engineering from Stanford University.


The secrets of 14nm lithography

Thu, 3 Mar 2013

The long-expected demise of optical lithography for manufacturing ICs has been delayed again, even though the technology itself has reached a plateau with a numerical aperture of 1.35 and an exposure wavelength of 193nm. Immersion lithography is planned for the 20/22nm node, and with the continued delay of EUV, is now the plan of record for 14nm.


Rebirth of mask process correction for better wafer lithography

Wed, 7 Jul 2013

Who knew that mask process correction (MPC) would again become necessary for the manufacturing of deep ultraviolet (DUV) photomasks?


Model-based hints: GPS for LFD success

Wed, 10 Oct 2013
For several technology nodes now, designers have been required to run lithography-friendly design (LFD) checks prior to tape out and acceptance by the foundry. Due to resolution enhancement technology (RET) limitations at advanced nodes, we are seeing significantly more manufacturing issues, even in DRC-clean designs.

Plug-and-play test strategy for 3D ICs

Tue, 3 Mar 2014
Three-dimensional (3D) ICs, chips assembled from multiple vertically stacked die, are coming. They offer better performance, reduced power, and improved yield.