Wafer-Level-Packaging

Topic Index

A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 0-9


Alchimer CEO Predicts Demise of Vapor Deposition Processes for TSVs by 2009

Tue, 3 Mar 2008
(March 17 2008) Massy, France — After being appointed CEO of Alchimer SA, Steve Lerner immediately predicted the demise of vapor deposition processes for depositing nanoscale films in through silicon vias (TSVs) within a year. Steve Lerner is a technologist with 29 years' experience in semiconductor development and manufacturing. He founded advanced packaging and device companies Alpha Szenszor, GigSys, and CS2, and has held executive positions at Amkor, Swire, and AME.

Solder Ball Transfer for Flip Chip and WLCSP

Sun, 3 Mar 2008
By Andrew Strandjord, PacTech USA
(March 19, 2008) — Wafer bumping is often separated into two different categories: flip chip bumping and wafer-level chip scale packaging (WLCSP). This categorization and affiliated nomenclature is mainly based on solder bump size and the type of equipment used to create them. "Flip chip" refers to bumps on semiconductor wafers in the range of 50-200 µm in height. "WLCSP" refers to bumps that are in the range of 200-500 µm.

U.S. Computer Maker to Use Dow Corning Compound at China Facility

Fri, 3 Mar 2008
(March 14, 2008) Midland, MI — A U.S.-based personal computer maker has qualified Dow Corning's TC-5121 thermally conductive compound for use in its manufacturing operations in China. TC-5121, introduced in December, is designed for mid-range electronic systems such as desktop computers and graphic processing units.

BTU Receives $3M Order for Pyramax Products from Leading SATS Company

Tue, 3 Mar 2008
(March 11, 2008) North Billerica, MA — BTU International, a supplier of advanced thermal processing equipment for the alternative energy and electronics manufacturing markets, today announced the receipt of a $3M multiple-machine order, the largest single Pyramax order in company history, from a leading semiconductor assembly and test subcontractor (SATS).

SMTA Announces "Best of Conference" Award for Pan Pacific 2008 Symposium

Fri, 3 Mar 2008
(March 7, 2008) Minneapolis, MN — The SMTA has announced "Best of Conference Awards" to two presenters from this year's Annual Pan Pacific Microelectronics Symposium and Tabletop Exhibition, held in late January in Hawaii. These awards are chosen by attendee ratings.

Thin-film TECs for High-heat Flux Rapid Thermal Response

Mon, 3 Mar 2008
By Paul A. Magill, Nextreme Thermal Solutions, Inc.

(March 5, 2008) — In the semiconductor industry, device characterization or screening occurs through the use of two related tests: burn-in and elevated temperature device characterization, with both tests using temperatures >99°C: the first to accelerate device failure modes that could be related to those in the field, and the second to simulate functional device behavior while characterizing its performance level.

MicroScale begins bumping services in Korea

Tue, 1 Jan 2002
MicroScale Co. Ltd., Korea's largest chip bumping house, has begun to operate a bumping line for semiconductor chips

The MEPTEC and Advanced Packaging Technologists of the Year Award

Tue, 1 Jan 2002
The Third Annual Microelectronics Packaging Technologist of the Year Award, sponsored by the Microelectronics Packaging and Test Engineering Council (MEPTEC) and Advanced Packaging magazine, was presented in October during a special MEPTEC luncheon

Time flies

Tue, 1 Jan 2002
We take great pleasure this year in celebrating the 10th anniversary of Advanced Packaging. Yes, it was way back in 1992 when AP hit the streets

10th Anniversary Insights
A short history of wafer-level packaging

Mon, 4 Apr 2002
There have been only a few fundamental shifts in the history of electronic packaging that changed the whole industry. One was the step from through-hole assembly to surface mount technology (SMT)

Plexus licenses Tessera technology

Mon, 4 Apr 2002
Plexus Corp., an electronic manufacturing services (EMS) provider, will be licensing Tessera's chip scale packaging (CSP) and multichip packaging (MCP) technology

SECAP spreads the word with APiA launch

Mon, 4 Apr 2002
SECAP, the Semiconductor Equipment Consortium for Advanced Packaging, is in its second year now with some interesting projects underway

BGA, CSP and flip chip

Sat, 6 Jun 2002
When to use which process, and why

Special needs of large flip chip being addressed

Sat, 6 Jun 2002
ASE Test Limited and MTBSolutions (MTBS) announced that they are jointly developing packaging technology for large flip chip devices

10th Anniversary Insights
The Evolution of Packaging Education

Thu, 8 Aug 2002
The first university course in packaging was offered nearly two decades ago, but the most significant changes in availability and breadth of university-level education programs have occurred in the past 10 to 15 years

APiA Adds Seven Members to Alliance

Thu, 8 Aug 2002
The Advanced Packaging and Interconnect Alliance (APiA) added seven organizations to its roster, increasing the scope of technologies included in its effort to address advanced packaging challenges

The back-end process: Step 7 - X-ray inspection

Mon, 7 Jul 2002
Flip chip challenges

Who Needs a Dog That Doesn't Bark?

Mon, 12 Dec 2003
My wife and I have always been Sherlock Holmes fans. While not as exciting as Harry Potter, who can forget those old Basil Rathbone black-and-white episodes, or the newer ones starring Jeremy Brett and his slicked-back hair?

Is Packaging Leading the Return of Semiconductor Growth?

Fri, 8 Aug 2003
It appears that past history again may be an indicator that growth is returning to the semiconductor industry. In our cyclic world of semiconductors, an increase in sales for the outsourcing of packaging and test services usually has been an early indicator that the industry has bottomed and a return to growth is on the way.

Productivity Enhancements in Advanced Packaging Lithography

Tue, 7 Jul 2003
The need for faster devices and smaller form factor has resulted in a prolific adoption of advanced packaging techniques. As semiconductor devices continue to migrate to smaller features, higher frequencies, higher power densities and lower voltages, the industry requires an aggressive packaging technology roadmap.

Multi-functional Dispensing for Semiconductor Back-end Packaging

Tue, 7 Jul 2003
Liquid dispensers have long played an essential role in printed circuit board (PCB) assembly.

Functional tuning of hybrids

Tue, 1 Jan 2002
Functional laser tuning of traditional ceramic-based hybrid circuits has been accomplished with the use of a standard 1.064-µm wavelength Nd:YAG laser for more than two decades

Leadframe Chip Scale Packaging

Tue, 7 Jul 2003
The proliferation of new packaging families and variations today is more rapid than ever before.

Quarterly Reports Show Few Bright Spots For Sub-contractors

Tue, 7 Jul 2003
For the most part, the good news still has not arrived in the packaging and test sub-contractor world.

Front End, Back End and a Little of the Middle

Tue, 7 Jul 2003
Now that SEMICON West is upon us the idea of back-end and front-end points out the separation of each step of electronics packaging. Each step in the process sometimes becomes so removed from the mainstream that engineers may lose sight of how an understanding of the whole benefits each step.

The back-end process: Step 5 - Flip chip attach
Process and material options

Wed, 5 May 2002
Flip chip is a technology where semiconductor devices are mounted and electrically connected face-down directly onto substrates

10th Anniversary Insights
The evolution of the subcontractor

Wed, 5 May 2002
The role and status of the packaging, assembly and test subcontractor has steadily increased over time

Reliability Requirements for Portable Electronics

Wed, 10 Oct 2003
Chip scale packaging (CSP) has been driven primarily by the small form factors required for portable electronics and other high-density semiconductor applications. It has been shown that reliability requirements can be met in spite of the design constraints imposed by these applications. Even when the form factor dictates a stacked approach, ultra-thin CSPs can be stacked and still meet — and exceed — the physical and reliability requirements.

Assembly Processes for Flip Chips on Substrates

Sat, 11 Nov 2003
Flip chip assembly is a key capability to enable product miniaturization. Our previous studies have investigated several flip chip interconnection types, including anisotropic conductive film or paste, and Au-Au thermosonic bonding. This project focuses on the assembly of 0.200- and 0.250-mm-pitch solder flip chip devices.

Next-generation Electronics Packaging Using Flip Chip Technology

Sat, 11 Nov 2003
There is a rapid increase in the number of electronic packages using flip chip technology. With the ongoing expansion of the Internet, mobile phones, PDAs, desktop computers and laptops, digital camcorders, digital cameras and other electronic-based consumer products, the flip chip revolution is in full swing.

Design your own ASIC

Mon, 9 Sep 2003
The potential of 90 nm application-specific integrated circuit (ASIC) designs is introducing new packaging challenges that threaten the IC designer's ability to take full advantage of this advanced process technology.

Award Winners

Mon, 9 Sep 2003

AP Award Program Sees Another Successful Year

Mon, 9 Sep 2003
Innovation again took center stage at Advanced Packaging's 2003 Advanced Packaging Awards Ceremony, held July 16 in conjunction with SEMI and the back-end portion of SEMICON West.

10 years ago in Advanced Packaging

Wed, 5 May 2002
In the very first issue of Advanced Packaging, thermal management was probably the biggest topic

Updates on folded flex and thin packaging at ICAPS

Wed, 5 May 2002
IMAPS held its first International Conference on Advanced Packaging and Systems (ICAPS) in March in Reno

New opto packages announced at OFC

Wed, 5 May 2002
The Optical Fiber Conference (OFC) in Anaheim in March included announcements of many new packaging technologies and products

IEEE's CPMT announces winners

Wed, 5 May 2002
Pisctaway, N.J. - The Components, Packaging and Manufacturing Technology Society (CPMT) of the IEEE recently announced the winners of its annual awards for technical excellence, achievement, leadership and service.

New Products

Wed, 5 May 2002
The FXS-160.40 inspection system is designed for off-axis inspection of planar devices

Plus or minus 10 years

Wed, 5 May 2002
While putting together our 10th anniversary issue, it was great fun to look through old issues of Advanced Packaging to see what has changed and what hasn't in the past decade

Progress on wafer-level burn-in and test

Fri, 2 Feb 2002
Motorola Semiconductor Products Sector (SPS) has developed and qualified the industry's first wafer-level burn-in and test (WLBT) process for high-performance flip chip microprocessors

New alliance to accelerate advanced packaging

Fri, 2 Feb 2002
A group of seven companies have begun a collaboration to accelerate the commercial development of advanced packaging technologies, such as wafer-level packaging (WLP)

Flip chip defect detection

Fri, 3 Mar 2002
Acoustic micro imaging and destructive correlation

MEPTEC MEETING REPORT

Fri, 3 Mar 2002
Intel's Packaging Plans Discussed

SEMICON West Technical Talks

Sun, 9 Sep 2002
The technical sessions began with the presentation of the IEEE/CPMT Electronics Manufacturing Technology Award to Scott Kulicke of K&S for his "commitment and dedication" and "outstanding leadership and service.

APiA to Supply ACE Semiconductor, Adds New Members

Sun, 9 Sep 2002
SAN JOSE, CALIF. - The Advanced Packaging and Interconnect Alliance (APiA) has agreed to work with ACE Semiconductor to provide a 200 mm advanced packaging process line in ACE's Shanghai fab

The back-end process: Step 8
Flip Chip Underfill

Thu, 8 Aug 2002
The advantages of the flip chip package over other types of electronic packaging are many, but the most obvious is the reduction in the package size, which delivers savings in board real estate and product thickness.

Lithography for Advanced Packaging

Thu, 8 Aug 2002
With the evolution in front-end semiconductor technology and end product platforms, there is a need for further process development to package these products effectively

die products

Mon, 7 Jul 2002
Standards provide key to progress

Flexible flip chip

Mon, 7 Jul 2002
Solutions for high-performance applications

10th Anniversary Insights
New (?) and emerging (?) technologies

Mon, 7 Jul 2002
Today, packaging and assembly of integrated circuits (ICs) can be characterized as an aggressive ongoing development effort

Database for die products

Mon, 7 Jul 2002
To assist design engineers working with bare die, the Die Products Consortium (DPC) has created a database of information on available die products

UTAC establishes US design center

Mon, 7 Jul 2002
United Test and Assembly Center (UTAC) is setting up a package design center in Pleasanton, Calif., to support the design needs of customers in North America

CSPs, stacked packaging proliferate

Mon, 7 Jul 2002
Several announcements by major semiconductor manufacturers indicate the extent to which advanced packaging technologies have permeated mainstream products

Advanced Packaging added to Chemical Abstracts Service

Mon, 7 Jul 2002
The American Chemical Society has selected Advanced Packaging for inclusion in its Chemical Abstracts Service (CAS)

Packaging TidBiTS

Tue, 3 Mar 2007
With the 8th annual Burn-in Test and Socket Workshop (BiTS) coming up March 11–14 in Mesa, AZ, Advanced Packaging collected news, events, and products around the industry focused on test, sockets, and the BiTS event. Meet the Press at BiTS, March 12, to learn more about editorial submissions, and the variety of publishing opportunities available to the industry.

High-accuracy Bonder

Tue, 5 May 2007
The KADETT semi-automatic device bonder, designed for R&D labs, university research, and pre-production environments, performs high-accuracy placement and bonding processes for advanced packaging, MEMS, and other assembly tasks.

Rogers Highlights High-frequency at IMS

Fri, 5 May 2007
(May 25, 2007) ROGERS, CT — Rogers Corporation will exhibit specialty materials for the high-frequency market at IEEE MTT-S International Microwave Symposium (IMS), June 5–7 in Honolulu, HI, at Booth 843. Offerings include advanced packaging materials, copper bond technology, and antenna-grade materials.

STATS ChipPAC Builds R&D for Packaging Technologies

Wed, 5 May 2007
(May 16, 2007) SINGAPORE — STATS ChipPAC Ltd. will establish a Singapore R&D facility for through-silicon via (TSV), microbumping, die embedding, and advanced substrate technologies to create advanced packages. Core operations will focus on wafer-level processing and advanced wafer integration.

Amkor, UTAC to Cross-license Packaging

Tue, 5 May 2007
(May 15, 2007) CHANDLER, AZ and SINGAPORE — Amkor Technology, Inc. (Chandler), and United Test and Assembly Center Ltd. (UTAC — Singapore) entered a multi-year cross-licensing agreement wherein UTAC will adopt Amkor's MLF technology and Amkor will use UTAC's QFN patents. The deal covers intellectual property rights (IPR) and transfer of associated packaging technologies.

AMD Orders Flip Chip Equipment

Tue, 5 May 2007
(May 15, 2007) RADFELD, Austria — AMD Penang ordered its first Datacon 8800 FC Quantum flip chip bonder, and is expected to add more in the coming months, to began producing single- and multi-flip chip assemblies for high-end processors. This marks Datacon's first order for flip chip equipment from an integrated device manufacturer (IDM).

SEMX Names Executive VPs

Tue, 5 May 2007
(May 15, 2007) ARMONK, NY — SEMX Corporation, the parent company of Semiconductor Packaging Materials (SPM), appointed Paul Nikac and Vito Tanzi as executive vice presidents of the corporation, following Kenneth J. Huth's retirement.

IITC Celebrates 10 Years

Fri, 5 May 2007
(May 4, 2007) SAN FRANCISCO, CA — The IEEE International Interconnect Technology Conference (IITC) began 10 years ago in 1997 in response to IBM's copper interconnection technology ramp. The forum, June 4–6 in San Francisco, presents R&D work on semiconductor processing, advanced materials, equipment development, and interconnect systems for scientific, engineering, and related industries.

TSMC Approves WLP Plan

Wed, 8 Aug 2007
(August 15, 2007) TAIPEI, Taiwan — TSMC board members approved a proposal for capacity investments leading to 300-mm wafer-level packaging (WLP) production capability. The investment equals $59.8 million in capital appropriation. It is designed to reduce form factor for more competitve end products.

JV Installs SUSS Coater/Developer

Tue, 8 Aug 2007
(August 14, 2007) MUNICH, Germany — SUSS MicroTec delivered a 200-mm Gamma production coating and developer cluster to HD MicroSystems, LLC (Wilmington, DE), to support the company's polyimide and PBO material technologies. HD MicroSystems is a joint venture (JV) of Hitachi Chemical Co. Ltd. and DuPont Electronic Technologies. It will use the production cluster to support expansion into advanced packaging markets, said John Malloy, U.S. marketing and sales manager, HD MicroSystems.

Investors Back Vietnam Packaging

Mon, 8 Aug 2007
(August 6, 2007) PALO ALTO, CA — Several Silicon Valley companies invested as much as $200 million to launch a packaging plant in Hanoi, Vietnam. The company, Vietnam-Chipscale Advanced Packaging Services (V-Caps) will involve executives from the Silicon Valley region and the local industry in Vietnam, and could employ up to 1,500 workers initially.

Henkel Adds N.A. Distributor

Fri, 8 Aug 2007
(August 3, 2007) IRVINE, CA — Henkel Corporation partnered with Production Automation Corporation (PAC), extending its distribution network in the U.S. and Mexico. PAC will market and support Henkel's Hysol, Loctite, and Multicore electronics assembly and semiconductor packaging materials.

Outsourced Packaging Outgrowing In-house

Fri, 8 Aug 2007
(August 3, 2007) WELLESLEY, MA — BCC Research finds, in "The Global Market for Advanced Electronic Packaging," the outsourced semiconductor packaging and test (OSPT) services sector outpacing conventional in-house package-and-test in growth, though outsourcing remains a $16.2B industry compared to $23.3B done in-house. The overall package-and-test market will grow from $38.5B in 2006 to $57.6B by 2011, according to the report.

Stacked Flip Chip Package

Mon, 6 Jun 2007
The Flip Chip PiP combines a baseband digital signal processor (DSP) flip chip with stacked memory and analog devices for a small package-to-die ratio and high I/O with a small footprint. This package-in-package (PiP) suits a range of mobile devices, including cell phones.

SEMICON West Preview

Thu, 6 Jun 2007
SEMICON West will take place July 16–20 in San Francisco, bringing together equipment suppliers, SATS providers, R&D institutes, and related companies in the semiconductor packaging industry to highlight new processes, systems, and packages.

Shaken, Not Stirred: IMAPS N.E. Connects to Bond Theme

Tue, 5 May 2007
By Meredith Courtemanche, assistant editor

IMAPS New England, May 1st in Boxborough, MA, was a regional show with a national feel — a strong technical program, about 70 exhibitors, and approximately 450 attendees checking out booths and listening to detailed keynotes and presentations. The show included a new vendor workshop on the exhibit floor and a Bond, James Bond theme complete with playing cards, tuxedos, and an energetic environment.

Nan Ya PCB Boosts Flip Chip Substrate Line

Fri, 4 Apr 2007
(April 20, 2007) TAIPEI, Taiwan — Nan Ya PCB Corporation added an additional line to its flip chip substrate production capacity, increasing output to 30 million units monthly. The line will produce seven million units, reports Taiwan's China Economic News Service (CENS).

Getter Services for MEMS WLP

Fri, 4 Apr 2007
(April 20, 2007) SANTA BARBARA, CA — Innovative Micro Technology (IMT) began offering getter deposition services of wafer-level packaging (WLP) of MEMS devices, and other components requiring a hard vacuum. In testing, IMT reportedly demonstrated vacuum levels below 10 mTorr for inorganic devices — equal to or better than industry standard.

Tronics Expands MEMS Capabilities

Wed, 4 Apr 2007
(April 18, 2007) CROLLES, France — Tronics Microsystems SA expanded its characterization, assembly, packaging, and testing capabilities with additional space and tools. The expansion will support design-to-manufacturing services, and support its MEMS device supply chain.

Tessera Interconnect Platform Targets Limitations

Tue, 4 Apr 2007
By Françoise von Trapp, managing editor

Tessera Technologies, Inc., launched an interconnection platform intended to address technical limitations of current-generation packaging technologies, such as pitch, profile, performance, reliability, and test capacity. The company expects this technology to become a fundamental building block of next-generation mobile, computing, and consumer electronic products.

Didier Andre To Lead European Operations for NEXX Systems

Wed, 4 Apr 2007
(April 11, 2007) BILLERICA, MA — NEXX Systems, a provider of processing equipment for advanced wafer-level packaging applications, has named Didier Andre as Director of European Customer Operations. Andre will work closely with NEXX's distributor, TELTEC, to strengthen NEXX's position with existing customers and to establish new opportunities in Europe.

Database Targets MEMS Manufacturability

Tue, 6 Jun 2007
(June 19, 2007) MATERIALS PARK, OH — ASM International released its MEMS Materials Database: Packaging Module, a licensed database containing mechanical, physical, processing, and component data for materials selection in MEMS packaging. The database targets improvements to time-to-market, reliability, and design and manufacturing of MEMS devices.

Webinar Spotlights Printing Flip Chip Bumps

Thu, 6 Jun 2007
(June 7, 2007) FRANKLIN, MA — Speedline Technologies will host a webinar July 19, 2007, at 11am EST, focused on the parameters and challenges of stencil printing solder paste to form bumps in flip chip applications. The Webinar will provide process optimization advice and defect examples.

Adhesive for Flip Chip BGAs

Tue, 5 May 2007
The DA-6534 one-part, high-performance thermal adhesive uses silver filler with a silicone-based chemistry to offer flexibility, reliability, and thermal conductivity. It targets thermal management packaging for flip chip BGAs and other advanced components.

WLP Photoresist Descuming with Plasma Treatment

Mon, 2 Feb 2007

By Scott D. Szymanski, March Plasma Systems

Commercially available plasma treatment systems can be used for a variety of wafer-level packaging (WLP) process steps including removal of photoresist residue after development (i.e. descum); organic, metal, and oxide contamination removal; wafer surface cleaning; and other processes. Through various alterations to the plasma chemistry or chamber configurations, these systems meet demanding WLP processing requirements.


Consumers, Integration Dictate Future of MEMS, 3-D Packages

Wed, 1 Jan 2007
(January 24, 2007) LYON, France and PITTSBURGH — The future of MEMS and 3-D packages relies on similar factors — consumer drivers and increased integration — according to industry analysts. 3-D integration will affect MEMS and IC packaging industries, says Yole Développement's "3-D ICs." Advanced packages require acceptance from the consumer market to reach targets for technological advancement, commercialization, and sector revenues.

Plasma, Thermal Partnership Yields Combined Equipment

Tue, 9 Sep 2007
(September 5, 2007) PFAFFENHOFEN, Germany — UniTemp GmbH, in partnership with plasma-finish GmbH, developed a semiconductor processing and packaging system that combines plasma and thermal applications. The resulting plasma-temperature processing oven, Model PTP, features a compact chamber and fast ramp rates.

Flip Chip Adhesive

Tue, 7 Jul 2007
For use in flip chip packaging, EA-6800 and 6900 adhesives are designed for lead-free processing temperatures and fast cure times, respectively. Each adhesive reduces voiding from residual moisture within substrates.

Thin-wafer Handling System

Tue, 7 Jul 2007
A polymeric spin-on coating, WaferBOND HT-250, temporarily attaches device substrates to a carrier substrate, enabling wafer thinning and subsequent processing. It will reportedly permit advanced packaging processes such as the creation of through-silicon vias (TSVs), 3D stacking, and other etching, plating, and follow-on processes.

Gartner Predicts Tempered Expansion

Wed, 7 Jul 2007
(July 25, 2007) STAMFORD, CT — Three semiconductor manufacturing facilities, all in China, began production in the second quarter of 2007; however, generally slow growth in semiconductors will keep the packaging-and-test sector from meeting growth levels set in 2006, according to Gartner Inc.'s report "Semiconductor Packaging, Assembly, and Test Facilities: Worldwide, Q'03 2007."

Die-attach Paste and Flip Chip Underfill
Henkel

Tue, 9 Sep 2007
Hysol QMI708 targets applications with copper leadframes and small footprints. It was developed to attach 2.5- × 2.5-mm and smaller die in QFN and SOIC packages.

FlipChip International Names VP Sales and Marketing for WLP and Bumping Business

Tue, 9 Sep 2007
(September 25, 2007) PHEONIX, AZ—FlipChip International (FCI) announced the appointment of David McComb as global vice president, sales and marketing for its wafer level packaging (WLP) and bumping business. McComb, who joined FCI in 2005 as the director of European business and sales, will assume responsibilities for sales, marketing, and licensing for FCI's activities for international customers.

Wafer Bump Providers Partner

Mon, 4 Apr 2007
(April 2, 2007) COLORADO SPRINGS, CO and JANGYIN, China — Wafer-bumping service provider IC Interconnect (ICI) and Jiangyin Changdian Advanced Packaging (JCAP), which produces solder, gold, and pillar bumps, formed an international alliance to transfer ICI technologies to Asia and JCAP bumping services to North America.

SolVision Nabs IC Inspection Contract

Wed, 2 Feb 2007
(February 28, 2007) BOUCHERVILLE, Quebec — A major Korean semiconductor contract manufacturer (CM) selected AV6010 vision systems from SolVision Inc. for IC package inspection at its assembly and test house. The manufacturer will use multiple systems to inspect packages, including advanced flip chip devices.

SATS Industry Grows 26%

Tue, 2 Feb 2007
(February 27, 2007) STAMFORD, CT — The global semiconductor assembly and test services (SATS) market grew 25.7% in 2006, the fifth consecutive year this sector has exhibited double-digit growth, according to preliminary reports from Gartner, Inc. The SATS industry, the outsourcing portion of back-end packaging, assembly, and test, is propelled by major transitions to advanced packaging, including wafer-level, chip-scale, flip chip, and system-in-package (SiP) methods, said Jim Walker.

Dynaloy, BASF Expand WLP Partnership

Thu, 2 Feb 2007
(February 22, 2007) INDIANAPOLIS and LUDWIGSHAFEN, Germany — Dynaloy LLC and BASF AG entered into an expanded sales and distribution agreement for strippers and cleaners used in wafer-level packaging (WLP) and bumping processes. BASF expects the partnership to broaden its back-end semiconductor market penetration, while Dynaloy is targeting Asian and European markets.

Back-end Process — Wafer Bumping

Tue, 2 Feb 2007
Advanced Packaging Techniques
By Terence Q. Collier, CVInc.

Traditionally, die are electrically connected to the outside world using fine gold or aluminum wires that attach from the die's bond pad to the land of a substrate or PCB. Wafer bumping involves taking those traditional aluminum pads and converting into a format that provides a desirable structure for solder adhesion (bumping). There are a number of new, old, and relatively untested techniques for bumping wafers.

Honeywell to Expand Packaging Materials R&D

Thu, 2 Feb 2007
(February 15, 2007) TEMPE, AZ — Honeywell Electronic Materials will expand its Spokane, WA, R&D center for advanced packaging materials, investing more than $1 million and adding about 85 pieces of equipment. The company plans to develop thermal management, electrical interconnect, and burn-in materials. The construction project is expected to finish by the end of 2007.

Vectron Acquires BiODE, Establishes R&D Center

Tue, 2 Feb 2007
(February 7, 2007) HUDSON, NH — Vectron International, a Dover company, completed its acquisition of BiODE Inc., a fluid-viscosity sensor and viscometer reader designer and manufacturer. The BiODE organization will be integrated into Vectron's sensors and advanced packaging (SAP) business unit. The company will also construct an R&D facility in Westbrook, ME, to facilitate integration of BiODE's core technologies into Vectron products.

Nextreme Introduces Thermal Copper Pillar Bump

Thu, 10 Oct 2007
(October 11, 2007) RESEARCH TRIANGLE PARK, NC — Nextreme, manufacturer of micro-scale thermal and power management products, announces the integration of cooling and power generation into the copper pillar bumping process used in high-volume electronic packaging. This breakthrough in flip chip process technology reportedly addresses two serious issues in electronics today — thermal and power management constraints.

Viscom Buys IR Inspection Line

Fri, 8 Aug 2007
(August 24, 2007) HANOVER, Germany and HILLSBORO, OR — Viscom AG will acquire the MX family of infrared (IR) inspection systems for semiconductor, MEMS, and package inspection from Phoseon Technology. The deal includes intellectual property (IP), product development, licensing, customer base, and employees attached to the inspection line. It will broaden Viscom's offering beyond AOI and X-ray inspection tools, said Volker Pape, co-founder and board member, Viscom.

Nano Micro Facility Installs Vistec VB6

Wed, 8 Aug 2007
(August 22, 2007) WATERVLIET, NY — The Forschungszentrum Karlsruhe independent science and research institute (Germany) began running applications on a Vistec VB6 electron beam lithography system in its Karlsruhe Nano Micro Facility. The system will allow researchers to develop new applications in nanotechnology and microsystems technologies.

DoD Supplements EI's MCM Contract

Tue, 8 Aug 2007
(August 21, 2007) ENDICOTT, NY — The U.S. Department of Defense (DoD) awarded Endicott Interconnect Technologies, Inc. (EI), a $19 million contract modification to existing work, requiring additional multi chip module (MCM) assemblies and equipment. EI provides fully assembled MCMs for a high-reliability, high-performance DoD computing application.

Options in flip chip cleaning

Thu, 11 Nov 2001
Meeting performance and reliability standards

News

Wed, 8 Aug 2001
Zuken addresses time-to-market with predictive analysis tool

What, me worry...?

Wed, 8 Aug 2001
Why are so many upper echelon managers in our industry reluctant to admit what everyone else seems to know: that they have problems in their businesses? Their employees and factory workers, their suppliers and even their competitors know that they have problems

Think TANK

Sat, 12 Dec 2001
Four prominent trees grew on the perimeter of the city's Circular Park. The path due south from the cypress tree to the dogwood tree intersected the path due west from the baobab tree to the acacia tree at the Lion Fountain

LSI Logic licenses flip chip technology to AIT

Sat, 12 Dec 2001
LSI Logic Corp. and Advanced Interconnect Technologies have signed a licensing agreement under which AIT will license LSI Logic's organic laminate flip chip FPBGA technology

KGD MEETING REPORT

Sat, 12 Dec 2001
SIPs at forefront of KGD Packaging and Test Workshop

IMAPS meeting Report

Sat, 12 Dec 2001
The exhibit floor at the IMAPS Symposium was not exactly packed, but most conference attendees thought that the turnout and content made it worthwhile

Wafer-level Packaging and Test, Technologies and Trends

Fri, 11 Nov 2002
The term "wafer-level packaging" (WLP) entered the microelectronics industry's lexicon in the late 1990s.

New (ad)ventures in Asia

Thu, 2 Feb 2001
Excitement abounds here at Advanced Packaging magazine whenever we work on something new. While each and every month we deliver a new magazine to your desk, lately we have also been working on some other projects related to the magazine

WLP power components shrink portable equipment

Thu, 2 Feb 2001
New power and protection devices in wafer-level packaging (WLP) are aiding in the overall reduction of size and weight of portable equipment products

The Back-end Process: Step 2 - Die Placement

Thu, 2 Feb 2001
The expansive growth rate of flip-chip in packaging (FCIP) continues to task flip chip attach (FCA) equipment suppliers with new challenges

Advanced Packaging launches Asia edition

Mon, 1 Jan 2001
NASHUA, N.H., AND Taipei, TAIWAN - PennWell Publishing and Arco Publishing have recently launched a Chinese/English language edition of Advanced Packaging magazine

Alice and Her Daughters

Mon, 1 Jan 2001
One day recently, out of the blue, my sister Alice made this remark about her three daughters and herself

Pursuing excellence

Thu, 3 Mar 2001
There are a few things I can count on hearing when I talk it up with folks in the industry. Among the general niceties people bestow upon us, there is always a mix of good questions, such as "When are you going to cover such-and-such topic?" and "Does this product really work?"

Nuclear particles and the green movement

Fri, 6 Jun 2001
The most common modern use for lead is in solders for electronics manufacture because of lead's low melting point and corrosion resistance. Historically, lead has been used in a wide variety of ways for thousands of years

A second chance to do it right

Fri, 6 Jun 2001
Historically, a rite of passage for a semiconductor packaging professional was the realization that packaging was an afterthought or seen as a necessary evil-or worse-in the IC world. Packaging added cost and leadtime, and more often than not it ruined some perfectly good chips

Industry experts speak on WLP and co-design

Sun, 12 Dec 2002
The editors of Advanced Packaging and Solid State Technology magazines conducted an exclusive survey of key figures in the semiconductor manufacturing industry. We gathered input on two critical areas of front and backend convergence ? WLP and chip/package co-design. Following is what the industry experts had to say.

Think Tank

Sun, 12 Dec 2002

Kicking off 2001

Mon, 1 Jan 2001
Beginning a new year always conjures up all sorts of resolutions... organizing your desk (because it might be condemned by the local fire marshal)...eating the "right" foods (we'll bypass the whole dieting thing altogether)...maybe even setting aside more savings (so we can retire sooner?)

CSP and flip chip underfill

Fri, 6 Jun 2001
Optimizing production throughput by leveraging dual-lane dispensing

May Day Party

Tue, 5 May 2001
Cathy was driving her daughter, Kathy, to the Advanced Packaging May Day party. Cathy planned to be there 15 minutes early (to straighten the ribbons in Kathy's hair) by driving 60 mph on the highway and 30 mph on the 20-mile stretch of side road.

LSI Logic ready for lead-free

Tue, 5 May 2001
In a response to industry demand for lead-free products and, more specifically, to customer projections to implement lead-free processes, LSI Logic Corp. has introduced a set of lead-free ball grid arrays (BGAs) for use in communication and storage products

Unpack your suitcase

Tue, 5 May 2001
Finally, the summer months are upon us. Oftentimes, this can translate into less business travel, as trade shows wind down (revving up for the big SEMICON West show, I suppose) and there are fewer conferences

Movers and shakers

Thu, 2 Feb 2001
Exatron Inc., San Jose, Calif., has announced the appointments of Bo Mendoza to customer relations manager, Bob Garcia to particle interconnect product manager, and Denise Smith as particle interconnect coordinator

Technology licensing

Thu, 2 Feb 2001
Technology licensing is prolific in many industries, including the pharmaceutical and biotechnology arenas, and is used heavily for consumer products

The glitch we can't stop talking about

Sun, 4 Apr 2001
Mention the word "dot-com" lately and undoubtedly your co-workers will give you a mixed bag of comments, from the "I told you so" naysayers to the "You haven't seen nothin' yet" optimists

Technology comparisons and the economics of flip chip packaging

Thu, 3 Mar 2001
The decision to use flip chip packaging is not a simple one. Many equipment, product, and process variables affect the relative merits of flip chip vs. wire bonded packages

The back-end process: Step 3 - Die attach step by step

Thu, 3 Mar 2001
In the past, most integrated circuit (IC) packages used wirebonding as the interconnect technology between chip and leadframe

Divide and Conquer?

Tue, 10 Oct 2002
The packaging world has seen profound changes over the decades and we may be faced with another one shortly.

The back-end process: Step 9
QFN Singulation

Sun, 9 Sep 2002
Two processes compared

Shining Stars of the Industry

Sun, 9 Sep 2002
Second Annual Advanced Packaging Awards

News

Thu, 11 Nov 2001
Kyocera America Inc. has introduced the industry's first flip chip build-up substrate that is capable of withstanding 260?C solder reflow, which is necessary for lead-free processing

The springtime swirl

Sat, 4 Apr 2000
As springtime activities spin around us, everyone at Advanced Packaging magazine is squeezing in time to dash off to the dry cleaners, pack suitcases and make last-minute limo reservations for the litany of upcoming shows we plan to attend. By the time this issue goes to press, we will have just completed trips to NEPCON West, APEX 2000 and IMAPS` International Symposium on Advanced Packaging Materials. We certainly understand the importance of getting away from our desks and talking with reader

ECTC meets in Las Vegas

Sat, 4 Apr 2000
The Electronic Components and Technology Conference (ECTC) will celebrate its 50th anniversary May 21-24 at Caesar`s Palace in Las Vegas. The conference is expected to attract more than 800 designers, engineers and technical managers from the packaging, components and materials segments of the electronics industry. The meeting features more than 300 technical papers, short courses, a review of educational programs and initiatives in packaging, and a technology corner featuring exhibits by leadin

Combo Memory agreement

Sat, 4 Apr 2000
APack Technologies Inc., the first wafer bumping and flip chip foundry service provider in Taiwan, signed a memorandum of understanding (MOU) with Itochu Corp., Linvex Finet Japan and Siix Corp. for joint development and promotion of Combo Memory to the worldwide market. The Combo Memory module stacks SRAM and flash memory components to fulfill the small form-factor requirement of wireless communication handsets. According to the MOU, APack will provide its packaging design and manufacturing kno

Design for reliability

Tue, 10 Oct 2002
Package and Board-level Reliability Analysis with CAE

Preparing for Next-generation Electronics

Tue, 10 Oct 2002
Since the early 1990s people have been excited about a new generation of consumer electronics — a true "anything, anytime, anywhere" generation that would enable instant communications through a wide range of devices.

U.K. Companies Find Packaging Niches

Tue, 10 Oct 2002
LONDON — The United Kingdom is not known as a critical location for semiconductor packaging, but there are numerous companies doing some very interesting work there.

Wafer-level Packaging Evolves and Grows

Tue, 10 Oct 2002
MEPTEC's latest one-day symposium, "International Wafer- level Packaging Conference: The Convergence of Fab and Assembly," focused on one of the hottest topics in the industry.

ONNN update: Thai floods close Rojana SATS ops indefinitely

Mon, 10 Oct 2011

ON Semi believes that its SANYO Semiconductor division's Thai operations in the Rojana Industrial Park have been severely damaged by Thailand's flood. Another facility in Bang Pa In, previously unaffected, is now flooded. ONNN says none of its employees in Thailand have been endangered by flood waters on-site.


Spansion consolidates test and assembly ops

Mon, 10 Oct 2011

Spansion Inc. (NYSE:CODE) will consolidate its 2 semiconductor assembly and test services (SATS) operations, closing its facility in Kuala Lumpur, Malaysia, to reduce costs by about $30 million annually.


Multitest vertical contact test probe technology eschews barrels

Fri, 10 Oct 2011

Multitest debuted the Quad Tech concept, next-generation vertical contact technology with a barrel-less architecture.


Global Unichip focuses on ASIC biz

Fri, 10 Oct 2011

Global Unichip Corp. (GUC; TW:3443) refined its business and technology model to become a full-service, flexible ASIC company. President Jim Lai refers to the model as GUC's branded Flexible ASIC Model, covering SoC integration, implementation methodologies, and integrated manufacturing.


OmniVision faces lawsuit over lost Apple image sensor contract

Thu, 10 Oct 2011

Levi & Korsinsky is bringing a class action lawsuit against OmniVision Technologies Inc. (NASDAQ:OVTI) on behalf of stockholders that allege that OmniVision failed to disclose properly the loss of an exclusive contract with Apple for image sensors, in-house production delays, as well as other counts.


Lasers package ultrathin semiconductors at low cost, high volume

Wed, 10 Oct 2011

North Dakota State University, Fargo, researchers have developed a packaging technology using Thermo-Mechanical Selective Laser Assisted Die Transfer (tmSLADT) to reduce the size and cost of microelectronics packages.


Nantong Fujitsu Microelectronics installs NEXX tool for copper pillar, RDL packaging

Wed, 10 Oct 2011

NEXX Systems shipped a Stratus electrochemical deposition tool to Nantong Fujitsu Microelectronics Co. Ltd. (NFME), based in Jiangsu province, China. NFME will use the Stratus for copper pillar and RDL advanced packaging applications.


IMAPS: Markovich takes reins, Jones given Lifetime Achievement Award

Fri, 10 Oct 2011

At the IMAPS 44th International Symposium on Microelectronics in Long Beach, CA, Voya Markovich, well-known industry PCB and packaging expert, took over the reins as the organization

IMAPS semiconductor packaging award bestowed on Nordson Asymtek's Adamson

Fri, 10 Oct 2011

Steven J. Adamson, marketing specialist with Nordson ASYMTEK, received the Daniel C. Hughes, Jr., Memorial Award, for the greatest contribution to IMAPS and the microelectronics packaging industry.


CSCD probe head accurately tests high-frequency devices on small pads

Tue, 10 Oct 2011

Cascade Microtech Inc. debuted InfinityQuad, a multi-contact probe head capable of automatically probing aluminum (Al), copper (cu), or gold (Au) pads as small as 30 x 50

ADI unveils digital isolator package to meet 8mm creepage reqs

Wed, 10 Oct 2011

Analog Devices Inc. (ADI) introduced a packaging technology for digital isolators that achieves a minimum of 8mm creepage distance required by global industry standards to ensure safe operation in high-voltage medical and industrial applications.


IMAPS 2011 preview

Mon, 10 Oct 2011

IMAPS 2011, the 44th International Symposium on Microelectronics, will take place in less than one week at the Long Beach Convention Center. Ahead of the show, here are some of the highlights for attendees.


Toshiba selling Amkor its Malaysian SATS ops

Fri, 9 Sep 2011

Amkor will acquire Toshiba Electronics Malaysia Sdn. Bhd., Toshiba

CSCD completes test socket biz sale, authorizes stock repurchase

Tue, 9 Sep 2011

Cascade Microtech (NASDAQ:CSCD) completed the sale of its test socket manufacturing business for $550,000 to R&D Interconnect Solutions. Cascade's board of directors also authorized a stock repurchase program under which up to $2,000,000 of its common stock may be repurchased.


STATS ChipPAC Expands QFN Portfolio

Tue, 11 Nov 2008
(November 24, 2008) SINGAPORE — STATS ChipPAC Ltd. has expanded its quad flat no-lead (QFN) packaging portfolio with a strip-etch version for applications requiring increased design flexibility and higher input/output (I/O) performance in a small, thin package profile. The new QFN package family, referred to as QFNs-se, reportedly features a higher number of very thin I/O terminal pads than conventional single or dual-row QFN or leadframe-based quad flat packages (QFPs).

MEPTEC Symposium: Density and Cost is Driving Innovation

Tue, 11 Nov 2008
by Julia Goldstein, Ph.D. contributing editor
Speakers at MEPTEC's Packaging Developments and Innovations Symposium, November 13, 2008 in San Jose, CA, presented various new technologies to enable package miniaturization while keeping costs in check. Much of the focus was on materials innovations that optimize the existing infrastructure. One departure from that was discussions surrounding through silicon via (TSV) advancements.

Advisory Board

Mon, 11 Nov 2008

By R. Wayne Johnson, Ph.D., Auburn University

While $4/gal.gasoline prices have dropped, it is inevitable they will rise again. So what does this have to do with advanced packaging? A lot! While we hear discussions of alternate energy, we will continue to use oil for the foreseeable future. Electronics (and advanced packaging) are important for measurements during well drilling and for production management over the life of the well.


Multi Flip Chip Assembly for the Mass Market

Mon, 7 Jul 2008
By Christian Pichler, Datacon Technology GmbH
Originally targeted to high-end applications, flip chip assembly technology is rapidly finding its way into low-end applications for high-volume products with multiple chips, due to cheaper substrates and cost-effective bumping. This requires high speed and precision, which can be achieved cost-effectively by processing directly from the wafer using tried-and-tested, high-throughput flip-chip bonder platforms.

Electronics Industry Association News

Mon, 7 Jul 2008
(July 14, 2008) — IMEC and Qualcomm collaborate on 3D packaging technologies; IPC meets internationally to discuss urgent trends; iNEMI releases recommendations for lead-free alloy alternatives.

Advanced Packaging Roadshow: Northwest Passage

Tue, 7 Jul 2008
Near Nature; Near Perfect
By Gail Flower, editor-in-chief
Early this spring the Advanced Packaging Roadshow flew out to Wilsonville, Oregon, to visit Mentor Graphics Corporation's U.S. headquarters, which is situated in a beautiful, park-like setting. The beauty of nature — with nutria feeding on the grounds, ducklings gathering in the lake, tulips in bloom, and greening outdoor soccer fields — provided a great spot for quiet thinking.

Countdown to SEMICON West: Exhibitor Preview

Mon, 7 Jul 2008
(July 7, 2008) SAN FRANCISCO, CA — With SEMICON West 2008 just one week away, July 15-17,at the Moscone Center, San Francisco CA, exhibitors are getting the word out to make sure attendees don't miss a thing. While SEMI has a full-line up of conferences, keynotes, and workshops planned, many exhibitors will be leveraging the venue to announce new processes, technologies, products, and more.

Unisem Licenses FlipChip International's WLP Technologies

Mon, 6 Jun 2008
(June 16, 2008) KUALA LAMPUR, Malaysia — Unisem Berhad and its subsidiary, Unisem-Advantpack Technologies (UAT) have entered into an agreement with FlipChip International (FCI) to license FCI's wafer bumping and wafer-level packaging (WLP) technologies. The agreement will reportedly include FCI's core technologies. In return, FCI will become a shareholder in UAT.

Asymtek Celebrates 25 Years in Business

Mon, 6 Jun 2008
June 16, 2008 — Asymtek, a Nordson company, provider of dispense, coating, and jetting technologies, recently celebrated the company's 25th anniversary. Asymtek's systems are known for innovative technology in dispensing, closed-loop process controls, and patented processes in jetting and coating. SMT Magazine talked to founder, Alec Babiarz about the company's history.

SMT/Hybrid/Packaging 2008: Exhibitor Offerings Span Electronics Supply Chain

Fri, 6 Jun 2008
Nuremberg, Germany — Bigger and more international than ever, exhibitors at SMT/Hybrid Packaging, June 2-4, Nuremberg, Germany, focused their product showcases around the theme of automotive electronics, or used the venue for the European launch of new products.

Probe Card for Flip Chip / Bumped Logic Devices

Tue, 6 Jun 2008
Megamax, the latest addition to Wentworth Laboratories, Inc.'s vertical probe card line addresses major probe card challenges encountered when probing high power flip chip devices such as microprocessor units (MPU's), graphics processing units (GPU's) and System on Chip (SoC's).

STATS ChipPAC and Infineon Sign Second Agreement on eWLB Technology

Sun, 8 Aug 2008
(August 31, 2008) SINGAPORE— STATS ChipPAC Ltd. and Infineon Technologies have signed a second agreement in which STATS ChipPAC will provide manufacturing services for products based on Infineon's first generation embedded wafer-level ball grid array (eWLB) technology. This agreement between the two companies comes closely follows the Aug. 7 release announcing an agreement between Infineon, STMicroelectronics and STATS ChipPAC on joint development of next generation eWLB technology.

Amkor Introduces Novel Flip Chip Technology

Wed, 7 Jul 2008
(July 2, 2008) CHANDLER, AZ — Amkor Technology, Inc. announced the introduction of a high-performance flip chip packaging technology using an advanced molding process technology that is expected to provide a number of design, cost and performance advantages for field programmable gate arrays (FPGAs), CPUs, graphics processors, and ASICs. The company plans to feature this technology during SEMICON West 2008, July 15 - 17, in San Jose, CA.

QFN Test Socket

Wed, 7 Jul 2008
The Z-Socket, or impedance socket, from Antares, is an RF QFN test socket developed to combine the reliability of traditional spring-probe technology with the impedance-matching functionality of shorter interconnects at higher price points.

A RoHS By Any Other Name...

Mon, 6 Jun 2008
(June 30, 2008) Gail Flower, editor_in_chief of Advanced Packaging, offers her perspective in a lead-free debate initiated by Rick Short of Indium, in response to a segment of The Riley Report, "The $38 Billion Blunder" penned by AP's columnist, George A. Riley, Ph.D.

Wafer-level CSP Interposers

Mon, 11 Nov 2008
Synergetix test socket interposers for wafer-level chip scale package (WLCSP) testing are used for vertical probing applications. The interposers have a plastic assembly containing IDI's semiconductor probe technology built in. Combined with an easy-to-design-and-fabricate load board, interposers require minimal attention throughout their life cycle.

SEMICON Europe: Connecting Companies for 3D Interconnects

Fri, 10 Oct 2008
By Paul Collander, Poltronics, Inc. At the recent Advanced Packaging Conference at SEMICON Europe in Stuttgart, Germany, (October 7-9, 2008) Fran

IMAPS International Symposium 2008 Preview

Thu, 10 Oct 2008
By Fran

SUSS MicroTec and STS Take the Show on the Road

Wed, 10 Oct 2008
(October 29, 2008) NEWPORT, UK and GARCHING, Germany— SUSS MicroTec and Surface Technology Systems (STS) are once again hosting a technology roadshow in five major Asian locations from October 29 to November 7. Similar to the US roadshow last spring, the series of one-day events is intended to provide a comprehensive overview of the latest developments 3D Integration and advanced packaging.

MEPTEC/Advanced Packaging Announce Symposium Final Program

Wed, 10 Oct 2008
(October 22, 2008) SAN JOSE, CA — MEPTEC, the MicroElectronics Packaging and Test Engineering Council, and Advanced Packaging magazine have finalized the program for their upcoming symposium titled "Packaging Developments and Innovations: From System Design to Integrated Delivery" to be held on Thursday, November 13, 2008 at the Wyndham Hotel, San Jose, CA.

MEPTEC and Advanced Packaging Magazine to Hold Packaging Symposium

Tue, 8 Aug 2008
(AUGUST 12, 2008) SAN JOSE, CA — In recognition of MEPTEC's 30th year, MEPTEC and Advanced Packaging magazine will present Packaging Developments and Innovations: From System Design to Integrated Delivery, Thursday, November 13, 2008, at the Wyndham Hotel in San Jose, CA. The symposium will include a special luncheon featuring keynote speaker, Glenn Daves, director of packaging technology, Freescale Semiconductor.

STMicroelectronics, STATSChip PAC, and Infineon Join Forces in Next-gen WLP Development

Thu, 8 Aug 2008
(August 7, 2008), GENEVA, SINGAPORE, and NEUBIBERG, Germany — STMicroelectronics, STATS ChipPAC, and Infineon Technologies AG have signed an agreement to jointly develop the next-generation of embedded wafer-level ball grid array (eWLB) technology, based on Infineon's first-generation technology, for use in manufacturing future-generation semiconductor packages.

SEMICON Europa's Advanced Packaging Conference Shifts Focus from TSV to WLP

Tue, 8 Aug 2008
August 5, 2008 — Shifting away from focus on 3D IC and TSV processes, this year's Advanced Packaging Conference at SEMICON Europa, titled "Technologies, Manufacturing and Supply Chain", will focus on more immediate issues facing the back-end sector of the semiconductor industry. Eef Bagerman, general manager operations, back-end innovation, NXP Semiconductors offered some insight about how the program was selected, and what technologies will be most likely to spark discussion.

Conductive Adhesives for Flexible Circuits

Mon, 8 Aug 2008
A line of fast-setting, one-component conductive adhesives designed for connecting passive components and bare die on lead frames and PCB substrates has been introduced by the Contact Materials Division (CMD) of Heraeus. Intended uses for these materials include smart cards and flexible circuits found in camera phones and automotive or semiconductor applications.

RF Components and Devices in 3D LCP Package

Mon, 8 Aug 2008
Part 1: Embedded Actives
By Swapan K. Bhattacharya, Chad Patterson, and John Papapolymerou, Georgia Tech
As real estate in electronic packages has been compromised in the Z direction, thin has become the buzz word — encompassing die, dielectric, passives, and ultimately resulting in thin packages. This series of articles will overview trends from thick to thin packages with embedded RF passive and active components.

X-Ray Inspection Identifies Flip Chip Detects

Tue, 9 Sep 2008
Using 2D and 3D X-ray techniques to find and confirm manufacturing defects in flip-chip devices
By Evstatin Krastev, Ph.D. Dage Precision Industries, a Nordson Company
While flip chip design eliminates excessive packaging, high-density flip chip devices place a greater burden upon device inspection. The combination of 2D x-ray and CT analysis offers powerful analytical capabilities need for the complete inspection of flip-chip devices and stacked packages.

Henkel Names New Electronics Executive Team

Fri, 7 Jul 2008
(July 25, 2008) IRVINE, CA — Following its acquisition of the Adhesives and Electronics Materials businesses from National Starch and Chemical Company, Henkel has announced its executive team to take the company forward. Under the direction of Alan Syzdek, corporate senior V.P. the electronics group of Henkel will be organized on a global basis by industry sector.

Advanced Packaging and Solid State Technology Applaud 2008 ACA Winners

Tue, 7 Jul 2008
(July 22, 2008) NASHUA, NH — On Wednesday, July 16, 2008, the editors and publisher of Solid State Technology (SST) and Advanced Packaging Magazine presented the 2008 ACA Awards, in usual impromptu style on the floor at SEMICON West. This was the sixth straight year attendees of SEMICON West were invited to vote on products they saw at the annual trade show.

Hermes European Embedded Dies Consortia Partners with Flip Chip International

Mon, 7 Jul 2008
(July 8, 2008) PHOENIX, AZ — Hermes, the Eurpoean consortia for the development and industrialization of embedded die technology, has partnered with Flip Chip International (FCI) to leverage the company's proprietary embeddable die customization (EDC) technology to enable the consortium's pursuit of heterogeneous systems integration.

Evaluating a TIM for Flip Chip Packages

Mon, 10 Oct 2008
By V. Gektin, M. Stern, Sun Microsystems; L. Larson, D. Bhagwagar, J. Marin, Dow Corning Corp. K.Nakayoshi , Dow Corning Toray Co., Ltd.
As power levels and heat generation increase in high-performance CPUs and other semiconductor devices, the thermal performance of commonly used packaging components is becoming a limiting factor. A silver-filled silicone material specifically for TIM 1 applications (the die/lid interface) was designed to meet this challenge.

Executive Panel Addresses Options in WLP

Tue, 10 Oct 2008
By Fran

DNP Develops Slim Leadframe

Thu, 1 Jan 2009
(January 29, 2009) TOKYO — Dai Nippon Printing Co. Ltd. (DNP) developed a package leadframe to slim down the semiconductor package mounted on electronic devices. The leadframe enables known good die (KGD) semiconductor packaging with a thickness of 0.15 mm, using precision plating processes.

3D Packaging Technologies Steal the Show at IMAPS

Tue, 4 Apr 2008
By Fran

Transistor Outline Packages

Tue, 9 Sep 2008
SCHOTT Electronic Packaging offers a hermetic transistor outline (TO) for fiber channel applications of 17 gigabits/second and beyond. The TO PLUS Line reportedly overcomes the normal limitations of a TO by combining glass and packaging design aspects. Up to 6 pins, including higher frequency and DC (electrical) ports, most of the necessary electronics can be packaged into a regular TO footprint, rather than resorting bulky complex hybrid packages.

SMT Magazine Presents Packaging Panel at IPC Midwest

Wed, 9 Sep 2008
(September 24, 2008) SHAUMBURG, ILSMT editor-in-chief Gail Flower chaired a panel comprising equipment supplier, laboratory, EMS provider, and consultant voices at IPC Midwest in Schaumburg, Ill. David Geiger, Flextronics International; Jacques Coderre, Unovis Solutions; Vern Solberg, STI - Madison; and Gene Dunn, Panasonic Factory Solutions of America spoke about emerging packaging technologies.

Pac Tech Announces Grand Opening and Technical Symposium

Mon, 9 Sep 2008
(August 31, 2008)SANTA CLARA, CA— In celebration of its new 55,000 sq.ft. wafer bumping and back-end processing facility in Penang, Malasia, Pac Tech Packaging Technologies is planning a grand opening ceremony and technical symposium on September 18 and 19, 2008, respectively. The festivities are intended to bring attendees up to date on all facility's capabilities, and inform them on new developments in packaging technology.

TSV First and Last: Through-Si Via Technologies for 3D SIC and 3D WLP

Wed, 1 Jan 2009
Part 2
By Jan Provoost and Eric Beyne, IMEC
3D SIC uses a via first approach to connect circuits at the global IC level. 3D WLP uses a via last approach to connect circuits at the bond pad level. Both these approaches occupy a separate space on the 3D roadmap. This article, presented in two parts, offers both options and describes the process to realize them.

International Wafer-Level Packaging Conference (IWLPC) Finalized

Wed, 7 Jul 2009
(July 22, 2009) MINNEAPOLIS — The 6th Annual International Wafer-Level Packaging Conference (IWLPC), October 27-30, 2009, Santa Clara, CA includes tutorials, expert panel discussions, Dr. Rao Tummala keynoting, and 18 tech sessions.

SEMICON West: Jan Vardaman and Paul Siblerud Analysis

Fri, 7 Jul 2009
Paul Siblerud, SEMITOOL, discusses the role of the EMC-3D consortium in developing new packaging technologies, such as through silicon vias (TSV). Jan Vardaman, TechSearch International, examines the barriers, and breakthroughs, around 3D integration.

Interplex Acquires Quantum Leap Packaging

Mon, 7 Jul 2009
(July 20, 2009) COLLEGE POINT, NY — Component and assembly maker Interplex Industries acquired Quantum Leap Packaging Inc. (QLP), an electronics packaging and polymer science company. Included in the transaction are all of QLP's proprietary technologies including resin technologies such as Quantech for hermetic semiconductor packaging.

Nanolab Technologies Adds X-Ray Capabilities

Wed, 7 Jul 2009
July 1, 2009 -- Xradia, Inc., a developer and manufacturer of high-resolution 3D X-ray imaging systems, announced a partnership with NanoLab Technologies. The companies will offer 3D X-ray imaging as part of a service model that enables customers in the electronics and semiconductor industry to address semiconductor packaging development and failure analysis challenges while evaluating the purchase of their own systems.

GLOBALFOUNDRIES, Amkor co-develop semiconductor assembly and test methods

Mon, 8 Aug 2011

GLOBALFOUNDRIES entered into a strategic partnership with Amkor (NASDAQ:AMKR) to develop integrated semiconductor assembly and test processes for advanced silicon nodes. The aim is integrated fab-bump-probe-assembly-test steps that can be commercialized across multiple customers and end-market applications.


Cabot divests Supermetals biz to GAM

Fri, 8 Aug 2011

Cabot Corp. (NYSE:CBT) will sell its Supermetals business to Global Advanced Metals (GAM), a supplier of tantalum ore to the Supermetals business.


Package-on-package (PoP) track at SMTAI

Wed, 8 Aug 2011

The SMTA will host conference events with Amkor, Research in Motion, and TechLead Corporation on package-on-package (PoP) 3D stacking at SMTA International (SMTAI), October 16-20 in Fort Worth, TX.


Assembleon launches packaging toolset with low impact force

Tue, 8 Aug 2011

Assembl

STATS ChipPAC names top suppliers of 2010

Tue, 8 Aug 2011

SATS provider STATS ChipPAC Ltd. (SGX-ST:STATSChP) honored its top materials and equipment suppliers in 2010, recognizing "intense focus and commitment to performance, quality, cycle time, and cost."


NATI adds PPMU and SMU test modules to PXI platform

Mon, 8 Aug 2011

National Instruments (Nasdaq: NATI) added per-pin parametric measurement unit modules and source measure unit modules to its PXI platform for semiconductor characterization and production test.


STATS ChipPAC adds former STM exec to Board

Mon, 8 Aug 2011

Semiconductor packaging and test provider STATS ChipPAC Ltd. (SGX-ST: STATSChP) welcomed Pasquale Pistorio as an advisor to its Board of Directors.


Compugraphics expanding photomask sizes for WLP

Fri, 8 Aug 2011

Compugraphics International is widening its line of photomasks to include larger-area products up to 16 in2, responding to customer demand for wafer-level packaging and other semiconductor and optical applications.


Inside the Known Good Die conference

Wed, 8 Aug 2011

The annual Known Good Die (KGD) conference, taking place Nov. 10 in Santa Clara, CA, will address semiconductor die testing, assembly, manufacturing, and business challenges, with the tagline "KGD in an Era of Multi-Die Packaging and 3D Integration."


Nemotek wafer-level camera integrates CMOS image sensors

Wed, 8 Aug 2011

Nemotek Technologie uncrated the Exiguus, with a VGA wafer-level camera integrating wafer-level optics assembled with CMOS image sensors (CIS).


Johnstech renames Kelvin-ready test contactor

Mon, 8 Aug 2011

Johnstech International Corporation is rereleasing the configurable ROL 200K (Kelvin) Test Contactor as the ROL 200KR Kelvin-Ready Test Contactor for both pad and leaded style devices.


Tessera adds DARPA former director to board

Mon, 8 Aug 2011

Tessera Technologies appointed Anthony J. Tether, Ph.D., to its board of directors. Tether is CEO of The Sequoia Group, and has held executive positions at DARPA and Ford Aerospace Corp., among others.


SEMI convenes system-in-package summit alongside SEMICON Taiwan

Fri, 8 Aug 2011

SEMI will hold the first-ever SiP Global Summit, September 7-9, co-located with SEMICON Taiwan. Three forums cover system in package (SiP) test, the "3D IC era," and the requirements of mobile electronics.


Plasma treatment research lab launched in China

Thu, 8 Aug 2011

Nordson MARCH and Science College of Donghua University, Shanghai, China launched a joint laboratory for plasma research and education. The college and supplier will share equipment, research projects, personnel resources, and additional resources as needed.


Lack of EDA tools, thermal issues impeding 3D packaging technology

Wed, 8 Aug 2011

Amkor's Ron Huemoeller shares his thoughts about two panels from SEMICON West, on 2.5D silicon interposer packaging technologies and its supply chain, and 3D packaging technology and its ecosystem.


Microbonds wins University of Waterloo support

Wed, 8 Aug 2011

The University of Waterloo, Ontario, through the Applied Research and Commercialization Initiative, is supporting several companies researching and developing new products. One company receiving aid from the school is Microbonds, maker of semiconductor bonding wire.


Multitest intros 16-site package test handler

Wed, 8 Aug 2011

Multitest launched a 16-site tri-temp pick-and-place handler, the MT9510 x16. The platform can be kitted to test a range of semiconductor packages.


Amkor expands package design kit for Agilent ADS

Tue, 8 Aug 2011

Amkor has extended its Quad Flat No-Lead (QFN) package design kit to be the first such kit available for Agilent Technologies' Advanced Design System (ADS) electronic design automation software.


Analyst: Gold price surge helping Cu wire shipments

Mon, 8 Aug 2011

Industry efforts to transition from gold to copper wire are accelerating as prices for gold continue to spike to near record levels, notes TechSearch International in a new report.


Nomura divests semiconductor packaging substrate maker shares

Sun, 8 Aug 2011

Nomura Principal Finance Co. Ltd., a wholly owned subsidiary of Nomura Holdings Inc., transferred all the shares it owns in Eastern Co. Ltd. to Eastern.


iPad teardown reveals Apple's hardware supremacy

Thu, 8 Aug 2011

Apple Inc.'s iPad has thus far thwarted competitive tablets in design efficiency, according to an IHS iSuppli Teardown Analysis of eight tablet models from IHS. Major savings come from Apple's control of chips like SDRAM and applications processors.

 


DEK licenses stencil system to Great Lakes Engineering

Wed, 8 Aug 2011

Great Lakes Engineering will supply DEK's VectorGuard packaging and surface mount assembly stencil system to customers in 32 states and 3 countries.


Agilent, UC Davis found millimeter wave research center

Wed, 8 Aug 2011

Agilent and UC Davis established the Davis Millimeter Wave Research Center to develop advanced mm wave and THz systems for radar, sensors, imaging systems, communications and integrated passive devices (IPDs) found in electromagnetic metamaterials and antennae.


Data I/O's next-gen pre-placement programmer prevents operator errors

Tue, 8 Aug 2011

Data I/O Corporation (NASDAQ: DAIO) debuted the RoadRunner3 in-line programming system, a just-prior-to-placement programming tool with modules to automate processes and eliminate operator interventions.


Unisem adds LTX-Credence tester to US test dev center

Mon, 8 Aug 2011

SATS provider Unisem purchased a LTX-Credence PAx RF Test System for its Sunnyvale, CA, test development center, joining other recent test/wafer equipment purchases at the site.


TI achieves volume production with stacked clip-bonded QFN

Thu, 7 Jul 2011

Texas Instruments has shipped more than 30 million units of its PowerStack packaging technology, a combination of chip stacking and clip bonding that is designed to improve performance and chip densities in power management devices.


TSV zen comes down to wafer processing balance

Tue, 7 Jul 2011

3D semiconductor packaging processes involve various groups, and standards are important in the hand-offs between them, explains Mark Berry, sales director at Metryx. He covers how to use metrology to protect wafer yields in 3D packaging.


NSMAT licenses Pd-coated Cu bonding wire to competitor

Fri, 7 Jul 2011

Nippon Micrometal Corporation (NMC) licensed their single-layer-palladium (Pd) coated copper (Cu) bonding wire for LSI packaging to Tanaka Denshi Kogyo K.K., bonding wire manufacturer and traditionally a competitor.


Optomec aerosol jet printing featured as wire bond, TSV alternative at IMAPS Device Packaging

Tue, 3 Mar 2011

Optomec Aerosol Jet product manager Mike O’Reilly will give a presentation titled "Aerosol Jet Printing as an Alternative to Wire Bond and TSV Technology for 3D Interconnect Applications" at the IMAPS Device Packaging Conference on March 9.


Hermetic wafer level packaging lowers cost with IMT Au Au bond

Tue, 3 Mar 2011

IMT introduced its hermetic gold-to-gold (Au-Au) thermo compression bonding for wafer-level packaging (WLP). In development for nearly a year, this bond is being actively used in production.


Gold tin process from Stellar Industries improves wettability in die bonding

Mon, 2 Feb 2011

The new gold/tin (AuSn) process from Stellar Industries is ideally matched to Stellar’s proprietary CPU copper on aluminum nitride (AlN) submounts with its sharp guillotine edge for precise edge alignments.The new gold/tin (AuSn) process from Stellar Industries is ideally matched to Stellar’s proprietary CPU copper on AlN submounts with its sharp guillotine edge for precise edge alignments.


Multitest wins InCarrier test handling system order

Thu, 2 Feb 2011

Multitest test handling systemMultitest received its fifth full purchase order for its InCarrier device transfer system with InStrip test handling system adapted to metal frame-based carriers.


Nanometrics WLP bonding metrology tool launches with logic order

Thu, 2 Feb 2011

The Unifire 7900IR provides 3D inspection of wafer-scale packaging features as well as registration for wafer-to-wafer bonding applications for use in advanced wafer scale packaging process control.


The road ahead for SiPs

Tue, 2 Feb 2011
With the proper up-front evaluation of SiP designs, a tool box of enabling technologies, and strong team interactions between all involved parties, SiP solutions can enable novel electronic products with faster time to market than would be possible with traditional scaling. Darvin Edwards, Masood Murtuza, Texas Instruments, Dallas, TX USA

Tessera terminates Amkor license

Mon, 2 Feb 2011

Tessera Technologies Inc. (NASDAQ:TSRA) announced that on February 17, 2011, it sent Amkor Technology, Inc. an official notice of termination of their license agreement with Tessera. The two companies are currently in arbitration regarding multiple issues.


Advanced transmission lines replacement for TSVs

Fri, 2 Feb 2011

Jamal Izadian, co-founder & president of RFCONNEXT, makes the case for shaped membrane transmission lines (SMTL) for use in high-speed 3D packaging applications. SMTL supports and improves flip-chip, micro-bumping, wafer thinning, system-in-package (SiP), package-on-package (PoP), and other packaging processes by extending the bandwidth and high-speed limits of these technologies.


inTEST brings ATE subsidiaries under inTEST Thermal Solutions

Thu, 2 Feb 2011

inTEST Corporation (NASDAQ: INTT) subsidiaries, Temptronic and Sigma Systems, both in Sharon, MA, will begin operating under the umbrella trade name, inTEST Thermal Solutions Corp.


STATS ChipPAC launches flip chip packaging for advanced silicon nodes

Wed, 2 Feb 2011

STATS ChipPAC launched fcCuBE technology, an advanced flip chip packaging technology that features copper (Cu) column bumps, bond-on-lead (BOL) interconnection and enhanced assembly processes. STATS ChipPAC claims the flip chip package is cost-comprable to standard packaging processes, and compatible with shrinking semiconductor device nodes down to 28nm.


Intel Capital leads InVisage Series C venture funding

Tue, 2 Feb 2011

InVisage pixel capture as compared to traditional image sensors.InVisage Technologies, image sensor technology start-up, received its series C round of venture funding, led by Intel Capital. The undisclosed amount will be used to bring the company's quantum-dot-based QuantumFilm technology and products into mass production.


Semiconductor industry veteran takes helm at Minco Technology Labs

Fri, 1 Jan 2012

Minco Technology Labs, hi-rel semiconductor die processing, packaging and test provider, appointed board member Bill Bradford as president and CEO.


Samsung Electronics ramps embedded multi-chip packaging with memory products

Thu, 1 Jan 2012

Samsung Electronics began producing embedded multi-chip package (eMCP) memory for use in entry- to mid-level smartphones. The products use low power double-data-rate 2 (LPDDR2) 30nm DRAM and 20nm NAND flash memory.


Semiconductor packaging houses gain from more device complexity

Wed, 1 Jan 2012

Increased I/O density, power/performance reqs, and other factors are increasing use of flip chip, 2.5D and 3D technologies, a boon to packaging subcontractors. But they face a challenge from foundries, and must navigate under-utilization of wire bonding capacity.


Upcoming SMTA events: IWLPC keynote named, SMTAI seeks presenters

Tue, 1 Jan 2012

The SMTA released its call for presenters for SMTA International (SMTAI) 2012, October 14-18 in Orlando, FL. The association, along with Chip Scale Review magazine, also announced the keynote for the International Wafer-level Packaging Conference (IWLPC), held November 5-8, San Jose, CA.


Inari proposes acquisition of Amertron

Tue, 1 Jan 2012

Packaging house Inari Berhad signed an MOU to acquire Amertron Global, which operates in the Philippines and China providing microelectronics and optoelectronics manufacturing services.


STATS ChipPAC expands WLP capacity with new Singapore facility

Thu, 1 Jan 2012

STATS ChipPAC held the groundbreaking ceremony for a new factory in Singapore, which will enable STATS ChipPAC to expand its manufacturing capabilities for advanced wafer level technologies.


TSRA faces stockholder challenge to Board of Directors

Wed, 1 Jan 2012

Tessera Technologies (TSRA) received a letter from Starboard Value and Opportunity Master Fund Ltd, intending to nominate 3 candidates for the TSRA Board of Directors. Tessera issued a response, saying that it has the right Board and management team in place.


@ The ConFab: Supply chain or supply web for 3D packaging?

Wed, 6 Jun 2012

With many advanced packaging processes taking place on the semiconductor wafer, the traditional supply chain of front-end fab at the foundry and back-end fab at the packaging and test house is falling apart. The ConFab session,

3D and 2.5D semiconductor packaging technologies @ The ConFab

Wed, 6 Jun 2012

As packaging has played a larger and larger role in chip performance, form factor, and capabilities, The ConFab has increased its focus on back-end processes. Cue

LED package sales to increase but revenues will stay flat until 2014

Mon, 6 Jun 2012

Displaybank published a 2009-2014 analysis of LED packages, the finished LED components used in various applications. While LED package units will grow steadily through the forecast period, revenues will remain mostly flat from 2010 to 2013.


AT&S cuts embedded package design time by 40% with Mentor Graphics

Thu, 5 May 2012

Mentor Graphics collaborated with Austria Technologie & Systemtechnik (AT&S) to implement AT&S Embedded Component Package (ECP) process in Mentor Graphics

IC package revenues outgrow unit shipments through 2016

Tue, 5 May 2012

Increased demand for product functionality is driving up IC packaging revenue faster -- a 9.8% compound annual growth rate (CAGR) -- than IC unit growth -- 7.3% CAGR 2010-2016, says New Venture Research (NVR).


ASE opens Phase 3 semiconductor packaging and test facility in Weihai

Tue, 5 May 2012

Advanced Semiconductor Engineering Incorporated (ASE) opened its Phase 3 manufacturing facility in Weihai, Shangdong province, China, boosting discrete packaging and test capacity.


Direct chip bonding, all-SiC design increase power density in Mitsubishi Electric inverter

Wed, 5 May 2012

Mitsubishi Electric Corporation developed a prototype forced-air-cooled three-phase 400V output inverter with all-silicon carbide (SiC) power modules and direct lead bonding that has a power density of 50kVA per liter.


Amkor plans semiconductor packaging and test facility in Korea

Sat, 5 May 2012

Amkor Technology Inc. (NASDAQ:AMKR) plans to build a state-of-the-art factory and global research and development center in the Incheon Free Economic Zone, which is located in the greater metropolitan area of Seoul, Korea.


Silicon Labs offers bare die from 1 wafer and up

Wed, 5 May 2012

Mixed-signal IC maker Silicon Laboratories Inc. (NASDAQ: SLAB) introduced a microcontroller (MCU) die sales program with a minimum order quantity of 1 wafer.


Amkor record 2010 financials capital investments in 2011

Thu, 2 Feb 2011

Amkor Technology Inc. (NASDAQ: AMKR), semiconductor assembly and test services provider, announced financial results for 2010, with net sales of $2.94 billion, net income of $232 million, and earnings per diluted share of $0.91. Amkor is currently planning capital additions of approximately $500 million for 2011.


FPGAs lure designers from ASICs DSPs embedded processors says Linley report

Fri, 2 Feb 2011

Altera closed the gap on Xilinx considerably in 2010, but Xilinx's competitive 28nm product should enable it to stay at the top of the FPGA market. Start-up Achronix could be the first to reach 22nm because of its Intel connection. The Linley Group's FPGA report, "A Guide to FPGAs," covers competitors within the FPGA space, as well as FPGA adoption in the chip industry.


Hitachi Chemical Henkel die attach film license

Sun, 2 Feb 2011

Hitachi Chemical has granted Henkel a worldwide license for the manufacture and sales of certain dicing die attach film.


Keithley Avoid wafer test probe set up cabling errors

Mon, 2 Feb 2011

Dave Rose, Keithley Instruments, addresses specific cabling techniques for DC, multi-frequency capacitance, and ultra-fast I-V and pulse testing, as well as the importance of proper grounding and shielding, choosing the proper interconnect for a specific measurement, and troubleshooting common interconnect problems.


Stacked silicon interconnect is better than 3D stacking Xilinx

Tue, 2 Feb 2011

ElectroIQ caught up with Suresh Ramalingam, director of advanced package design and development at Xilinx, at the January MEPTEC luncheon, where he gave a presentation on the company's stacked silicon interconnect technology. In an interview with Debra Vogler, Ramalingam discusses SSIT in relation to die stacking and TSV.


Camgian integrates Air Force radar on chip with low power active logic

Fri, 2 Feb 2011

Under a 3-year, $9.3 million contract with the Air Force Research Lab (AFRL), Camgian Microsystems will develop two ASICs with ultra-low-power characteristics: an RF transceiver ASIC will use radar-on-a-chip technology, while a DSP architecture will integrate aggressive power management.


Clarkson U tallies 1.4M support from Intel

Fri, 2 Feb 2011

During the past ten years, Clarkson University has received more than $1.4 million of direct and indirect (through Semiconductor Research Corporation) funding from Intel Corporation.


Agilent Infiniium oscilloscopes gain deeper standard memory

Wed, 2 Feb 2011

Infiniium 9000, AgilentAgilent Technologies Inc. (NYSE: A) enhanced the memory depth of its Infiniium oscilloscope lineup. All 30 models now ship with the industry's deepest standard memory and offer the deepest memory options, according to the company.


Conductive pressure sensitive tapes films introduced by Creative Materials

Tue, 2 Feb 2011

Creative Materials Inc. announced a new series of pressure-sensitive tapes that suit use in the fabrication of solar cells and modules; to replace solder and/or conductive adhesive connections; or as bus bar materials for a wide variety of printed electronics applications, including touch panels, LCDs, electro-chromatic displays, and electro-luminescent displays.


RF MEMS packaging collab DelfMEMS KFM

Tue, 2 Feb 2011

DelfMEMS and KFM Technology signed a common agreement to combine their expertise in RF micro-electro-mechanical systems (MEMS) and thin film packaging (TFP) technology. DelfMEMS will use the collaboration to provide packaged MEMS switches, fixed capacitors, and high-Q inductors on the same chip.


Silicon Si interposers aim of CEA Leti SHINKO common lab

Fri, 1 Jan 2011

CEA-Leti signed a multiyear agreement with SHINKO ELECTRIC INDUSTRIES CO. LTD. to develop advanced semiconductor packaging technology. They will focus on volume production of silicon interposers.


Tessera director Bruce McWilliams SuVolta resigns

Tue, 1 Jan 2011

Tessera Technologies (Nasdaq:TSRA) announced that Bruce McWilliams, PhD, has resigned as a member of Tessera’s board of directors effective immediately, to devote his time and attention to the needs of SuVolta's growing business.


Brush Engineered Materials changes name to Materion

Thu, 1 Jan 2011

Brush Engineered Materials Inc. (NYSE:BW) will change its name to Materion Corporation (NYSE:MTRN) and unify all of its businesses under the new name effective March 8, 2011.


Packaging, assembly changes coming in next ITRS Update

Wed, 1 Jan 2011

Dr. Phil Garrou looks ahead to a laundry list of changes coming in the next ITRS Update with respect to assembly and advanced packaging, including 3D integration, interposers, and applications from medical to automotive and embedded applications.

 


STATS ChipPAC expands wafer level packaging WLP with 300mm line

Tue, 1 Jan 2011

STATS ChipPAC Ltd. (SGX-ST:STATSChP), semiconductor test and advanced packaging service provider, expanded its wafer level package (WLP) offering with new 300mm manufacturing capabilities in Taiwan.


CEA Leti ramps 300mm 3D packaging integration line

Mon, 1 Jan 2011

CEA-Leti is expanding its technology offering, ramping up one of Europe’s first 300mm lines dedicated to 3D-integration applications. The new line is dedicated to R&D and prototyping and includes 3D-oriented lithography, deep etching, dielectric deposition, metallization, wet etching, and packaging tools.


JEDEC expands solid state drive SSD standards

Wed, 1 Jan 2011

JEDEC Solid State Technology Association, standards developer for the microelectronics industry, today announced that its JC-64.8 Subcommittee for Solid State Drives will target the development of standards for SSDs in applications beyond conventional disk drive form factors.


China WLCSP established R and D subsidiary in CA

Mon, 1 Jan 2011

China WLCSP Co. Ltd., provider of wafer level (WLP) miniaturization technologies for the electronics industry, confirmed its commitment to the US market with the opening of a new R&D center in Sunnyvale, CA.


Nautic_acquires Aavid Thermalloy for thermal management products

Tue, 1 Jan 2011

Nautic Partners has partnered with management to acquire Aavid Thermalloy LLC. Aavid designs and manufactures high-performance thermal management products used in a wide range of electronics systems and energy supplies.


CoorsTek acquires Saint Gobain Advanced Ceramics

Tue, 1 Jan 2011

CoorsTek Inc., technical ceramics manufacturer, completed its purchase of the advanced ceramics business of Saint-Gobain. CoorsTek adds manufacturing facilities and product lines such as silicon carbide for semiconductors.


TCS to acquire Trident Space & Defense to bolster expertise in secure wireless communications

Mon, 1 Jan 2011

Trident Space & Defense, which specializes in semiconductor packaging, data storage solid state drives, high-reliability electronic components, and turnkey full-tracking ground stations, will become part of the TeleCommunication Systems Inc. (TCS) government segment, as part of an acquisition announced in 2010.


Thermal nano tape for semiconductor packaging

Mon, 1 Jan 2011

SRC and researchers from Stanford University have developed a combination of elements that yields a unique nanostructure material for packaging. This advance should allow longer life for semiconductor devices while costing less than current state-of-the-art materials.


Advanced packaging collab Rudolph Technologies process tool supplier IC device manufacturer for defect inspection wafer debonding

Tue, 1 Jan 2011

The development effort involves the integration of defect inspection with a debonding tool. Manufacturing efficiencies, along with the ability to handle ultra-thin wafers, necessitates the integration of inspection in de-bonding applications. Rudolph is bringing its inspection technologies to this three-way collaboration to provide this integrated process control solution.


Aries 0.30mm pitch test sockets suit BGA CSP MLF packages

Fri, 1 Jan 2011

High-frequency center probe test sockets from AriesAries Electronics, an international manufacturer of standard, programmed and custom interconnection products, now offers machined high-frequency center probe test sockets to accommodate IC devices with a lead pitch of 0.30mm.


TSV can deal with stress says Synopsys

Mon, 3 Mar 2011

Victor Moroz discusses the strong but doable effects of stress on TSVs. TSV stress ranges are comparable to the size of the TSV, and analog behaves differently than digital. Synopsys recently presented results (part of a collaboration with imec) at a SEMATECH event.


CEA Leti IPDiA partner 3D integration for passives on Si

Mon, 3 Mar 2011

CEA-Leti and IPDiA have formed a common lab to capitalize on their complementary expertise in miniaturization and 3D integration on silicon. The common lab will develop very high-end passive components that will resist harsh environments, functional sub-mounts for LEDs, and assembly technologies.


Samsung licenses Tessera OptiML zoom tech

Thu, 3 Mar 2011

The System LSI Division of Samsung Electronics Co. Ltd. has licensed the OptiML Zoom image enhancement solution from Tessera Technologies Inc. (NASDAQ:TSRA).


Japan quake hampering package substrate supplies

Wed, 3 Mar 2011

Amid questions about the impact of the Japan earthquake on electronics and semiconductor production, there's one angle that could directly affect the semiconductor packaging sector: BT resin shortages.


KLAC packaged IC inspector ICOS CI T620

Tue, 3 Mar 2011

KLAC's ICOS CI-T620, a high-performance component inspector system for tape and reel.KLA-Tencor Corporation (Nasdaq: KLAC) introduced the ICOS CI-T620, a high-performance component inspector system for tape and reel. The CI-T620 system has dual tapers working sequentially with minimal operator intervention to increase units per hour.


Unisem adds Accretech wafer prober for 12 in wafers in Sunnyvale

Mon, 3 Mar 2011

Accretech’s next generation prober, the UF3000EX, offers high-speed wafer handling, a low-noise XY stage, and high accuracy with its OTS (Optical Target Scope) positioning technology. 


Molex joins antenna consortium

Mon, 3 Mar 2011

Molex Incorporated, interconnect supplier, has joined with other researchers to advance the goals of the Danish SAFE (Smart Antenna Front End) project. Scheduled to span four years, the $8.7 million project is being conducted by a consortium comprising Aalborg University, Intel Mobile Communications, WiSpry and Molex.


Accel RF ships reliability test systems for compound semiconductors in Asia

Fri, 3 Mar 2011

Accel-RF Corporation installed two advanced semiconductor reliability test systems for customers in Taiwan and Japan. The systems were delivered in Q4 2010 with installation completed in early January 2011.


Multitest wafer level test contactors approved by fabless customer for Asia testing

Thu, 3 Mar 2011

Multitest announced that a major fabless semiconductor manufacturer has evaluated and approved its Mercury-based wafer-level contactors for subcontractors in Asia.


TSV substrates for power amplifiers A*STAR IME partners with ELTA Systems

Mon, 3 Mar 2011

The collaboration will result in new applications in multi-chip modules in radar, communication, and electronic warfare systems. The new technology platform would enable miniaturization of wireless applications that are faster, lighter and can withstand higher temperatures.


Two-element wafer-level camera from Nemotek boasts low distortion

Tue, 2 Feb 2012

Nemotek Technologie uncrated a two-element wafer-level camera, Exiguus H12-A2. The two-element lense gives Exiguus H12-A2 high resolution and low (<0.5%) distortion.


Present at ESTC 2012 in Amsterdam

Tue, 2 Feb 2012

Electronics System Integration Technology Conference (ESTC) 2012 seeks original papers describing research in all areas of electronic packaging, including LED packaging, flexible electronics, assembly and interconnect technologies, and more.


Amkor plans IMAPS Device Packaging keynote

Tue, 2 Feb 2012

The 2012 IMAPS Device Packaging Conference will take place March 6-8 in Fountain Hills, AZ, with Amkor's Dr. Robert Darveaux presenting "Escalating Challenges in Developing Complex Solutions for Next Generation Package and Interconnect Technologies."


Amkor continues cost reductions with voluntary retirement in Japan

Fri, 2 Feb 2012

Amkor (NASDAQ:AMKR) shared that it cut costs through workforce reductions in Q4 2012, and announced a voluntary retirement program in Japan to continue this initiative.


Kyocera doubles flip-chip assembly with new cleanroom in US

Tue, 2 Feb 2012

Kyocera America, Inc. doubled its flip chip assembly capacity for microelectronic devices with a $3.5 million Class-10,000 cleanroom, offering lead-free processes in San Diego.


STATS ChipPAC shutters Thailand semiconductor packaging plant after floods

Wed, 2 Feb 2012

STATS ChipPAC decided not to resume semiconductor assembly operations in its Thailand plant, owing to extensive equipment and facility damages sustained during the disastrous floods in 2011.


USPTO seeks nominees for National Medal of Technology and Innovation

Tue, 1 Jan 2012

The USPTO is looking to increase the diversity of honorees for its annual National Medal of Technology and Innovation (NMTI), honoring "this nation's creative geniuses."


WLCSP QFN ELP Semiconductor packaging for consumer applications

Wed, 1 Jan 2011

Semiconductor packaging for consumer products. Source: UnisemThere are a few key attributes in new consumer electronics: a reduced footprint and/or profile, high electrical performance, fine-pitch design, custom features, and a low cost. Multi-row, wafer-level, flip-chip, and multi-chip packaging can meet these needs, say Unisem writers Rico San Antonio and Chris Stai. They compare the value of each packaging type.


Wafer level packaging of image sensors

Sat, 1 Jan 2011
Wafer-level packages that use a glass cover over the package cavity and through-silicon vias to interconnect the die bond pads satisfy the packaging requirements for CMOS image sensors: compact, reliable, low cost, and accommodate both front- and back-illuminated image sensors with no external changes. Giles Humpston, Tessera Inc., San Jose, California, USA

Tooling and process technology vital for thin packages

Tue, 1 Jan 2011

Getting thinner appears to be the goal driving the market in both the wafer-level and substrate-level sectors, and innovative tooling and process technology will become paramount in addressing thinned packaging and ramping up to volume reliably, writes Dave Foggie from DEK.


QFN leadframes without plating etching waste or bulk EoPlex

Mon, 1 Jan 2011

EoPlex model showing different materials (colors) and different metastructures (patterns).Arthur Chait, president and CEO of EoPlex, describes the company’s high-volume print forming technology -- a lead carrier product called xLC-- and how it enables a cost-effective replacement for conventional quad flat pack no-lead (QFN) leadframes.


Low shrinkage adhesive for optical assembly

Thu, 1 Jan 2011

DYMAX OP-67-LS opto-mechanical adhesiveA fast-cure, low-shrinkage adhesive for optics and optical assembly, DYMAX OP-67-LS opto-mechanical adhesive cures in seconds for bonding of optical components. The product's low-shrink nature virtually eliminates movement during curing and subsequent thermal cycling.


Lifting the veil on silicon interposer pricing

Mon, 12 Dec 2012

Are we closer than we think to our needed mass production costs for silicon interposers? Phil Garrou gleans some insights from the year-ending RTI Architectures for Semiconductor Integration and Packaging conference.


Singapore IME launches 2.5D silicon interposer MPW

Wed, 12 Dec 2012

Singapore's Institute of Microelectronics (IME) has launched a new multiproject wafer service for 2.5D through-silicon interposers, to provide a cost-effective platform for R&D prototyping and proof-of-concept in the technology.


Tezzaron licenses Ziptronix's bonding tech for 3D memory

Mon, 12 Dec 2012

Tezzaron Semiconductor has licensed patents regarding Ziptronix's direct bonding technologies, "direct bond interconnect" (DBI) and "direct oxide bonding (ZiBond), for use in 3D memory.


Will the $2 interposer be silicon or glass?

Tue, 11 Nov 2012

Dr. Phil Garrou reports from the 2nd annual Georgia Tech 2.5D Interposer Conference: what's the market projection for silicon and glass interposers, what's preventing high-volume manufacturing, and is there a crossover with flat-panel display glass manufacturing?


Alchimer pursuing partners with new CEO, CTO

Tue, 11 Nov 2012

Alchimer SA says it is seeking partnerships with various semiconductor equipment and materials companies as it welcomes two top execs: Bruno Morel is the company's CEO since May of this year, and product development director Fr

Deca tips new M-Series chip-scale packaging offering

Wed, 11 Nov 2012

Deca Technologies has introduced a new chip-scale packaging (CSP) product line for applications where its existing wafer-level CSP option isn't a good fit. Details and analysis to come.


Texas Instruments (TI) embedded die package teardown report released

Thu, 3 Mar 2012

Texas Instruments' MicroSiP module is the first embedded die package in high volume production. Yole D

Altera taps Amkor for molded flip chip packaging of FPGA family

Wed, 3 Mar 2012

Altera Corporation will use an exposed-die molded flip chip technology from Amkor on its 28nm Arria V FPGA. Amkor

Amkor (AMKR) names Taiwan leader with semiconductor packaging background

Fri, 3 Mar 2012

Amkor Technology Inc. (Nasdaq: AMKR) added Mike Liang as president of Amkor Technology Taiwan. Liang's background includes stints with Phoenix Semiconductor, Ti-Acer, UMC, and others.


AMAT, Singapore's microelectronics institute open 3D semiconductor packaging R&D lab

Wed, 3 Mar 2012

Applied Materials Inc. (AMAT) opened the new Centre of Excellence in Advanced Packaging at Singapore

STATS ChipPAC brings FOWLP to stacked packages for <1mm profile

Tue, 3 Mar 2012

STATS ChipPAC Ltd. (SGX-ST:STATSChP) uncrated its next-generation eWLB package-on-package (PoP) technology, with a package profile height below 1.0mm.


Flip chip bumping, WLP partnership unites FCI and NANIUM

Tue, 3 Mar 2012

"Together, FCI and NANIUM offer a complete WLP service portfolio covering 150, 200 and 300mm wafer sizes," summarized Armando Tavares, NANIUM president of Executive Board.


Plessey Semiconductors debuts ECG sensor from passive component project

Mon, 3 Mar 2012

Plessey Semiconductors developed the Electric Potential Integrated Circuit (EPIC) sensor, optimized for use as an ECG sensor, at a reportedly lower cost and better resolution than conventional electrodes. It enables ECG monitoring in mobile phone applications.


ICECool puts 3D thermal issues back in focus

Mon, 10 Oct 2012

With the approach of full commercial production of 3DIC products, Dr. Phil Garrou shifts his attention to thermal performance questions and proposed thermal solutions for the future.


Why SATS consolidation needs to happen

Fri, 10 Oct 2012

The advent of leading-edge semiconductor packaging technologies dictates efficient use of capital, and only the top-tier semiconductor assembly and test services (SATS) companies will have the financial wherewithal to develop required expertise and capacity, says one analyst.


Nanium ships 200 millionth eWLB component

Wed, 10 Oct 2012

Nanium says it has shipped its 200 millionth embedded wafer-level ball grid array technology (eWLB) component, a 10% year-over-year productivity increase that reflects full conversion to the company's eWLB overmold technology that allows thinner and more robust packages.


KIT develops "photonic wire bond" for optical chip connections

Thu, 9 Sep 2012

Researchers at the Karlsruhe Institute of Technology (KIT) say they have developed a novel optical connection process for semiconductors using "photonic wire bonding" that achieves data transmission rates of several Tbit/sec.


UMC, ST to develop 65nm backside CMOS image sensors

Mon, 9 Sep 2012

Rudolph wins order for advanced packaging metrology systems

Thu, 9 Sep 2012

An unidentified "premier global industry research center in Asia" will use Rudolph Technologies' MetaPulse G metrology system in its advanced packaging process development activities.


Ultra Tec adds endpoint detection module for chip package sampling

Tue, 9 Sep 2012

Ultra Tec Manufacturing has released a new endpoint detection module for its ASAP-1 IPS selected area preparation system, for improving electronic package decapsulation and sample preparation.


FormFactor to acquire Microprobe, creates top probe card supplier

Tue, 9 Sep 2012

Wafer probe card maker FormFactor has agreed to acquire fellow probe card supplier MicroProbe, with a combined entity rivaling top-seller Micronics in the high-growth probe card market.


Microsemi unveils tiny die packaging for implantable medical devices

Mon, 8 Aug 2012

Microsemi says its new die packaging technology, targeting implantable medical devices such as pacemakers and cardiac defibrillators, can be paired with an ultralow-power radio for wireless health monitoring.


Super QFN goal of EoPlex xLC lead carrier substrate

Fri, 4 Apr 2011

EoPlex Technologies Inc. is promoting the xLC substrate for quad flat pack no lead (QFN) semiconductor packages. The substrate enables QFNs with hundreds of leads and multiple rows at a lower cost than conventional packages.


Copper pillars appear in packages from Amkor to Unisem, says Vardaman

Thu, 4 Apr 2011

Following Intel's lead, many companies are moving to adopt copper pillar as the technology for their flip chip applications, as well as leadframe packages. E. Jan Vardaman, president of TechSearch International, says the move to Cu pillar is reminiscent of the transition from the evaporated bump to the plated bump.


Beyond ball shear test Microprobing chip/package stress at Stanford

Wed, 4 Apr 2011

IITC paper, Stanford UniversityNew work from Stanford goes beyond simple bump shear testing to allow simulation of stresses exerted on chips during semiconductor packaging. The researchers are able to explore how the stresses affect back-end structures. Alex Hsing, a PhD student in Professor Reinhold Dauskardt's Group at Stanford University, summarizes the group's approach.


Questar wedge and ball wire bonders target small lots, high variation

Wed, 4 Apr 2011

Questar's Q7000 series of fine-pitch, fine-wire (17-75μm), aluminum/gold (Al/Au) automatic wedge and ball bonders Questar Products International released the Q7000 series of fine-pitch, fine-wire (17-75μm), aluminum/gold (Al/Au) automatic wedge and ball bonders to better meet smaller lot size, multiple product variation, frequent set-up change styles of package production.


Multi depth imaging system shows defect progress

Tue, 4 Apr 2011

Depths 15 to 18 (of 50 depths) in a ceramic chip capacitor, imaged acoustically and simultaneously with Sonoscan’s automated multi-gate system.Sonoscan has demonstrated the single-scan imaging of a sample at 50 different depths, or gates, a technique called PolyGate. It reveals how features, including defects, change from one gate to the next.


Applied Materials creates WLP center with Singapore Institute of Microelectronics

Wed, 4 Apr 2011

Applied Materials Inc. (AMAT) signed an agreement with the Institute of Microelectronics to set up a Center of Excellence in Advanced Packaging in Singapore. The Center will have a full line of wafer level packaging processing equipment and will conduct research in semiconductor hardware, process, and device structures.


Packaging Roadmaps at MEPTEC

Fri, 4 Apr 2011
Phil Garrou, Contributing Editor

Thermal analysis system tracks temp, air velocity and pressure from multiple points

Fri, 4 Apr 2011

iQ-200 thermal analysis system Advanced Thermal Solutions, ATS, has released the iQ-200 thermal analysis system for precisely and simultaneously measuring the temperatures of solid materials and the surrounding air, as well as tracking air velocity and air pressure at multiple points to comprehensively profile heat sinks, components, and PCBs.


Reworkable edgebond adhesive improves CBGA and BGA thermal cycle performance

Thu, 4 Apr 2011

After removal of underfilled BGA, underfill residues must be removed.Zymet Inc. introduced a reworkable edgebond adhesive, UA-2605, that improves thermal cycle performance of CBGAs and plastic BGAs. The adhesive can prevent pad damage during BGA rework, particularly with fine-pitch BGAs.


Tessera focuses on semiconductor technologies beyond packaging

Thu, 4 Apr 2011

Tessera Technologies Inc. (Nasdaq:TSRA - News) began two corporate initiatives to expand its technologies in semiconductor microelectronics beyond packaging, and to potentially separate its Imaging & Optics business.


Keithley 2652A SourceMeter tests high power semiconductors

Wed, 4 Apr 2011

Keithley Instruments Model 2651A High Power System SourceMeter Keithley Instruments Inc., advanced electrical test instruments and systems provider, introduced the Model 2651A High Power System SourceMeter instrument to characterize high-power electronics, like HB-LEDs, power semiconductors, DC-DC converters, batteries, etc.


Verigy wins Freescale test equipment order

Wed, 4 Apr 2011

Freescale Semiconductor's Networking and Multimedia Group (NMG) placed a volume order for Verigy's V93000 scalable test platform to use in testing select QorIQ PowerPC communications microprocessors, based on Power Architecture technology.


Cu wire bonding joins MagnaChip Semiconductor offerings

Tue, 4 Apr 2011

MagnaChip Semiconductor now offers cost-competitive and state-of-the-art copper wire bonding technology, which can create a packaging cost savings of about 20% to 30%. MagnaChip worked with the major packaging companies to develop a bonding process that protects wafers under bond pads.


SiliconBlue 40nm mobileFPGA roadmap targets sensor management, mobile display

Mon, 4 Apr 2011

SiliconBlue Technologies unveiled its mobileFPGA platform device roadmap using TSMC's 40nm low power standard CMOS process. The two distinct families target the two areas where smartphones and other handhelds differentiate.


Thinfilm PARC bring printed electronics commercialization engagement forward

Mon, 4 Apr 2011

Thin Film Electronics ASA (Thinfilm) and PARC, a Xerox company, entered the next phase of their co-innovation engagement for printed memory devices. This next phase extends the engagement to prototyping the product for manufacturing readiness.


HB LED packaging materials pros and cons

Fri, 4 Apr 2011

LEDDaniel Duffy, research scientist in Henkel's Advanced Technology Group, notes pros and cons of epoxy and silicone encapsulants for high-brightness LED (HB-LED) manufacturing, and what HB-LED manufacturers need from die attach materials. He also considers quantum dots.


Invensas demos DFD implementation of its xFD technology

Mon, 9 Sep 2011

Invensas president Simon McElrea explains the company's new wire bond-based multi-die face-down (xFD) packaging technology, demo'd at this year's Intel Developer Forum, and its advantages in terms of performance and manufacturing cost reductions.


Wafer packaging database provides WLP data

Fri, 9 Sep 2011

Research and Markets released "Wafer Packaging Fab Database," providing a global overview over 150 companies' 250+ mid-end semiconductor packaging houses.


Open microfocus X-ray tubes gain automatic venting

Thu, 9 Sep 2011

X-RAY WorX GmbH introduced electronically controlled venting valves for open X-ray tubes. This avoids the manual venting typically performed during X-ray tool maintenance.


Present on interposer technology

Tue, 9 Sep 2011

The first annual Global Interposer Technology Workshop at Georgia Tech will convene students, academics, researchers, and industry to share information on silicon and glass interposers for semiconductor packaging.


Advanced semiconductor package test emphasized at new BiTS Workshop

Fri, 9 Sep 2011

The Burn-in & Test Socket Workshop (BiTS Workshop) is changing its name to The Burn-in & Test Strategies Workshop to reflect the "evolution of packaged ICs."


Honeywell doubles semiconductor Cu and Sn production

Thu, 9 Sep 2011

Honeywell (NYSE:HON) Electronic Materials will more than double refining and casting capacity for high-purity copper and tin at its Spokane, WA, facility, citing increased demand from memory and semiconductor packaging sectors.


IRphotonics installs thermal camera for IR cure R&D

Wed, 9 Sep 2011

IRphotonics added a high-resolution FLIR thermal imaging camera to its application engineering lab. The camera will be used to analyze heat distribution during iCure use.


SEMICON Europa preview

Tue, 9 Sep 2011

SEMICON Europa 2011 will take place October 11-13 at Messe Dresden in Dresden, Germany. The event covers new technologies and products for advanced microelectronics manufacturing. This year has more co-located events than ever before.


Rudolph: NSX package inspection system sales top 1000

Mon, 9 Sep 2011

Rudolph Technologies Inc. (NASDAQ:RTEC) shipped the 1000th NSX Inspection System from its Bloomington, MN manufacturing facility. The NSX inspects wafer bumps, WLP, MEMS, and more.


Multi-die face-down packaging suits existing wire bond lines

Thu, 9 Sep 2011

Invensas Corporation, a Tessera subsidiary, will demonstrate dual-face down implementation of its new multi-die face-down packaging technology at the Intel Developer's Forum. The multi-die package is wire bonded, mounting ICs upside down and staggering them in a shingle-like configuration.


3M, IBM to make 3D chip adhesives

Wed, 9 Sep 2011

Forget "3D stacking" -- the two companies say a special electronic "glue" applied to the wafer will help stack dozens of chips into a "silicon skyscraper" that will be much faster and more efficient than current chip technology.


AMKR authorizes $150m stock repurchase

Wed, 8 Aug 2011

Amkor Technology's Board of Directors authorized the repurchase of up to $150 million of AMKR common stock, to enhance stockholder value and support its business model.


Gold wires go brittle at nanoscale

Mon, 8 Aug 2011

Gold wires are used in electronic devices due to the material's flexiblity and conductive quality. At the nanoscale, however, gold wires (<20nm wide) become "brittle-like" under stress, according to a new study at Rice University.


STATS ChipPAC expands wafer-level chipscale packaging in Taiwan

Thu, 11 Nov 2011

STATS ChipPAC Ltd. completed the expansion of its 300mm wafer bump and wafer-level chipscale packaging (WLCSP) operation in Taiwan.


Report examines fan-out wafer-level packaging momentum, assembly pricing trends

Wed, 11 Nov 2011

Fan-out wafer-level packaging (FO-WLP) is gaining momentum as an option for devices with large numbers of I/Os, vs. going finer-pitch to keep using conventional fan-in technology, says TechSearch International in an updated report.


SUSS MicroTec sends equipment to SVTC in MEMS, 3D IC dev partnership

Tue, 11 Nov 2011

Nanotechnology accelerator SVTC Technologies partnered with SUSS MicroTec on wafer-level packaging for MEMS, and 3D IC bonding technology development.


Microsemi taps Amkor for SoC package test

Mon, 11 Nov 2011

Microsemi SoC Products Group will use outsourced semiconductor assembly and test (OSAT) provider Amkor Philippines (ATP) for final electrical package test on nearly all its products.


Fujikura, FlipChip International improve embedded die packages

Fri, 11 Nov 2011

Fujikura Ltd. and FlipChip International LLC (FCI) released ChipletT and ChipsetT embedded die packages for single die or multi-die semiconductor packaging applications.


Backside-illuminated image sensors: Optimizing manufacturing for a sensitivity payoff

Fri, 11 Nov 2011

Backside-illuminated image sensors require more precise wafer processing -- uniform extreme wafer thinning, dopant control, epitaxy growth, trench manipulation, etc. -- but the payoff in image quality is significant. Researchers at imec experimented with different wafer fab technologies to make a record BSI sensor. They also consider new architectures/packaging techniques for this technology.


WLP start-up combines SunPower solar silicon fab with Cypress semiconductor interconnect

Wed, 11 Nov 2011

Deca Technologies, a new company backed by Cypress Semiconductor and SunPower, will combine solar wafer manufacturing methods with semiconductor manufacturing support to create wafer-level chipscale packaging (WLCSP) derivatives.


Thailand flood update from key semiconductor assembly and test companies

Fri, 11 Nov 2011
Numerous global semiconductor suppliers maintain assembly and test operations in Thailand. Many of these facilities have been affected by the disaster. IHS iSuppli pulled together a list of those affected, and those that have thus-far escaped damage.

Steve Adamson passes; Nordson plans memorial scholarship

Fri, 11 Nov 2011

Nordson Corporation will honor the life of Steven J. Adamson, former Nordson ASYMTEK marketing specialist and electronics industry mentor, by funding a $3,000 annual scholarship in Adamson's name with the IMAPS Educational Foundation.


Multitest passes BGA test evaluation at IDM

Fri, 11 Nov 2011

Multitest's Mercury contactor passed a "thorough BGA test evaluation," landing on the qualified contactors list for all business units of an international IDM.


MOSAID taps Winpac to package fastest NAND Flash device

Wed, 11 Nov 2011

MOSAID launched the 256Gb HLNAND2 semiconductor memory device, operating at up to 800MB/s per channel for mass storage applications. Winpac will package and distribute HLNAND devices for MOSAID.


SRC attacks 3DIC reliability, design tools with new effort

Thu, 5 May 2011

Semiconductor Research Corporation is leading an effort to address key roadblocks for wide-scale adoption of the emerging 3D ICs and systems. These new initiatives will address critical reliability and design tool issues and leverage partnership between researchers from universities and the semiconductor industry.


NXP metrology labs tap Tektronix for test/measurement equip calibration and repair

Thu, 5 May 2011

NXP named Tektronix Service Solutions to provide calibration and repair services for all test and measurement instruments at NXP's production and development sites in the Netherlands.


Leadframe package design tool combines CAD Design, Cadence IP

Wed, 5 May 2011

CAD Design Software combined its Electronics Packaging Designer (EPD) and Cadence Design Systems' Allegro IC Package design and analysis environment to create a "Silicon Realization" flow for ICs in leadframe packages.


STATS ChipPAC invests in copper wire bonding for 45nm, low-k

Wed, 5 May 2011

STATS ChipPAC Ltd. (SGX-ST: STATSChP), semiconductor test and advanced packaging service provider, has shipped over 300 million semiconductor packages with copper wire-bond interconnects. The SATS provider is investing in Cu wire bonding for finer silicon nodes (45/40nm) and low-k/extra low-k.


GN ReSound taps eSilicon for ASIC ramp up

Tue, 5 May 2011

Hearing aid maker GN ReSound contracted with eSilicon Corporation, independent semiconductor Value Chain Producer, for production of the AD4.0 ASIC. This ASIC is a key component in next-generation hearing instruments from GN ReSound.


NASA orders Flexpoint Bend Sensors

Mon, 5 May 2011

Flexpoint was unable to reveal the application in which NASA is using Bend Sensors, though Clark Mower, president of Flexpoint, called the project a "new and expansive area of potential use of our technology."


IC packaging report covers 12 package types + bare die, SATS providers

Thu, 4 Apr 2011

New Venture Research will release "The Worldwide IC Packaging Market, 2011 Edition" in May 2011. It provides analysis of packaging by I/O count and package type, bare die interconnect, and looks at the major semiconductor assembly and test services (SATS) providers.


Semiconductor materials group prez joins JSR Corp's Officers Committee

Thu, 4 Apr 2011

Tokyo-based JSR Corporation named the first non-Japanese Officer to its Officers Committee. Eric R. Johnson, the current president of the company's US semiconductor materials operations, JSR Micro, has been named as an Officer.


Asian semiconductor packaging specialist orders SPTS etch, PVD and CVD technologies for TSV

Tue, 4 Apr 2011

SPP Process Technology Systems (SPTS) won a multi-system order for its Sigma PVD, Omega Etch and Delta CVD wafer processing systems from a leading outsourced semiconductor assembly and test (OSAT) provider in the Asia-Pacific region.


Molded flip chip imaging improved at Sonix

Mon, 4 Apr 2011

Sonix Inc. introduced its Molded Flip Chip Imaging (MFCI) enhancement. Sonix Inc. introduced its Molded Flip Chip Imaging (MFCI) enhancement. Sonix MFCI improves image quality and defect detection in molded flip chips and packages with polyimide (PI) layers.


Laird phase change material enables stencil applied TIM

Sat, 4 Apr 2011

Laird Technologies released the Tpcm 580SP Series phase change material, a high-performance, screen-printable or stencilable thermal interface material with a thermal conductivity of 4.0W/mK that provides an alternative to thermal grease.


Electronics packaging leaders gathered under cherry blossoms at ICEP

Thu, 4 Apr 2011

ASE FOWLPT.Onishi, Grand Joint Tech and E.J. Vardaman, TechSearch International share the highlights on low-k dielectrics, 3D packaging, copper pillar, and other exciting work presented at the International Conference on Electronics Packaging (ICEP) in Japan.


Multitest ECON contactor exceeds 4.5M insertions

Tue, 4 Apr 2011

Multitest's ECON contactor exceeded 4.5 million insertions at an Asian test house. The contactor performance resulted in a 99% stable test yield.


STATS ChipPAC expands TSV service with mid end flow

Tue, 4 Apr 2011

STATS ChipPAC Ltd. (SGX-ST: STATSChP), semiconductor test and advanced packaging service provider, is expanding its 300mm through silicon via (TSV) offering with the addition of mid-end manufacturing capabilities.


Flip chip still in growth phase, even at $16B

Mon, 4 Apr 2011

2010 total flip chip market value. Split by cost-of-ownership supply chain segments (substrates for LCD drivers excluded, service margin included). SOURCE: Flip Chip report, Yole Développement, April 2011.Yole reports on the flip chip market, and finds that this $16 billion industry, with diverse applications, is still growing. New flip chip technologies, such as copper pillars, and technology demands, such as fragile 28nm chips, are driving demand.


SATS provider Sigurd chooses Multitest MT2168

Thu, 3 Mar 2011

Multitest MT2168 semiconductor test handlerSigurd Microelectronics Corporation (Sigurd) will be the first adopter of Multitest's MT2168 pick-and-place test handler in volume production in Taiwan. The SATS provider will use it to test various QFN packages.


NXP claims smallest logic package

Tue, 3 Mar 2011

The SOT1115 package decreases package size by 10% for the 6-pin version. The 8-pin SOT1116 decreases the package size by 60%.NXP Semiconductors N.V. (NASDAQ: NXPI) says that it has developed the smallest logic leadless plastic packages measuring 0.9 x 1.0 x 0.35mm with 0.3mm pitch. The packages also demonstrate 4x better mechanical adhesion to the PCB than other packages in the same form factor.


Fujitsu resumes back end operations after Japan earthquake

Fri, 3 Mar 2011

About a fortnight since the 8.9 earthquake struck Japan near Sendai, Fujitsu has resumed some operations at its back-end packaging and semiconductor testing sites.


Supertex halves board space with 42 ball bumped die package

Wed, 3 Mar 2011

 Supertex (NASDAQ: SUPX) will package its HV2601 and HV2701 16-channel, low-charge injection, 200V analog switch ICs in 5.29 x 5.30mm, 42-ball bumped die packages. This packaging represents a 50% space savings over the previous 48-ball fpBGA package.


Si2 Microsystems will test fire samples for THT

Tue, 3 Mar 2011

Torrey Hills Technologies (THT) signed an agreement with Si2 Microsystems Pvt Ltd., India-based microelectronics company and THT furnace customer, for the use of its furnace to test-fire samples sent from THT's potential semiconductor, packaging, and solar cell clients.


IEEE surpasses 400000 members

Fri, 3 Mar 2011

IEEE reached the 400,000 member mark for the first time in its history. By the end of 2010, total IEEE membership had surpassed 400,000, making it the seventh consecutive year the association had experienced membership growth.


NuPGA becomes MonolithIC 3D, expands IP in monolithic 3D semiconductor space

Thu, 3 Mar 2011

As it developed an improved FPGA technology, the NuPGA team discovered a path for practical monolithic 3D ICs. MonolithIC 3D changed its strategy to focus on monolithic 3D IC technology as a pure IP innovator organization.


Silicon interposers embedded capacitors subject of ALLVIA presentation at IMAPS Device Packaging

Wed, 3 Mar 2011

ALLVIA, through-silicon via (TSV) foundry, will present its latest analysis on silicon interposers and embedded capacitors during the IMAPS Conference on Device Packaging in Scottsdale, AZ, March 9. Dr. Sergey Savastiouk, CEO at ALLVIA, will present "Silicon Interposers Enable High Performance Capacitors."


NVIDIA licenses SMSC Inter Chip Connectivity technology

Wed, 3 Mar 2011

NVIDIA Corporation (NASDAQ: NVDA) has licensed Inter-Chip Connectivity (ICC) technology from SMSC (NASDAQ: SMSC), a leading semiconductor company creating valued connectivity ecosystems.


TSMC, Arteris develop silicon-interposer-based NOCs

Wed, 12 Dec 2011

Arteris Inc., network-on-chip (NoC) interconnect IP company, will incorporate its FlexNoC NoC interconnect IP into an SoC die on silicon interposer test chip with TSMC.


Partnership forms to commercialize advanced photonic chip innovations

Tue, 11 Nov 2011

The Institute of Microelectronics, a research institute of Singapore's A*STAR, plans to commercialize key innovations in silicon photonic chips designed to support high-speed, high-bandwidth optical communications.


OSRAM envelops LED chip in reflective package

Tue, 11 Nov 2011

OSRAM Opto Semiconductors introduced the Oslon Square LED for lighting applications, packaged enclosed in a reflective layer to boost light output.


Cirrus Logic awards STATS ChipPAC for packaging services

Mon, 11 Nov 2011

SATS provider STATS ChipPAC Ltd. (SGX-ST:STATSChP) was named "Supplier of the Year" by Cirrus Logic Inc. (NASDAQ:CRUS), analog and mixed-signal processing components maker.


Hynix renews Tessera license

Thu, 11 Nov 2011

Hynix Semiconductor Inc. exercised the renewal option in its March 31, 2005 license agreement with Tessera Technologies Inc. (NASDAQ:TSRA) to extend the term of that license to May 22, 2017.


AKM consigns chip test equipment to ChipMOS' ThaiLin under new service agreement

Tue, 11 Nov 2011

ChipMOS subsidiary ThaiLin Semiconductor Corp. will take on dedicated semiconductor testing capacity for a new long-term service agreement with its client Asahi Kasei Microdevices Corporation (AKM).


Fairchild, Infineon compatibility agreement aligns power MOSFET packages

Thu, 4 Apr 2010

Fairchild Semiconductor and Infineon Technologies formed a packaging partnership for their power MOSFETs in the MLP 3x3 (Power33 or S3O8) and PowerStage 3x3 packages.


Gold group reiterates industry "concerns" about Cu bonding

Fri, 4 Apr 2010

A seminar held at last month's Semicon China reiterated points made earlier in the year by an industry group that there are still questions about using copper bonding wire vs. gold in semiconductor packaging applications.


Future implications of IC packaging for the PCB

Tue, 4 Apr 2010

Vage Oganesian of Tessera and Vern Solberg, Tessera consultant, discuss the advanced packaging options available with 3D contact features on substrate interposers for complex, high-pin-count flip chip applications.


TSMC repeats call for foundry-centric 2.5/3D industry

Thu, 12 Dec 2011

The readiness of suppliers to offer 2.5D packaging technologies was in full debate at the RTI 3D ASIP event this month, with presentations and rumors questioning how soon customers will need 2.5D/3D, and whether some offerings are worth the investment.


Advanced package technologies' growth through 2015

Tue, 12 Dec 2011

Small, mobile, Internet-connected devices are bucking the slow economy and use advanced packaging technologies to pack an enormous amount of functionality into a very small form factor, notes New Venture Research, which provides forecasts for each advanced packaging device type.


Amkor PoP tech surpasses 100M units

Sat, 12 Dec 2011

Amkor Technology Inc. (Nasdaq:AMKR), semiconductor assembly and test services (SATS) provider, has shipped more than 100 million units of its Through Mold Via (TMV) package-on-package (PoP) products.


Fan-in WLCSP outpaces semiconductor packaging market

Thu, 12 Dec 2011

Yole identifies the fan-in wafer-level chipscale packaging (WLCSP) market for strong growth, and a diverse base of chip technologies. Fan-in WLCSP reached 2.3 million 300mm-equivalent wafers shipped in 2011, or about $1.7 billion in revenue.


Powertech seeks 30-51% of Greatek

Mon, 12 Dec 2011

Powertech Technology Inc. (PTI) has approved a tender offer of NT$25.28 per share for the common shares of Greatek with a minimum acquisition target of 30% of outstanding shares.


IPC, JEDEC devise package strain test

Thu, 12 Dec 2011

IPC and JEDEC created

Embedded WLP, TSV interposers, copper pillar, materials: 4 projects of IME packaging consortium

Wed, 6 Jun 2011

Singapore's Institute of Microelectronics (IME), a research institute of the Agency for Science, Technology and Research (A*STAR) launched the 11th cycle of its 15-year packaging R&D with 23 companies and 4 main projects.


LORD underfill encapsulant designed for lower cost

Wed, 6 Jun 2011

LORD ME-555 LORD Corporation launched the ME-555 underfill encapsulant for semiconductor packaging and assembly. LORD ME-555 is a high-purity, semiconductor-grade epoxy underfill for encapsulating flip chips.


Tektronix buys Teradyne testers for better test dev, IC test range

Wed, 6 Jun 2011

Tektronix Component Solutions purchased 5 Teradyne J750EX semiconductor test systems to screen a wider variety of complex ASICs, increase test capacity, and generate test programs faster.


Honeycomb heatsink cools BGAs in thin-profile devices

Tue, 6 Jun 2011

JaroThermal's Honeycomb heatsink JaroThermal's Honeycomb heatsink directs heat towards the outside of the device, while producing a steady flow of cool air inside the heatsink. Honeycomb heatsinks can be used with either plastic or metal/ceramic BGA packages.


NXP assembles RF power transistors in plastic packages

Fri, 6 Jun 2011

NXP Semiconductors N.V. (NASDAQ: NXPI) launched overmolded plastic (OMP) RF power devices with 2.5-200W peak power. The plastic packages are a lower-cost option alongside NXP's ceramic package RF devices.


New power MOSFET package from IRF minimizes form factor

Mon, 6 Jun 2011

ternational Rectifier, (IR, NYSE:IRF), power management technology provider, introduced a PQFN 2 x 2mm with <1mm profile package featuring its latest HEXFET MOSFET silicon. The new package is ultra-compact, high density and efficient for lower-power applications.


Flip chip probe card from Wentworth Laboratories withstands high-power, high-density test

Tue, 6 Jun 2011

The AccumaxDirect premier vertical probe card from Wentworth Laboratories withstands "severe test parameters" in high-volume flip chip/C4 test. It was just approved for use with Verigy testers.


GA Tech's Rao Tummala recognized with major IEEE packaging award

Wed, 6 Jun 2011

IEEE's Field Award for microelectronics packaging contributions goes to GA Tech's Rao Tummala, a longtime IBM research who pioneered packaging integration research and globalization of electronic packaging.


More Moore & More than Moore require fabless, foundry, and packaging houses on board

Tue, 5 May 2011

Complex supply chain. SOURCE: Yu, The ConFabToday at The ConFab, John Chen (Nvidia), Jeong-ki Min (Samsung Electronics), and Abraham Yee (Nvidia) gathered foundry, OSAT, and chip maker leaders to discuss what happens beyond Moore's Law. The following are key points from "Collaboration to Strengthen the IC Supply Chain."


LCP packaging tech from RJR Polymers competes with ceramics for QFN, RF power packages

Tue, 5 May 2011

RJR Polymers debuted liquid crystal polymer (LCP) semiconductor packaging technology for RF and microwave system designers that is competitive with ceramic ACPs, improving thermal management and offering design flexibility based on the company’s epoxy range.


STATS ChipPAC widens fan-out WLP configurations with TSVs, IPDs

Tue, 5 May 2011

STATS ChipPAC says integrating through-silicon vias with passive devices and its eWLB technology addresses complex design issues, shrinking lithography nodes, and increased performance demands for mobile and consumer applications.


What SEMICON West offers packaging professionals in 2011

Thu, 6 Jun 2011

SEMICON West is a major conference for semiconductor manufacturing professionals. Semiconductor packaging has become a major focus in recent years, and this year, BEOL attendees have ATE Vision 2020, 3D IC standards meetings, a keynote, and multiple sessions dedicated to packaging technologies. Here's your guide to attending SEMICON West on a packaging track.


Chip Supply changing its name to Micross Components, consolidating several facilities in Orlando

Wed, 5 May 2011

Semiconductor die and packaging specialist Chip Supply Inc. is changing its name to Micross Components, which reflects the acquisition of Chip Supply last November by Micross Components. Micross provides specialist products and services for high-reliability and state-of-the-art electronics for high-reliability, industrial, and commercial applications.


3D stacked IC design flow gets boost from imec, Atrenta partnership

Wed, 5 May 2011

imec's 3D integration industrial affiliation program (IIAP) partnered with Atrenta Inc., SoC realization products provider to semiconductor and electronic systems industries, to developed an advanced planning and partitioning design flow for heterogeneous 3D stacked ICs.


Carsem expands MLP/QFN capacity in Suzhou

Tue, 5 May 2011

Artist's rendition of the expanded MLF/QFN production and test area at Carsem.Carsem will grow its Suzhou, China factory by an additional 430,000 square feet, increasing their Suzhou micro leadframe package (MLP) capacity to over 20 million per day, with a focus on copper wire bonding.


Agilent debuts benchtop SMU line to compete with expensive semiconductor analyzers

Tue, 5 May 2011

Figure. The Agilent B2900A 4.3" color LCD display supports graphical and numerical view modes, and enables test set-up and check test results quickly. Single view, dual view, graph view and roll view improve usability and productivity of bench-top test, debug and characterization. Agilent Technologies Inc. (NYSE:A) released the B2900A Series line of compact benchtop source/measure units (SMU) for semiconductor, component, and materials testing. The company claims that these SMUs offer capabilities competitive with semiconductor device analyzers.


Will PoP delay TSV adoption? TechSearch International analyzes the 3D technologies

Thu, 5 May 2011

PoP provides a cost/performance solution that solves business and logistics issues associated with stacking devices directly. 3D TSV, with its associated uncertainties, cannot yet meet PoP's benefits, says TechSearch International (TSI).


AMKR senior notes offering draws $400M

Mon, 5 May 2011

Amkor Technology (NASDAQ:AMKR) completed its offering of $400 million aggregate principal amount of its 6.625% Senior Notes due 2021. The proceeds from the offering will be used to fund the company's tender offer for the approximately $264.3 million aggregate principal amount of its outstanding 9.25% Senior Notes due 2016, for general corporate purposes.


Non-planar device scaling: SEMATECH talks TSV, SoC, SiP

Thu, 5 May 2011

The semiconductor industry is moving to 3D device structures, says Raj Jammy, SEMATECH, at The ConFab 2011, discussing TSV and system-in-package (SiP) opportunities and challenges. He also summarizes logic and memory roadmaps.


Ramtron taps KYEC for SATS on its F-RAM

Wed, 5 May 2011

Ramtron (NASDAQ: RMTR) named Taiwan-based King Yuan Electronics Co., LTD (KYEC) to provide semiconductor assembly and test services (SATS) for its entire line of F-RAM products.


Benchmark "mid-end" tools and materials for 3DIC and wafer-level packaging (WLP)

Fri, 5 May 2011

Yole Développement released "Equipment & Materials for 3DIC and Wafer-Level-Packaging," a database and complete report analyzing in detail the equipment and materials tool-box for wafer-level packaging (WLP). This semiconductor packaging technology falls into the "mid-end," where frontend semiconductor wafer fabs and backend packaging facilities both operate.


3D packaging disrupts the IC supply chain -- ConFab session dedicated to the OSAT/foundry/fabless relationship

Fri, 5 May 2011

The ConFab gathers semiconductor industry leaders to discuss the biggest trends in the chip manufacturing sector. One of these major trends is 3D packaging, and Session 2 on Monday (May 16) will combine packaging house, fabless, and foundry approaches to the new supply chain, with speakers from Amkor, GLOBALFOUNDRIES, STATS ChipPAC, and Qualcomm.


Rudolph's 3D package inspection system meets TSV, RDL, bump inspection needs

Thu, 5 May 2011

Rudolph Technologies' Wafer Scanner 3880 inspection and measurement systemRudolph Technologies (NASDAQ: RTEC) released the Wafer Scanner 3880 to inspect micro and standard bumps, through silicon via (TSV) post-via-fill copper protrusions (nails) and re-distribution layers (RDL) used in 3D IC packaging.


RDL: an integral part of today's advanced packaging technologies

Sun, 5 May 2011
RDL technology has been instrumental in the development of many advanced packaging technologies such as fan-in and fan-out WLP, and TSV applications. Philip Garrou, MCNC, Research Triangle Park, NC; Alan Huffman, RTI Int., Research Triangle Park, NC

Tessera CEO & president Nothhaft resigns, Young takes his place

Thu, 5 May 2011

Tessera Technologies, Inc. (NASDAQ: TSRA) Board of Directors appointed Robert A. Young, Ph.D., as president and CEO, taking over for Henry R. Nothhaft, who resigned to pursue his advocacy of smart innovation policies in Washington DC.


CoolChip's thermal management tech brings in MIT prize

Wed, 5 May 2011

CoolChip Technologies won the MIT Clean Energy Prize for their technology that reduces data center cooling needs with air-based CPU cooling.


RFaxis' pure-CMOS on-die coexistence filter reduces package size, current consumption

Tue, 5 May 2011

RFaxis released its patent-pending On-Die Coexistence Filter technology, designed to replace "bulky and expensive" stand-alone coexistence filters for cellular, mobile, and other devices.


Multitest adds extended temp control to MT9510 test handler

Fri, 5 May 2011

Multitest, a designer and manufacturer of final test handlers, contactors and load boards, now provides extended temperature control with its extended temperature calibration (XTX) on the MT9510 test handler.


CSCD WLCSP HVM test probe card retains pin, scales from x1 to x8

Fri, 5 May 2011

Cascade Microtech (CSCD) launched a WLCSP probe card series that retains pin position, scales from x1 to x8 on a per-die basis, and can be configured for individual die testing. The Viper series will be used for high-volume test to qualify known good die (KGD).


Amkor, Carsem patent dispute over wafer-level packaging continues

Fri, 8 Aug 2012

The U.S. Court of Appeals for the Federal Circuit issued a favorable ruling in Amkor's appeal in its patent infringement case against Carsem and affliates before the U.S. ITC, Amkor reports.


Tessera receives initial Amkor payment in court award

Tue, 8 Aug 2012

Tessera received an initial payment of approximately $20 million from semiconductor packaging company Amkor, related to the interim award issued by the International Court of Arbitration of the International Chamber of Commerce (ICC).


Wafer-level packaging start-up Deca Technologies appoints leader for Philippines

Fri, 8 Aug 2012

Deca Technologies, wafer-level packaging (WLP) services to the semiconductor industry, added Iain Meikle as VP of operations and managing director in the Philippines.


Tessera changes CFO, Neely brings high-tech experience

Thu, 8 Aug 2012

Tessera appointed Rick Neely, Jr. as EVP and CFO, responsible for the company

Flooding in the Philippines threatens microelectronics facilities

Thu, 8 Aug 2012

Heavy monsoons moving through the Philippines are causing floods in and around Manila, the capital. The Philippines is a small but growing area for microelectronics manufacturing and packaging facilities.


ASIC developers can now access multi-project wafer runs at Tektronix Component Solutions

Wed, 8 Aug 2012

Tektronix Component Solutions, a custom microelectronics services provider, tapped supply chain aggregator MOSIS to help its customers develop complete, high-performance ASICs with lower early-stage ASIC development costs.


Unisem appoints COO with semiconductor packaging experience

Thu, 8 Aug 2012

Unisem named Lee Hoong Leong as group COO, replacing Ang Chye Hock, who has retired. Lee brings experience from UTAC, STATS ChipPAC, TI, and National Semiconductor.


Flip Chip International names leader for Asia

Wed, 8 Aug 2012

FlipChip International (FCI), wafer-level packaging and flip chip bumping provider, named Weng Kay Lui as Asian sales director, overseeing sales for, among other areas, FCI's recently expanded FlipChip Millennium (Shanghai).


STATS ChipPAC adds director with experience from Intel to Zarlink

Wed, 7 Jul 2012

STATS ChipPAC appointed Gary Tanner as a member to its Board of Directors. Tanner brings experience from Zarlink Semiconductor, Intel, Texas Instruments, and other semiconductor companies.


2012 ITRS update: Back-end packaging and MEMS

Fri, 7 Jul 2012

At SEMICON West, the working groups of the International Technology Roadmap for Semiconductors (ITRS) outlined 2012 updates to the roadmap. Check out the back-end process info here.


New report on embedded and fan-out WLP from Research and Markets

Mon, 8 Aug 2010

Research and Markets released "Embedded Wafer-Level-Packages: Fan-out WLP/Chip Embedding in Substrate - 2010 Report," which covers embedded IC packaging markets, technology innovations, the manufacturing processes for fan-out and embedded wafer-level packaging, cost targets, and more.


Insights from SEMICON: Video interview with blogger Phil Garrou

Wed, 7 Jul 2010

In this video interview, Philip Garrou, microelectronics consultant and Advanced Packaging blogger, offers information on his blog, Insights from the leading edge, and summarizes reasonable roadmaps for 3D technology and TSV in particular. 2012 mainstream adoption seems too aggressive to Garrou.


TSV infrastructure and standardization questions with Matt Nowak

Tue, 7 Jul 2010

In this video, Matt Nowak, Qualcomm, talks about his keynote at ASMC on through silicon technologies for stacking die in advanced packaging applications.


Take the survey on PoP assembly

Fri, 7 Jul 2010

Package on package (PoP) stacking makes use of the vertical space available on electronics printed circuit boards (PCBs). It increases density, fitting more silicon into the same footprint. However, package stacking can be difficult, as fine pitches require placement accuracy, and taller stacks generally face reliability issues, especially if the stack is reflowed improperly. So where should PoP stacking take place?


Teledyne completes Intelek acquisition

Thu, 7 Jul 2010

Teledyne completed the acquisition of Intelek plc. Teledyne was the beneficial owner of, or had received valid acceptances in respect of approximately 93% of Intelek's ordinary shares. The aggregate value for the transaction will be approximately £35 million.


SEMICON West Lesson #3: 3D and packaging are hot

Mon, 7 Jul 2010

Wrap-up of what we heard and saw at SEMICON West 2010. Lesson 3: Everything about 3D & packaging was hot, with suppliers jostling to get into this next high-growth market. But are they really prepared for what awaits them?


STATS ChipPAC drawdown under credit facility for redemption at maturity of US$150.0 million 7.5% senior notes due July 19

Mon, 7 Jul 2010

STATS ChipPAC drew down US$150.0 million under the Credit Facility, and used the proceeds from this drawdown to redeem all US$150.0 million in outstanding principal amount of its 7.5% Senior Notes due 2010 at their maturity on July 19, 2010.


Cu protrusion, keep-out zones highlight 3D talks at IEDM

Wed, 12 Dec 2010

Dr. Phil Garrou looks at 3D IC technology discussions at IEDM 2010, including details of TSMC's integration of 3D into its advanced CMOS foundry processes, and a close examination of 3D-induced stresses.


Cohu-names-prez-of-Semiconductor-Equipment-Group

Wed, 12 Dec 2010

Cohu Inc. (NASDAQ:COHU) appointed Luis A. Müller president of its newly formed Semiconductor Equipment Group, which encompasses Cohu subsidiaries Delta Design and Rasco GmbH.


RoodMicrotec-adds-almost-EUR2m-capital

Wed, 12 Dec 2010

RoodMicrotec N.V. has successfully secured mezzanine capital of € 1.994 million without repayment obligation, providing a long-term strengthening of the company’s equity position.


Silbond semiconductor chemical supplier acquired by investment firm

Tue, 12 Dec 2010

O2 Investment Partners, LLC, announced it has acquired all outstanding shares of Silbond Corporation, a specialty chemical manufacturing business based in Weston in southeastern Michigan.


Terepac-expands-to-Silicon-Valley

Mon, 12 Dec 2010

Terepac Corporation has been accepted into the Plug and Play Tech Center in Sunnyvale, California, an incubator in the heart of Silicon Valley. Terepac’s footprint in Silicon Valley is the company’s first presence in the United States.


SemiSouth-sends-SiC-die-to-Micross-for-hermetic-packaging-aimed-at-mil-aero-drilling-apps

Tue, 12 Dec 2010

Micross Components, Inc. and SemiSouth Laboratories, Inc. announced a collaborative effort to expand SemiSouth's line of Silicon Carbide (SiC) Power JFETs and Schottky Diodes. SemiSouth will provide select JFET and diode die to Micross for packaging and test in metal hermetic packages


Foundry-orders-Nanometrics-TSV-metrology-system

Fri, 12 Dec 2010

Nanometrics Incorporated (Nasdaq: NANO) announced that a leading semiconductor foundry has ordered a UniFire 7900 metrology system for advanced 3D wafer-scale packaging process control.


DCG-sends-wafer-test-systems-to-CIMPACA

Thu, 12 Dec 2010

The Centre Intégré de Microélectronique Provence Alpes Côte d'Azur (CIMPACA) selected DCG Systems products for its characterization and failure analysis platform: the ELITE lock-in thermography system and the Meridian WaferScan emission microscopy wafer prober with LVx option.


FormFactor-FORM-makes-Board-of-Director-changes

Tue, 12 Dec 2010

FormFactor Inc. (NASDAQ: FORM) announced that Executive Chairman Carl Everett was elected to serve as non-executive Chairman of the Board of Directors. Current lead independent director Jim Prestridge will remain on the Board. FORM also announced the resignations of Board members Homa Bahrami, Chenming Hu and Harvey Wagner.


DIOD releases first product in thermally enhanced PowerDI5060 package

Fri, 12 Dec 2010

Diodes Incorporated (Nasdaq: DIOD) released its first device in its unique PowerDI5060 package, the DMP3010LPS 30V rated p-channel enhancement mode MOSFET.


MEMS packaging facility lands Canadian grant

Thu, 12 Dec 2010

The MiQro Innovation Collaborative Centre (MICC; Bromont, QC, Canada) will receive a $14.1 million grant as part of the Canadian government's Centres of Excellence for Commercialization and Research (CECR) program. The grant will be used for 200mm MEMS and WLP research.


Vishay Intertechnology enters into new $450 million credit facility

Thu, 12 Dec 2010

Vishay Intertechnology Inc. (NYSE: VSH) has entered into a new five-year $450 million credit facility. The senior secured facility, which matures on December 1, 2015, replaces VSH's prior $250 million revolving credit facility, which was scheduled to mature on April 20, 2012.


Alpha and Omega Semiconductor buys Agape Package Manufacturing

Wed, 12 Dec 2010

The consideration for the acquisition is approximately $38 million, comprising of approximately $17 million in cash and 1.8 million AOS's common shares. Prior to this acquisition, AOS held 43% equity stake in APM.


IMI to buy PSi technologies, adding SATS to EMS offering

Tue, 7 Jul 2010

Integrated Microelectronics Inc. (IMI), a leading electronics manufacturing service (EMS) provider to OEMs, announced an agreement to acquire 67% of PSi Technologies Inc. (PSi), an independent semiconductor assembly and test services (SATS) provider.


ROGERS teams RO4460 prepreg with RO4360 laminate for multilayer HF circuits

Tue, 7 Jul 2010

Rogers Corporation has developed a match for the RO4360 laminate: RO4460 prepreg. Both materials feature dielectric constant (Dk) of 6.15 ±0.15 and low dielectric loss of 0.003 at 2.5GHz. Together, they form an ideal system for fabricating compact, cost-sensitive multilayer high-frequency (HF) circuits in limited space.


Soft-pad silicone thermal management material from Shin-Etsu

Fri, 7 Jul 2010

Shin-Etsu Silicones of America Inc., U.S. subsidiary of Shin-Etsu Chemical Co. Ltd., Japan, launched the TC-CA Series, comprised of Shin-Etsu’s advanced polymer and thermally conductive filler composite material technologies. The low-hardness silicone soft pad series of products have both high thermal conductivity and excellent electrical insulation properties.


Henkel releases NCP for copper pillar interconnect

Mon, 7 Jul 2010

Henkel’s Hysol FP5201 NCP offers the underfill protection required for Cu Pillar technology, effectively mitigating the stress between the substrate and the die.


Leveraging 3D packaging technologies: Tessera shares its latest work

Fri, 7 Jul 2010

In this video interview, Craig Mitchell, Tessera, comments on 3D packaging and interconnect. The chip industry is using packaging technologies to address miniaturization and density. Materials are posing a challenge.


Video: Wafer level packaging data from Texas Instruments

Tue, 7 Jul 2010

In this video interview, Dave Stepniak, Texas Instruments, talks about a wafer-level packaging (WLP) trends paper he presented at SEMICON West. He summarizes the paper for senior technical editor Debra Vogler.


From SEMICON West: Reducing the cost of wafer-level packaging with Novellus

Thu, 7 Jul 2010

WLP has always faced cost challenges on the mass-market sectors, like consumer devices. WLP can reduce power consumption and package size. Novellus introduced several products at SEMICON West to increase deposition and removal productivity and advance the technology.


Embedded wafer-level packages: Fan-out WLP/chip embedding in substrate 2010 report

Tue, 7 Jul 2010

This report from Research and Markets covers new and established technologies for embedded package integration. Benefits of embedded package integration include miniaturization, improvement of electrical and thermal performance, cost reduction and simplification of logistic for OEMs.  


Advanced packaging technologies: Imbedding components for increased reliability

Tue, 4 Apr 2010

Imbedded component/die technology is a method of imbedding active and passives into cavities within a multi-layer PCB to decrease the surface area required to implement the circuit design and increase the robustness of the overall assembly. Casey H. Cooper, STI, discusses the design methodology, packaging processes, and test data gathered during imbedded die/component packaging implementation in a mixed-signal prototype. The prototype was subjected to reliability testing and demonstrated in a test flight.


SATS providers join top 20, says Gartner

Fri, 9 Sep 2010

Gartner VP of semiconductor manufacturing research, Jim Walker, notes that, for the first time, 2 SATS companies joined the top 20 capital spenders in 2010. He also predicts solid growth for advanced packaging tooling with memory ATE and copper wire bonders being the top performers. Walker says the conversion to copper wire from gold is a wise move.


Flip chip bonding, printed electronics, no-litho subjects of IeMRC Conference

Thu, 9 Sep 2010

The 5th annual IeMRC Conference, September 21 in Loughborough, UK, will include 4 sessions: Advanced packaging, Materials processing and assembly, Printed electronics, and EPSRC.


KGD Packaging and Test Workshop keynote, panel on TSV, and more

Wed, 9 Sep 2010

KGD (Known Good Die) Packaging and Test Workshop 2010 will focus on semiconductor die products test, assembly, manufacturing, and business issues in the microelectronics industry. Bill Bottoms will keynote, covering deep submicron and 3D integration.


Reinforced thermal interface material integrates nylon mesh layer

Fri, 9 Sep 2010

Fujipoly released Sarcon 100GR-FL, a low resistance, durable thermal interface gap filler pad. The gel-like material is manufactured with an integrated nylon mesh layer that prevents distortion and stretching during die-cut operations.


Thermal gap filler provides electrical isolation with high tolerance stack-up

Tue, 9 Sep 2010

Laird Technologies released the Tflex XS400 Series thermal gap filler, a compliant elastomer gap filler for moderate thermal performance with a thermal conductivity of 2.0W/mK. This soft interface pad conforms with minimal pressure, resulting in minimal thermal resistance even at low pressure with little or no stress on mating parts.


Semiconductor packaging substrates future wiring density needs: Join the discussion

Thu, 9 Sep 2010

Meeting these future needs will require radical improvements and innovations in all aspects of organic packaging substrate technology. A pre-competitive iNEMI R&D project plan, currently under development, will identify approaches capable of meeting wiring density needs for future generations of organic semiconductor packaging substrates. Meeting these future needs will require radical improvements and innovations in all aspects of organic packaging substrate technology.


Picotest Signal Injectors improve regulator, power supply test accuracy

Mon, 9 Sep 2010

Picotest released a new family of Signal Injectors, or adapters, to improve voltage regulator, LDO, and power supply testing accuracy. Increased bandwidth and higher resolution measurements are enabled for PSRR, stability, crosstalk, reverse transfer, input impedance, Bode plots, and crosstalk tests along with non-invasive in-circuit testing (ICT) for load transients, stability and output impedance. Picotest released a new family of Signal Injectors, or adapters, to improve voltage regulator, LDO, and power supply testing accuracy. Increased bandwidth and higher resolution measurements are enabled for PSRR, stability, crosstalk, reverse transfer, input impedance, Bode plots, and crosstalk tests along with non-invasive ICT for load transients, stability and output impedance.


Next-gen bond tester software launch from Nordson DAGE

Tue, 9 Sep 2010

Nordson DAGE, a subsidiary of Nordson Corporation (NASDAQ: NDSN) and provider of bond testing technology, introduced Paragon intelligent bond testing software for semiconductor packaging.


GaAs test services debut from WIN Semiconductors, Presto Engineering

Wed, 9 Sep 2010

Users of WIN's GaAs foundry services can engage in wafer-level and package test in Silicon Valley, CA, and Grenoble, France.


Advanced packaging industry today: TSV weak vs FOWLCSP, package-to-PCB assembly a concern for small pitch packages, and more analysis

Thu, 9 Sep 2010

Research in China put out this new report chronicling the advanced semiconductor packaging industry happenings and key companies from 2009 to 2010. The study mainly focuses on CSP and BGA packaging. Technology adoption and costs are analyzed, from eWLB to TSV. Packaging tech usage examples are included here, along with assessments of tech adoption and industry player rankings.


LCP QFN packaging tech supports finer pitch, thinner leadframes

Thu, 9 Sep 2010

LCP based QFN semiconductor packages.RJR Polymers debuted a new-generation LCP quad flat-pack no-lead (QFN), air-cavity package that will support finer lead pitches, thinner leadframes and shorter wire bond lengths in a near hermetic, ROHS-compliant solution.


Tessera-opens-Seoul-Korea-office

Mon, 11 Nov 2010

Tessera Technologies Inc. (Nasdaq:TSRA) opened a new office in Seoul to support Tessera’s regional activities with OEMs and industry partners in the growing cell phone market.


Dow-Electronic-Materials-opening-TMG-facility-in-Korea

Fri, 11 Nov 2010

Dow Electronic Materials has broken ground for a new metalorganic precursor manufacturing plant in Cheonan, Korea. Dow is expanding TrimethylGallium (TMG) production capacity to meet the surging global demand for the material in the LED and related electronics markets.


Smart textile large-area manufacturability at heart of PASTA project

Wed, 11 Nov 2010

imec PASTA smart textile project aimsBare die in yarn, comfortable electronics, stretchable interposers, washable photovoltaic clothes, and other elements will be on the table for the PASTA project to bring smart textiles from the lab to industrial manufacturability. Imec leads the program.


IBM-fine-pitch-substrate-bumping-skips-solder-paste-beyond-C4NP

Tue, 11 Nov 2010

IBM IMS process for substrate bumpingJae-Woong Nah, researcher at IBM's Thomas J. Watson Research Center, briefed ElectroIQ on his IMAPS conference paper: "Mask and mask-less injection molded solder (IMS) technology for fine-pitch substrate bumping." IMS is a variation of C4NP for solder deposition on fine-pitch laminates. Nah explains how the researchers injected 100% pure molten solder instead of solder paste with a reusable film mask for forming high-volume solder on fine-pitch substrates.


Kulicke-Soffa-pushes-copper-wire-bonding-transition with IConnPS ProCu

Tue, 11 Nov 2010

Kulicke & Soffa Industries Inc. (Nasdaq: KLIC) introduced the IConnPS ProCu wire bonder optimized for copper wire bonding. The K&S IConnPS ProCu offers a significant and new level of capability for packaging lines transitioning from gold to copper wire bonding.


Copper-based-ink-printed-electronics enables screen-print process

Mon, 11 Nov 2010

NovaCentrix announced that Metalon ICI-020, a new copper-based screen ink, will be featured at Printed Electronics USA 2010 in Santa Clara, CA, November 30-December 2, 2010. Pre-printed samples of Metalon ICI-020 screen ink on card stock will be distributed with the registration packs by IDTechEx staff, and attendees may bring their samples to the NovaCentrix exhibit area to cure the ink with NovaCentrix’s PulseForge process tool.


New EI LCP laminates meet harsh environment SiP reqs

Tue, 11 Nov 2010

EI added LCP Laminates to its family of microelectronics packaging product offerings. Custom-designed LCP Laminates are suitable for semiconductor packages as LCP coreless designs for up to 6 layers as well as in combination with other rigid materials as hybrid circuits. Development and testing of Z-interconnect cross-sections for >8 layer offerings are also underway.  


GE-intros-CT-system-for-3D-metrology-and-analysis

Mon, 11 Nov 2010

tsv ctThe phoenix nanotom m, from GE´s Inspection Technologies business, has been developed for high resolution and high precision X-ray computed tomography (CT) in non-destructive 3D analysis and 3D metrology.


LTX-Credence-adds-low-cost-analog-tester-ASLx

Thu, 11 Nov 2010

LTX-Credence (LTXC) introduced the ASLx, a new test system extending the capabilities of the ASL low-cost analog and mixed-signal test platform. ASLx provides 4x the analog and digital pin count and 5x the power capability of the ASL1000.


Flip-chip-wafer-level-packaging-WLP-IMAPS-2010

Wed, 11 Nov 2010

Silicon interposer for advanced packaging (Source: RTI)Alan Huffman, research engineer and program manager at RTI International, presented a paper at IMAPS 2010 titled "On the origins, status, and future of flip-chip and wafer-level packaging." In a podcast interview with Debra Vogler, senior technical editor, Huffman discusses the advantages and disadvantages of flip-chip and wafer-level packaging (WLP), along with potential solutions.


IDTechEx launches active RFID and sensor networks report

Mon, 8 Aug 2010

The IDTechEx report, "Active RFID and Sensor Networks 2011-2021," comprehensively analyzes the technologies, players and markets with detailed 10-year forecasts, including tag numbers, unit prices and interrogator numbers and prices.


SMTA announces IWLPC featured tutorials

Thu, 8 Aug 2010

Tutorials at the October event will cover 3D packaging, future interconnects, WLP, flip chip, and more.


STATS ChipPAC announces pricing of new senior notes

Thu, 8 Aug 2010

The senior notes consist of $600.0 million of 7.5% Senior Notes due 2015. The Private Placement is expected to close on Thursday, August 12, 2010.


UNISEM records 40% jump in Q2 revenue from 2009

Mon, 8 Aug 2010

Semiconductor packaging and test provider Unisem (M) Berhad announced results for the second quarter, ended 30 June 2010 (2Q10).


Assembleon intros back-end package assembly robot

Thu, 8 Aug 2010

Assembleon intros back-end package assembly robotAssembléon’s recently released Twin Placement Robot (TPR) will reportedly reduce costs for semiconductor backend manufacturing. The TPR fits on Assembléon’s A-Series pick & place equipment for packaging and IC placement. Plans are in the works for the TPR to do semiconductor manufacturing tasks as well.


Wire-bonding/AOI, chip mounting areas linked: Case study from IPTE

Tue, 8 Aug 2010

Continental Corporation applied economic conveyor and handling modules from IPTE’s EasyLine product portfolio to link its gold and aluminum wire bonding, mounting, and AOI areas. Continental Corporation applied economic conveyor and handling modules from IPTE’s EasyLine product portfolio to link its gold and aluminum wire bonding, mounting, and AOI areas.


Market research: Thermal interface materials and fillers

Mon, 8 Aug 2010

Japan Marketing Survey Co. Ltd. (JMS) will publish "Outlook of thermal interface material market 2010) this week, with data on the semiconductor package thermal management market size by application, thermal interface material types' market shares, and more.


Dielectric materials evolve to meet the challenges of wafer-level packaging

Mon, 11 Nov 2010
New polymers that are capable of buffering die structures from the package stresses will be required of advanced packaging; and materials will continue to evolve to meet the new requirements. Toshiaki Itabashi, DuPont Semiconductor Fabrication Materials, Kanagawa, Japan

PoP rework: Process control and using the right materials increases yield

Mon, 9 Sep 2010

POP after package rework.PoP packages present some unique rework challenges, such as how to rework an underfilled package; also, these packages are prone to warpage. Inspecting the area array devices can be a challenge. Bob Wettermann, BEST Inc., discusses rework solutions.


Microelectronics partnership for Harris, EI

Wed, 9 Sep 2010

Endicott Interconnect Technologies Inc. (EI) entered into a strategic partnership agreement with Harris Corporation to jointly develop innovative microelectronic solutions and collaborative services for new products serving key markets and customers. 


IWLPC speaker Mackie will cover low-alpha assembly materials for wafer-level packaging

Tue, 9 Sep 2010

Indium Corporation’s global product manager, Andy C. Mackie, Ph. D., MSc, is presenting at the International Wafer-Level Packaging Conference (IWLPC) October 11-14, 2010 in Santa Clara, CA.


SEMICON Europa plans dedicated semiconductor packaging and test track

Fri, 9 Sep 2010

The advanced packaging and test track of SEMICON Europa will deal with the industry shift away from high-lead solders, digital test and testing integrated analog/mixed-signal packages, package design in the electronics design workflow, and LEDs, among other topics.


IMAPS International Symposium on Microelectronics: Reasons to attend

Thu, 9 Sep 2010

3D Semiconductor Integration, Next Generation Materials, Photovoltaics, Advanced Assembly & Packaging to be Highlighted at IMAPS 2010 International Microelectronics Conference.


Fujitsu renews packaging license with Tessera on original terms

Wed, 9 Sep 2010

Under the agreement, Fujitsu is licensed to Tessera's semiconductor packaging technology covering a broad range of chipscale and multi-chip package types.


Conflict minerals and the electronics supply chain: Where we stand now and what the future holds

Tue, 9 Sep 2010

New requirements are coming on-line for manufacturers of products containing tin (Sn), tantalum (Ta), gold (Au), tungsten (W), or any other “conflict metals.” If the electronics industry thinks that the SEC regulations will only impact publicly traded companies, they need to think again.


Proteus Biomed chooses IC test house Integra for new designs

Mon, 9 Sep 2010

Integra Technologies, IC test and evaluation services provider, was selected by Proteus Biomedical for development and production test of their new integrated circuit (IC) designs for future medical electronics products.


KaiSemi FPGA-to-ASIC chip conversion service

Fri, 9 Sep 2010

An in-house tool allows KaiSemi to perform automated FPGA-to-ASIC conversion, creating fully compatible replacement chips.


STATS ChipPAC opens 300mm embedded WLP BGA (eWLB) manufacturing fab

Wed, 9 Sep 2010

STATS ChipPAC Ltd. opened a new 300mm embedded Wafer-Level Ball Grid Array (eWLB) manufacturing facility, switching over from 200mm technology. The official inauguration was held at STATS ChipPAC's Yishun facility in Singapore with more than 150 local dignitaries, customer representatives, business partners and management participating.


Freescale licenses RCP to Nepes, brings redistributed chip packaging to 300mm in Singapore

Mon, 9 Sep 2010

Freescale will license its redistributed chip packaging technology to Nepes, Korean semiconductor parts and materials specialist. Nepes and Freescale will also collaborate on RCP development.


DEK-VectorGuard-3D-stencils-for-chip-on-board

Fri, 12 Dec 2010

DEK stencil for chip on boardVectorGuard 3D stencils are designed for specialist applications requiring multiple level printing. Facilitating printing on different levels with upward or downward steps, VectorGuard 3D enables a uniform stencil thickness.


MicroProbe direct-dock extended to ADvantest T2000 SoC test

Wed, 12 Dec 2010

MicroProbe, wafer test technology supplier, is extending its direct-dock offering to support Advantest's T2000 SoC test platform. The T2000 platform-compatible option enables test coverage at wafer sort. More than 100 direct-dock probe cards are already in the field.


Focus on 3D TEST at IEEE Workshop

Wed, 12 Dec 2010

The test community is embracing 3D ICs, as evidenced by presentations at the first IEEE International Workshop on Testing 3D stacked ICs that addressed a range of test challenges and solutions, reports Dr. Phil Garrou.


Flip-chip-wafer-level-packaging-see-double-digit-CAGR-says-TechSearch-International

Wed, 12 Dec 2010

TechSearch International’s new study, "2010 Flip Chip and WLP: Market Projections and New Developments," projects a CAGR of more than 15% for flip chip units. In unit volumes, WLPs are expected to see a 12.48% CAGR from 2009 to 2014. The report profiles drivers for the demand for gold and solder bumping, as well as WLP.


Amkor-3-generations-of-3D-packaging

Mon, 11 Nov 2010

In this podcast interview, Smith discusses the three generations in the transition to 3D packaging and how the OSATs shape the development roadmap. Smith says that we need complete supply chain collaboration: EDA tool suppliers, equipment/materials suppliers, logic, memory, fabless, IDMs, and the SATs, to develop and deploy the technologies.


Flip chip PoP is perfect for mobile, if done right

Wed, 11 Nov 2010

Craig Mitchell, TesseraPackage-on-package, implemented with flip chip package assembly, is meeting requirements for next-gen mobile devices. Challenges remain: fine pitch underfill, brittleness of ultra low-k (ULK) dielectrics, and shorting between adjacent bumps. Craig Mitchell, Tessera, examines the lucrative 3D packaging step and how to face these challenges.


Package-on-package-POP-survey-Stack-packages-at-SATS

Mon, 11 Nov 2010

Advanced Packaging asked our readers where -- at the foundry, in a dedicated semiconductor assembly and test services (SATS) house, or on the SMT line -- package-on-package (POP) assembly should take place.


Rudolph-Asia-OSAT-collab-on-2D-defect-inspection-3D-solder-bump-TSV-depth-metrology-for-stacked-die

Tue, 11 Nov 2010

Rudolph’s NSX Series Macro Defect Inspection Systems Rudolph Technologies Inc. (RTEC) is partnering with a major outsourced semiconductor assembly and test (OSAT) services manufacturer to provide its inspection and metrology capability in the development of stacked packaging processes. The process uses silicon interposer technology, sometimes referred to as 2.5D IC, as an intermediate step toward full blown 3D ICs.


Fujitsu-transfers-flip-chip-to-China

Mon, 11 Nov 2010

Japan's Fujitsu Semiconductor Ltd. will transfer its flip chip mounting technology to a Chinese group affiliate for system chip assembly.


Mattson-wins-etch-order-for-WLP-facility

Tue, 11 Nov 2010

Mattson Technology Inc. (NASDAQ: MTSN) received a repeat order for the Alpine etch system from a leading semiconductor manufacturer. The system will be used in the customer's leading-edge 300mm packaging facility in Asia for advanced wafer-level packaging processes.


MEPTEC-Packaging-Roadmaps attendee wants more collaboration and partnerships

Thu, 11 Nov 2010

Senior technical editor Debra Vogler asked Tarun Verma, senior director, packaging engineering at Altera, to comment on the MEPTEC Semiconductor Packaging Roadmaps conference, which took place recently in Santa Clara, CA.


IC-packaging-and-substrates report looks at type, volume

Mon, 11 Nov 2010

Japan Marketing Survey Co. Ltd. (JMS) published the report "IC Packaging & Substrate Report 2010." It covers production trends of major semiconductor package assemblers and substrate makers and the package market size through 2014, based on package type and electronics volume.


Tessera and Nanium, formerly Qimonda Portugal, sign packaging technology licensing agreement for DRAM and other semiconductor devices

Fri, 2 Feb 2010

Tessera Technologies Inc. (Nasdaq:TSRA) semiconductor packaging subsidiary, Tessera Inc., signed a technology licensing agreement with Nanium S.A. Nanium, formerly known as Qimonda Portugal, previously was the largest semiconductor packaging assembly and test operation within Qimonda. Nanium has now reorganized as an independent company and will focus on providing assembly and test services for the DRAM memory market and other semiconductor products. Products manufactured by Nanium will be incorporated into computers, servers and various electronic devices such as MP3 players, mobile phones, cameras, and game consoles. The initial term of the license agreement runs through the end of 2017.


Reverse costing analysis of the Infineon X-GOLD 213-eWLB fan-out wafer-level package

Wed, 2 Feb 2010

System Plus Consulting released its new reverse costing analysis of the enhanced Wafer Level BGA (eWLB) packaging used in the X-GOLD 213 circuit from Infineon. eWLB is a ball grid array (BGA) package based on the emerging fan-out wafer-level package (FO-WLP) concept. All the packaging operations are done at the wafer level, and a fan-out area is provided to extend the package size beyond the IC surface area to allow for higher ball counts. The ball pitch is 0.5mm and only one redistribution layer is used for this 217 balls, 8 × 8mm package.


Hymite will sell portfolio of wafer-level semiconductor packaging patents

Mon, 2 Feb 2010

ICAP Ocean Tomo, the intellectual property brokerage division of ICAP Plc (IAP.L), is offering for sale a patent portfolio relating to wafer-level semiconductor packaging owned by Hymite A/S. The 77 issued U.S. and foreign patents and patent applications cover new packaging technologies for optical communications components, LED emitters, and semiconductor fabrication.


Burn-in and Test Socket (BiTS) Workshop Preview

Fri, 2 Feb 2010

The Burn-in & Test Socket (BiTS) Workshop will take place March 7–10, 2010 at the Hilton Phoenix East/Mesa Hotel in Mesa, AZ. More than 30 papers and posters will be presented; participants include end users and suppliers of sockets, boards, burn-in systems, handlers, and packages; and other related equipment, materials, and services. The TechTalk session on PCB design, fabrication and assembly is booked full, as is the tutorial on RF socket characterization by Gert Hohenwarter, Ph.D. of Gatewave Northern Inc. Here are some of the show highlights.


World Gold Council, SEMI survey packaging industry on wire bonding material choices

Tue, 1 Jan 2010

On behalf of the World Gold Council (WGC), SEMI conducted a survey titled “Semiconductor Industry Opinions Concerning the Selection of Bonding Wire Material.” The survey was intended to gauge the semiconductor industry’s use of copper bonding wire versus gold for packaging applications. The WGC is a commercially driven organization focused on creating demand for gold. While 41% of semiconductor companies surveyed use copper bonding wire, none use it in the majority of their products. However, the majority of respondents will consider copper bonding wire in their new products.


TSV: Current challenges and solutions with Novellus

Fri, 8 Aug 2010

In this video interview, Sesha Varadarajan, Novellus, says that capacitance issues must be overcome, and the PVD step must provide good enough coverage to properly apply copper. CTE mismatch can also cause issues.


Si, glass interposers for 3D packaging: analysts' takes

Tue, 8 Aug 2010

Silicon interposers for advanced packaging Yole reportYole asks if next-generation package substrates are myth, niche, or high-volume necessity? Several companies are investigating silicon interposers and there is great interest in the topic, but there is no clear consensus on apps and timing for adoption, says TSI in its forecast for Si interposers. Both analyst forecasts are summarized.


Look for TSV to take off in 2012: Jan Vardaman

Tue, 8 Aug 2010

In this video interview from SEMICON West 2010, Jan Vardaman, president/founder of TechSearch International, discusses 3D technologies in the real engineering world. Especially for 300mm, work is being done on processes and yield. She points to 2012 for widespread adoption of TSV.


Achieving cost and performance goals using 3D semiconductor packaging

Sun, 8 Aug 2010
It has been proven that SoC and 3D multiple die packaging can significantly improve performance and the function-to-area ratio, however, one must look at the tradeoffs. Vern Solberg, STC-Madison, Madison, WI USA

Fraunhofer's Ramm will open International Wafer-Level Packaging Conference

Tue, 8 Aug 2010

Peter Ramm, Fraunhofer EMFT, will be the Opening Speaker at the 7th Annual International Wafer-Level Packaging Conference (IWLPC). Ramm will present "The European 3D Technology Platform for Heterogeneous Systems" at the Kick-Off Reception.


QFN chip packaging expansion at Carsem

Mon, 8 Aug 2010

Carsem is aggressively expanding its MLP/QFN package manufacturing capacity in Ipoh, Malaysia and Suzhou, China factory locations. This capacity expansion in assembly is matched with an equal proportion of test capacity expansion.


Murata nibbles RFMI stocks, signs collaboration agreement

Thu, 8 Aug 2010

Murata purchased 533,000 shares of RF Monolithics Inc. (RFMI) common stock at a small premium over RFM’s recent 30 day volume weighted average price, in a private transaction. RFM and Murata Manufacturing Co. Ltd. have entered into a collaboration agreement.


DSP on FPGA workshops planned by Avnet, MathWorks, TI

Wed, 8 Aug 2010

The series of workshops focuses on digital signal processing (DSP) system design using Xilinx FPGAs with high-speed data converters. These workshops are being offered to design engineers in North America.


Combination chipset shipments will near 280M in 2010, says ABI Research

Tue, 8 Aug 2010

Shipments of “combo” chipsets for mobile devices that gather a variety of connectivity types in one small package are expected to approach 280 million worldwide by the end of 2010. Integrating different radio technologies such as FM, Bluetooth, Wi-Fi and GPS on a single chip may sometimes involve performance compromises, but saves money, space and power.


Gyroscope integrates MEMS/ASIC in custom package

Mon, 8 Aug 2010

Sensonor Technologies is developing SAR500, a novel high-precision, low-noise, high-stability, calibrated and compensated digital oscillatory gyroscope with SPI interface housed in a custom-made ceramic package.


SiliconBlue highest logic capacity FPGA in 6x6mm package

Mon, 8 Aug 2010

SiliconBlue Technologies, provider of custom mobile devices for consumer handset applications, debuted two device packages for its iCE65 mobileFPGA family. The iCE65L01 FPGA device with 1,280 logic cells is now offered in a 5x5 mm, 81-ball BGA package with 63 user I/O pins, and the iCE65P04 device with 3,520 logic cells is now offered in a 6x6 mm, 121-ball BGA package with 95 user I/O pins.


Roadmapping More than Moore: When the application matters

Fri, 7 Jul 2012

At the ITRS 2012 update, back-end technologies session, at SEMICON West, roadmapping for More than Moore was addressed as both a philosophical and technical matter.


ULIS invests EUR20M in advanced IR imaging sensor fab and packaging

Tue, 7 Jul 2012

ULIS invested EUR20 million in a new state-of-the-art facility to meet increasing market demands for IR technology, with a move to 200mm wafers and pixel/wafer-level packaging techniques.


Ultratech named advanced packaging tool supplier of choice by top-tier packaging houses

Tue, 7 Jul 2012

Ultratech formed 'exclusive supplier' and 'preferred tool vendor' agreements with several top-tier advanced packaging companies around the world.


STATS ChipPAC ramps advanced flip chips to HVM, adds TCB processing capability

Tue, 7 Jul 2012

STATS ChipPAC brought its fcCuBE advanced flip chip semiconductor packaging technology with copper column bumps, bond-on-lead interconnection, and enhanced assembly processes into high-volume manufacturing for multiple customers.


Tessera: Adding Vista Point Technologies, losing Powertech Technology?

Mon, 7 Jul 2012

Tessera received notice from Powertech Technology Inc. (PTI) that it will terminate its license agreement with the semiconductor packaging and optics technology company. Tessera also completed phase 1 of its acquisition of camera module technologies from Flextronics.


Unisem focuses new business model on Tier-1 customers and high-value technologies

Fri, 6 Jun 2012

UNISEM relaunched its business model with the name

Ultratech acquires IBM patents for semiconductor packaging processes

Fri, 6 Jun 2012

Ultratech acquired IBM patents on semiconductor packaging technologies, including C4 bumping, ball grid array (BGA) methods, lead-free solders, and 3D packaging.


DARPA seeks microfluidic thermal management for 3D ICs

Mon, 6 Jun 2012

DARPA

ECTC

Fri, 6 Jun 2012

Attendance was high at this year's Electronic Component Technology Conference (ECTC) in San Diego. Sandra Winkler is senior industry analyst at New Venture Research and IEEE/CPMT Luncheon Program Chair, shares the key trends in ECTC's sessions, like WLP, 2.5D, LED packaging, and more.


StratEdge improves thermal management in power semiconductors with LL packages

Wed, 6 Jun 2012

The LL leaded laminate copper-moly-copper base packages dissipates heat from high-power compound semiconductor devices, such as gallium nitride, gallium arsenide, and silicon carbide chips.


Rockwell Automation helps scale Terepac circuits miniaturization method

Tue, 6 Jun 2012

Terepac Corp. will produce high volumes of its proprietary micro circuits for Rockwell Automation, supporting the "Internet of Things" with RFID tags. Rockwell Automation will support the infrastructure that Terepac uses, enabling it to miniaturize significantly more circuits than its current capability.


ams offers foundry customers KGD with enhanced IC test

Mon, 6 Jun 2012

The Full Service Foundry business unit of ams extended its dedicated test solutions for foundry customers, offering known good die (KGD), with customers' complex analog/mixed-signal ICs 100% electrically tested according to their own test specification.


Conference report: IITC closes with talks from EUV to TSV

Thu, 6 Jun 2012

Day 3 of the 15th IITC (International Interconnect Technology Conference) opened in San Jose, CA under clear sunny skies and a pleasant breeze. The herd thinned a bit, down to ~150 hearty souls from the original 230 the prior two days.


Inari IPO debuts on Bursa Malaysia, new packaging facility planned

Thu, 7 Jul 2011

OSAT Inari Berhad was listed on the Bursa Malaysia, Stock Code: 0166, in an IPO that will partly be used to fund a new packaging and test facility.


Henkel develops die attach film for leadframe packages

Wed, 7 Jul 2011

Henkel worked with STMicroelectronics (STM) to qualify Henkel's Ablestik C100 conductive die attach film materials for scalable, adaptable leadframe packaging.


TSV moves to "real engineering," but reliability data needed

Mon, 7 Jul 2011

Jan Vardaman, president and founder of TechSearch International, summarizes highlights from her SEMICON West presentation on TSVs, speaking to RDL development, LED packaging, and TSV-alternative PoP.


Robotic die bonder upgrades SET packaging platform

Fri, 7 Jul 2011

The FC300R performs chip-to-substrate bonding, chip-to-wafer assembly, and chip-to-chip stacking for flip chip, through silicon via (TSV), and other advanced packaging processes, with a robotic handling system for fragile and diverse substrates/wafers.


WACKER makes semiconductor-bound silicone elastomers under cleanroom reqs

Tue, 7 Jul 2011

WACKER began operating several silicone-polymer production lines at its Burghausen, Germany, site, expanding production of high-purity specialty silicones, encapsulation and coating compounds, as well as UV-activated silicones.


Crystal oscillator adhesives debut from Creative Materials

Fri, 7 Jul 2011

Creative Materials now manufactures electrically conductive and electrically insulating adhesives for quartz oscillator circuits, used for bonding leads and lids. The low-stress adhesives feature good thermal stability with low out-gassing.


ASE forecasts IC inventory adjustments, maintains capex budget

Thu, 6 Jun 2011

Advanced Semiconductor Engineering Inc. (ASE, TAIEX:2311) predicts that the global IC sector will face inventory adjustments in the near term. ASE will maintain its capital expenditure plan through the correction period.


Korean IDM orders NEXX tools for WLP metallization

Tue, 6 Jun 2011

NEXX Systems installed 2 300mm Stratus deposition at a Korean IDM for high-volume wafer-level packaging processes.


Microsemi packages military DDR3 SDRAM in PBGA

Tue, 6 Jun 2011

The compact package suits mission-critical applications requiring up to 4GByte memory densities in smaller, faster packages with extended-temperature ranges.


Endicott Interconnect update: Defense electronics contracts

Mon, 6 Jun 2011

Endicott Interconnect Technologies released an update on its defense electronics development and production and sustainment contracts, which totalled $101 million.


Advanced packaging programs at SEMICON West emphasize holistic approach

Fri, 6 Jun 2011

SEMICON West preview: This year's SEMICON West Advanced Packaging Program is taking a broad approach, encouraging participation from across the supply chain to help keep pace with a rapidly expanding electronics market -- and in markets beyond, from automotive to aerospace and medical.


Microsemi names Carsem supplier of the year

Wed, 6 Jun 2011

Carsem received Microsemi Corporation's Best Supplier of The Year Award, for assembly and test services that were provided by the Carsem factory located in Suzhou, China.


JEDEC revises package inspection standard JESD9B

Tue, 6 Jun 2011

The JEDEC Solid State Technology Association published a significant revision to JESD9B, Inspection Criteria for Microelectronic Packages and Covers.


Technic Pd/Ni process eliminates free ammonia in leadframe fab

Mon, 6 Jun 2011

Technic Inc. debuted Pallaspeed Pd/Ni NFA, a production-proven sulfate palladium nickel process that produces low-stress ductile deposits over a wide current density range, for structures like semiconductor package leadframes.


NXP-intros-leadless-package-tin-plated-solderable-side-pads

Fri, 10 Oct 2010

The NXP SOD882D package has two tin-plated, solderable bottom pads that are exposed and are also Sn-plated on the sides.NXP SOD882D enables easy visual inspection of solder pads. SOD882D is an ultra small and flat package built for space constrained and robust devices. The new package pad designs were developed out of NXP's discrete leadless packaging technologies.


Advanced IC packaging report covers key techs, markets

Thu, 10 Oct 2010

New Venture Research, a technology market research company, released "Advanced IC Packaging Technologies and Markets, 2010 Edition," a strategic report on the latest technologies in IC packaging, with forecasts of key markets.


Vishay Siliconix Medical MOSFETs marks foray into implantable apps

Mon, 10 Oct 2010

Vishay Intertechnology Inc. (NYSE: VSH) released two devices in its first family of power MOSFETs built on an enhanced process flow with strict manufacturing process controls for implantable medical applications.


DEK develops fine-pitch isotropic conductive adhesive for infrared product maker

Thu, 10 Oct 2010

DEK develops fine-pitch isotropic conductive adhesive for infrared product makerDEK has teamed up with Irisys, infrared products supplier, to develop a robust fine-pitch isotropic conductive adhesive (ICA) interconnection process designed to drive Irisys’ latest generation of advanced infrared sensor products. The project led to the development of an optimized process for the assembly of pyroelectric thermal sensing arrays.


Sequans system-in-package WiMAX product targets portable products

Tue, 10 Oct 2010

4G chipmaker Sequans unveiled its latest Mobile WiMAX solution, the SQN1280, an all-in-one WiMAX system-in-package (SIP) for makers of handsets, tablets, USB sticks, portable hotspots, M2M modules, and a variety of consumer electronics devices.


IMI adds SATS PSi to gain power semiconductor share

Tue, 10 Oct 2010

The AYALA group’s electronics unit, listed Integrated Microelectronics Inc. (IMI), has completed its $30-million acquisition of PSi Technologies Inc.


austriamicrosystems extends beyond standard foundry offering into advanced packaging

Thu, 10 Oct 2010

austriamicrosystems Full Service Foundry introduced "More Than Silicon," a comprehensive service and technology package that goes beyond standard foundry services. Foundry customers receive access to leading-edge technology add-ons, advanced packaging services, and dedicated support engineers to enable first-time-right designs.


Paste print tool uses embedded electronics for finer pitches

Fri, 10 Oct 2010

DEK has launched ProActiv process technology to enable electronics manufacturers to print pastes with high-density heterogeneous PCBs and ultra fine pitch assemblies such as advanced package assembly. DEK has launched ProActiv process technology to enable electronics manufacturers to print pastes with high-density heterogeneous PCBs and ultra fine pitch assemblies such as advanced package assembly.


ECTC 2009 In Review

Mon, 6 Jun 2009
In a time when R&D is at the forefront of the industry, events like ECTC 2009 become critical for showcasing research achievements, as well as providing venues for learning about the latest developments across the spectrum of device manufacturing. With 16 professional courses, 39 sessions of 6 papers each, two poster sessions, and the opportunity to mix it up with prestigious members of academia and research institutes, calling the event informative would be an understatement.

The Riley Report

Tue, 5 May 2009
Flip Chips and Flashlights by George A. Riley, Contributing Editor
With the industry's attention riveted on the next-generation of TSV- enhanced stacked - everything 3D marvels, we sometimes forget how microelectronics are changing everyday products in our world.

Yole Report: Memory Packaging & Integration Trends

Fri, 5 May 2009
(May 8, 2009) LYON, France — The memory semiconductor industry is about to go through major technological changes as new integration trends and disruptive packaging technologies pave the way to the future growth, reports Yole. The study presents the end applications driving the use of 3D integrated memories and their key players. It also includes an overview of the memory packaging market, its forecasted evolutions with new applications and growth in flash and DRAM.

TI introduces ultra-thin ESD/EMI embeddable package

Thu, 5 May 2009
By Fran

Professor Rao Tummala to Present Keynote at 2009 International Wafer-Level Packaging Conference (IWLPC)

Fri, 5 May 2009
(May 29, 2009) MINNEAPOLIS, MN — Professor Rao Tummala, Advanced Packaging Editorial Advisory Board Member, will keynote the 6th Annual International Wafer-Level Packaging Conference (IWLPC), October 27–30, 2009 at the Santa Clara Marriott Hotel in Santa Clara, CA.

Simplicity Leads to 3D Packaging Success

Tue, 4 Apr 2009
By Francoise von Trapp, contributing editor
3D embedded technologies just got closer to volume manufacturing. We've been hearing variations on the embedding theme for quite some time, but as of yet, none have made it to high volume manufacturing. However, one embedded solution, Imbera's integrated module board (IMB) technolog appears to be on its way, after the company's announcement of successful Series B funding, which the company expects will take it into high-volume production.

Plasma Cleaning and Surface Modification for Microelectronics

Mon, 4 Apr 2009
By Gene Dunn, Panasonic Factory Solutions of America
Plasma technology offers a dry cleaning process that uses ionized gasses in vacuum chambers to remove contaminants for improved yields in gold bonding processes. Additionally, Auger electron spectroscopy (AES) is a useful analytical technique for determining the elemental surface characteristics and the effectiveness of plasma treatment to remove contaminants. This article discussed both.

Upcoming Boston Technical Events

Fri, 3 Mar 2009
(March 20, 2009) BOSTON — The SMTA Boston Chapter will cohost a technical presentation with IMAPS on April 21, preceding the opening of the SMTA Boston Academy, April 22-23. SMTA/IMAPS will present "Manufacturing & Reliability Challenges with QFN Packages in Pb and Pb-Free Environments." The Boston Academy will include seven courses on SMT, packages and components, PCBs, and lead-free and REACH.

New Method to Form Ultra-Thin Device Wafers

Tue, 8 Aug 2009
August 11, 2009

Commercializing a WLCSP passivation layer solution

Mon, 8 Aug 2009
Lord Corp. exec Russell Stapleton talks with SST about the company's first-generation passivation layer solution for wafer-level chipscale packaging, due to launch in 1Q10.

Conference on 3D Architectures for Semiconductor Integration and Packaging

Tue, 6 Jun 2009
(June 2, 2009) RESEARCH TRIANGLE PARK, NC — The 2009 3D Architectures for Semiconductor Integration and Packaging Conference and Exhibition will bring together industry leaders to examine the practical and competitive landscape on the path to implementation of 3D integration and packaging technologies, December 9 through 11, 2009, in Burlingame, CA.

NOR flash revenue set to grow in 2010 after downturn

Fri, 5 May 2010

Buoyed by improved demand and a brightening macroeconomic environment, NOR flash memory market revenue is projected to return to growth in 2010, according to iSuppli Corp. The climb will be modest: from $4.6 billion in 2009 to $4.8 billion in 2010.


Alchimer, KPM Tech Sign Agreement for TSV Wet Processing Tools & Materials

Mon, 2 Feb 2010

In a deal that will generate economical new process options for the 3D integration market, Alchimer S.A., a provider of nanometric deposition technology for semiconductor interconnects and through-silicon vias (TSV), and KPM Tech Co. Ltd., a manufacturer of plating materials and systems, announced a multi-level collaboration that gives KPM Tech exclusive rights to produce chemicals in Korea for Alchimer’s technology. The agreement also includes the manufacture of various configurations of wet processing tools to support the Alchimer TSV platform.


Power savings of embedded computing modules (ECMs) over FR-4 implementations

Thu, 12 Dec 2009

Silicon circuit board (SiCB) technology allows bare-die FPGAs, CPUs, and memory to be placed together on a single silicon substrate. Embedded computing modules using SiCB offer better performance than FR-4 material -- notably 22% reduced power consumption in a typical system, reports David Blaker from siXis Inc.


Advanced packaging materials conference scheduled for Cambridge University

Thu, 12 Dec 2009

The IMAPS-UK MicroTech-2010 and IEEE-CPMT Advanced Packaging Materials (APM), Feb. 28 to March 2 at Cambridge University, will be the major Spring 2010 event on electronics packaging, interconnection and integration conference in Europe.


Ultrathin, stackable QFN packages

Tue, 12 Dec 2009

Tom Adams from Sonoscan describes advances with "chip-in-polymer technology, developed at Germany's Fraunhofer IZM, which achieves 3D packaging advantages through better shock/vibration protection and shorter interconnect distances.


AMAT buys Semitool, deepens inroads into AP, Cu for memory

Tue, 11 Nov 2009

Execs from Applied Materials and Semitool discuss the motivations behind AMAT's $364M acquisition, to solidify and widen a presence in two key growth segments: advanced packaging and copper interconnects for memory.


IMAPS 2009: Fusion bonding for 3D/TSV, wafer-level/multichip packaging for MEMS

Mon, 11 Nov 2009

Presentations at this year's International Symposium on Microelectronics (IMAPS, San Jose, Nov. 1-5) included discussion of TSV/3D integration challenges and temporary bonding steps qualified for different process flows, and a wafer-level packaging (WLP) encapsulation process and stacked multi-chip package (MCP) for a MEMS variable capacitor and control IC chip.


Rudolph scores backend inspection biz from ASE

Fri, 10 Oct 2009

Taiwanese subcon ASE has ordered "multiple" tools for backend inspection from Rudolph Technologies, illustrating a trend to incorporate real-time process control into advanced backend fabrication processes.


Avoiding ASIC expense and risk with SiCB technology

Mon, 10 Oct 2009

Embedded computing modules employing "silicon circuit board" technology as an alternative to expensive ASIC developments offer advantages in performance and power for integrating memory and logic -- and are a practical alternative to 3D integration due to thermal and supply chain issues, explains siXis' David Blaker.


IMAPS GBC and Device Packaging Conference in Review

Tue, 3 Mar 2009
by Fran

Stenciling Platform

Tue, 3 Mar 2009
Micro-engineered to meet the challenges of fine-pitch printing, DEK's VectorGuard Platinum is an enabling stencil platform suited to advanced applications such as wafer level packaging (WLP), direct chip attach, flip chip and ball grid arrays (BGAs). The process is reportedly capable of delivering aperture accuracies of less than 3µm, and positional tolerances of better than 20µm at pitches down to 50µm.

Innovative Advanced Packaging Technologies Enable Leading-edge Wireless Products

Mon, 3 Mar 2009
By Manish Ranjan, Ultratech Inc.
Leading-edge consumer electronic products demand innovative silicon and packaging solutions. While front-end silicon technologies have progressed at a pace defined by Moore's Law, the back-end infrastructure has lagged in similar advancements. This has created an interconnect gap whereby the signal speed achieved on the silicon side is significantly higher than the speed achieved on the printed circuit boards.

Vertical-die-stacking-goes-3D-without-TSV

Thu, 10 Oct 2010

vertical die stack technologyAndrew Smith, Ventmark Technology Solutions, presents a 3D die stacking technology to address package miniaturization. Using bare die and vertical interconnect structures, this stacking technology permits the design of ultra-thin, near-CSP solutions without TSVs. Designers lacking custom ICs should look to new chip stacking technology.


3D architectures for semiconductor integration and packaging: Conference preview

Thu, 10 Oct 2010

The International Conference "3-D ARCHITECTURES FOR SEMICONDUCTOR INTEGRATION AND PACKAGING" will take place December 8-10, 2010 at the Hyatt Regency San Francisco Airport Hotel. Check out the planned keynotes and topics of the conference.


TI: Fast ramp at backend site to meet "steep demand"

Tue, 9 Sep 2009

SST/AP gets an update on Texas Instruments' progress ramping its new assembly/test facility in the Philippines -- which had been ramped far ahead of schedule in response to "unprecedented" demand.


Nemotek Technologie sizes up its future in wafer-level cameras

Tue, 9 Sep 2009
(September 1, 2009) MOROCCO — Jacky Perdrigeat, CEO of Nemotek Technologie, discusses the company's technology and business strategy, as it opens a new logistics center in Hong Kong with electronics component distributor Anglia.

HyperBGA Product Line

Thu, 8 Aug 2009
August 27, 2009 -- Endicott Interconnect Technologies (EI) announced improved capabilities of HyperBGA® PTFE-based "coreless" semiconductor package. Now packing more power and density with the addition of signal layers, HyperBGA® enables semiconductor devices to run at extremely high speeds.

Device bonding improved by new SET oxide removal chamber

Mon, 10 Oct 2010

SET unveiled a patented system enabling a thorough removal of oxides before or during the semiconductor packaging bonding sequence. SET unveiled a patented system enabling a thorough removal of oxides before or during the semiconductor packaging bonding sequence. Addressing the challenges of the oxidation of metal surfaces in device bonding, this machine system encompasses a substrate chuck and a bond head with a non-contact localized confinement chamber that operates safely with reducing gases such as forming gas or formic acid vapor.


SABIC Valox ENH resins launched for green FR PBT materials

Thu, 10 Oct 2010

SABIC Innovative Plastics launched three new sustainable additions to its Valox* ENH resin series that deliver advanced flame retardance (FR) with desirable mechanical and electrical performance. These innovative materials help customers comply with global environmental regulations.


EoPlex QFN packaging with thin green leadframe

Fri, 10 Oct 2010

EoPlex Inc. debuted a high-performance, clean-tech lead carrier for semiconductor packaging. EoPlex xLC is reportedly a cost-effective replacement for the leadframes currently used in quad flat pack no-lead (QFN) packages.


CT X-ray tube cooling system released by X-RAY WorX

Tue, 10 Oct 2010

Head of an X-RAY WorX tube of type XWT-225-SE with external cooling unit (black)X-RAY WorX presented its new concepts for the cooling of high resolution microfocus X-ray tubes. The company offers a new, modular cooling concept with an optimized internal cooling of the target inside the tube head.


Probe supplier Cascade Microtech targets lower costs and increased access

Mon, 10 Oct 2010

Cascade Microtech Inc. (NASDAQ: CSCD) announced new programs to drive down ownership costs and provide customers with increased access to experts in probe technology. The new programs involve direct sales channels and a repair program, among other efforts.


IC sockets business report released

Tue, 10 Oct 2010

Global Industry Analysts released a report analyzes the global market for IC sockets in US$ Million by dual in-line memory module sockets, production sockets, test/burn-in sockets, and others. Regional IC sockets markets are analyzed as a consolidated whole with no granular level breakup offered by product group/segment. Annual estimates and forecasts are provided for the period 2006 through 2015.


Highlights from the 2010 ECTC

Tue, 6 Jun 2010

At the Electronic Components & Technology  Conference (ECTC)  this month in Las Vegas the CPMT (Components, Packaging and Manufacturing Technology) Society of IEEE bought out their long time partners ECA (formerly EIA). Other news: STATSChipPAC expanded its presence in eWLB, copper-copper bonding in 3D was reviewed, and Doublecheck Semiconductors, working with Disco and the Fraunhoffer IZM claims to have developed technology that enables standard silicon wafers to be thinned down to less than 100µm.


A Novel ACA for 3D Chip Stacking and Lead-free PCB Packaging

Fri, 6 Jun 2010

In a SiP chip stack, space constraints can lead to large parasitic inductances in the packaging. Planarity, processing, high-temperature exposure, and other factors also present challenges. A new anisotropic conductive adhesive technology could enable low-cost flexible packaging via a multi-layer particle structure. S. Manian Ramkumar, Ph.D., RIT, reviews the adhesives benefits to various levels of electronics interconnect.


Aries Adds CSP Optical FA Test Sockets for EMMI or Optical Sensor Applications

Fri, 6 Jun 2010

Aries Electronics, manufacturer of interconnection products, now offers a CSP test socket with a window that optically exposes 100% of the top of the device under test (DUT) for failure analysis (FA) testing for emission microscopy (EMMI) or optical sensor applications.


Semiconductor packaging and electronics consortium formed for all-electric aircraft

Wed, 5 May 2010

The CREAM Project addresses the thematic “Aeronautics and Air Transport (AAT)” through the objective of developing an “Innovative Technological platform for Compact & Reliable Electronic integrated in Actuator and Motor” destined for several applications of the All Electric Aircraft such as fuel pumps, landing gear or brake actuators, flight control actuators, etc.


Harsh Environments in Advanced Packaging: Just the Beginning

Thu, 11 Nov 2007
Significant inroads to integrate surface-acoustic-wave- (SAW-) based electronics with sensors are producing more high-demand areas for packaging applications.

IN THE NEWS

Thu, 11 Nov 2007

BiTS and Pieces

Sun, 4 Apr 2007
The snow in New England was turning gray. Even skiing had lost its appeal.

Weathering the Storm Together

Thu, 1 Jan 2009
What were the most significant technological advancements in our industry in 2008?

Gone Fishing

Thu, 1 Jan 2009
I really like fly fishing. I’ve always wanted a fishing rod of my own, not one left over from an older brother’s stock of cast-offs, but a number 6 Orvis with just the right balance and flexibility for my style of trout fishing.

imec, PVA Tepla demo 3D TSV void detection

Thu, 1 Jan 2013

Imec and PVA Tepla say they have achieved void detection in through-silicon vias at wafer level, after TSV copper plating, thanks to a nondestructive high-frequency scanning acoustic microscopy (SAM) technique.


Novati to use Ziptronix bonding tech for 3D assembly

Fri, 1 Jan 2013

Novati Technologies Inc. has licensed Ziptronix's direct bonding technologies, "direct bond interconnect" (DBI) and "direct oxide bonding (ZiBond), to offer 3D stacking services and test to customers.


Comparing Package Bond Thermal Performance

Thu, 1 Jan 2009
Thermal Simulation Cuts Cost.

Practical Electronics 101

Thu, 3 Mar 2007
This issue of Advanced Packaging stands out for me because I had a chance to get to know more about practical issues that revolve around sockets.

Family Allowance

Wed, 11 Nov 2000
Donald balanced his family budget with difficulty. He called his three sons - Al, the eldest, Ben and Cory, the youngest (who was four years Al's junior)

Industry Interview

Wed, 11 Nov 2000
Business models, roadmaps and a little black magic: An interview with Bob Hilton

Wrapping up 2000

Wed, 11 Nov 2000
What a year this has been! Advanced Packaging magazine has seen many great changes this year: a new and invigorated staff...an enthusiastic publisher...a renewed commitment to the industry...a fresh new design

Bare die will shine on

Fri, 9 Sep 2000
Circuit manufacturers are more accepting of bare die than they were in the past

Lost in the PR labyrinth

Fri, 9 Sep 2000
How does a new product or technology reach its customers, gain a strong market share or become an industry standard?

Satisfying the Appetite of Power-hungry Chips

Thu, 3 Mar 2007
Increasing complexity of chips - more transistors operating faster at lower and varied voltages with more I/O - is a well-known phenomenon.

Catching Up with Moore’s Law: Are Industry Consortia the Key?

Sun, 7 Jul 2007
Greetings from the Constitution State. For my first contribution to this publication - since developments in new packaging technology have failed to keep pace with Moore’s Law - I chose to consider industry consortia’s role in accelerating the rate of advancement in device packaging.

BGA ...Who ever would have thought?

Sun, 10 Oct 2000
BGAs, BGAs, BGAs everywhere! How many different types of BGAs are there? There are BGAs that use ceramic substrates, organic substrates, flex tape substrates, thin film substrates and metal (leadframe) substrates

Our gift to you

Sun, 10 Oct 2000
When it's this good, why wait? That was our thinking behind the redesign of Advanced Packaging magazine that you now hold in your hands

Think Tank

Fri, 9 Sep 2000
Four entrepreneurs - Amber, Beryl, Carrie and Denise - each purchased a rectangular lot to build a factory

2007: Packaging Saves the World

Mon, 1 Jan 2007
Perhaps for the first time in electronics, packaging has come into its own. As you read this forecast for 2007, you will notice a new attitude filled with confidence and enthusiasm.

Merger Consolidates Prototyping Services

Mon, 1 Jan 2007
PLANO, TX - A merger between CV Inc. Business Solutions, FIB-X, Microtech Analytical Labs LP (MAL), and Fast Semiconductor, Inc. (FAST Semi), has created a full-scale prototyping house for chip-scale, flip chip, BGA, and QFN packages, with bumping and wire-bonding, assembly, failure analysis, design debug, and other packaging services.

APEX Commemorates 50 Years of IPC

Mon, 1 Jan 2007
LOS ANGELES - IPC Printed Circuits Expo/APEX/Designers Summit, February 18-22 in Los Angeles, will host the 50th anniversary celebration of the IPC - Association Connecting Electronic Industries, as well as various other celebratory and informative events.

Millenium Prediction: A Package for All Occasions

Sat, 1 Jan 2000
Looking for the perfect package? For the semiconductor manufacturer, selecting the optimal packaging solution can be tough. To make the "right" choice, it is important to comprehend both the technical and business requirements of their product.

Non-anhydride Flip Chip Underfill

Sat, 1 Jan 2000
Amicon E 1158 flip chip underfill encapsulant is said to cure in five minutes at 135°C and can sustain more than 3,000 thermal shocks from -55°C to 125°C with no delamination. The product is highly flowable, non-anhydride-based and designed to fill gaps of 50 or more microns. It reportedly exhibits good adhesion to common die passivations.

High-purity Underfill Encapsulant

Sat, 1 Jan 2000
ME-525 is a high Tg, low CTE, high-purity underfill encapsulant designed for use with small-gap flip chip devices. The product is said to penetrate gaps as small as 2 mils and cure in 30 minutes at 150°C. Easy to dispense and with high chemical and moisture resistance, the product has low viscosity, high flow for capillary chip underfill and is capable of flowing under a 1/4" die in less than 60 seconds.

Underfill Technology

Sat, 1 Jan 2000
The "No Flow-Fluxing" underfill is designed to help manufacturers and assemblers of area-array devices, such as flip chip, CSP and BGA, reduce the overall cost of device assembly. This technology reportedly eliminates separate fluxing, flux cleaning, underfill capillary flow and post-cure operations using underfill in area-array device assembly because the underfill performs the dual role of fluxing the interconnects and curing to become the underfill layer.

And the Award Winners are ...

Sat, 1 Jan 2000
Recently, two distinguished colleagues were presented the First Annual MicroElectronics Packaging Technologist Award for their significant contributions in the advancement of packaging technology. The award was co-sponsored by Advanced Packaging magazine and MEPTEC and was presented at the recent MEPTEC 1999 Symposium in San Jose, California. While you undoubtedly know Advanced Packaging magazine, some readers may not be familiar with MEPTEC - a Silicon Valley organization dedicated to semicondu

The following is a commentary on the article "Moiré Interferometer:

Sat, 1 Jan 2000
The following is a commentary on the article "Moiré Interferometer: Assist in Electronic Packaging Development," which was published in the September 1999 issue of Advanced Packaging (pp. 44-50).

Letters to the Editor

Sat, 1 Jan 2000
The article in your October issue, "True Cost of Outsourcing" by Randie Reed, is written from the perspective of a controller. I have found through my experiences that the "make or buy" decision is a very important one that is often quite complex. This article simplifies the complexity. The true cost of buying outside may be far higher than the production costs, overhead costs and delivery costs. Most companies making a tangible product have to buy some things and make some things. What to make

Advanced Packaging in a New Millennium

Sat, 1 Jan 2000
Now that we have crossed the millennium threshold, what`s the state of semiconductor chip packaging? Actually, that question has preoccupied the editorial team at Advanced Packaging for the past six months now, and while we may not have the answers yet, we have the mechanisms in place to track both old and new trends that will shape our industry in 2000. Although each issue of Advanced Packaging is set to explore late-breaking technology in a broad sense, the primary editorial focus will remain

Pizza Contest in Pizza Bay

Tue, 8 Aug 2000
Five pizza companies - Andy's, Bebe's, Cassidy's, Denzy's and Elsie's - submitted 5 pizzas each, with toppings of pepperoni, bologna, cheese, anchovies and pineapple, for the Annual Best Pizza Contest held in Pizza Bay

Making connections... across the board

Tue, 8 Aug 2000
When I was first introduced to the semiconductor packaging industry, my colleagues educated me about interconnection technologies - gave me a crash course on ICs and PCBs, and loaded me down with jargon

The School Break

Thu, 6 Jun 2000
"I know that you wanted only 10, 100, 10K and 100K Ohm resistors for your school project (SP), but I bought a box that contains more than the quantities you need, as well as several resistors of other values," said Tom's dad

Reworkable Flip Chip Underfills

Tue, 2 Feb 2000
Loctite 3567 is an epoxy-based liquid underfill compatible with polyimide-passivated flip chip, CSP and BGA assemblies. The product allows a flip chip to be replaced after testing determines that the chip is defective; packages can be removed by heating the package and the underfill for one minute at 210 to 220∞C, where the epoxy will begin to decompose. The adhesive cures in 5 to 15 minutes when exposed to temperatures of 150 to 165∞C, is easy to dispense and quickly penetrates gaps

Component Placement Cell

Tue, 2 Feb 2000
The 3500-II is a fully automatic, high-accuracy die bonder capable of performing automated eutectic die attach using backside metalized die or preforms, and enables bonding of thin die with air bridges using 2 or 4-sided perimeter collets. Using look-up and look-down cameras for flip chip applications and "relative-to" referencing for linear micro-strip line placement, the 3500-II yields accuracies of ±0.5 mil.

Dispensing System

Tue, 2 Feb 2000
The M-2000 dispensing system is suited for high-volume, production-critical packaging applications, including flip chip underfill, cavity fill, and dam and fill. The product features a DP-3000 series linear pump for increased closed loop control and better than 1 percent, 3 sigma dispensing accuracy. The platform includes mass flow calibration, software-managed temperature control, advanced lighting systems, and operating software for easy set-up and system control.

Tackling 2000 and Beyond

Tue, 2 Feb 2000
During the past few months, there has been a spirit of regeneration throughout the world, as many eagerly anticipated the calendar year rolling over to 2000. Regardless of which stance you took regarding the true start of the third millennium, the result of last New Year`s still tends to be the same: From individuals to entire companies, everyone is talking about doing something new. Many tackled weighty resolutions this year like none other, while others just analyzed how to better accomplish t

Shining Stars of the Industry

Sat, 9 Sep 2001
The Recipients of The 2001 Advanced Packaging Awards

Keeping advanced product development viable

Sat, 9 Sep 2001
Nearly every manufacturing company today has resources and budgets assigned to examine future designs of existing products, or to develop new products for existing and new markets

News

Sat, 9 Sep 2001
Though Toshiba once had the smallest logic device in a two-billion unit market ($400 to 500 million), Texas Instruments (TI) has taken the competitive lead by introducing the NanoStar Little Logic - the smallest single-gate logic family available

IMaps flip chip report

Sat, 9 Sep 2001
IMAPS flip chip event targets an eager audience

The back-end process: Step 7 - Solder bumping step by step

Sun, 7 Jul 2001
Wafer bumping is replacing wire bonding as the interconnection of choice for a growing number of components

Editorial

Mon, 5 May 2000
It was a pleasure to meet you...

CSP and Flip Chip Packaging

Sat, 1 Jan 2000
Although wire bond technology continues to dominate the integrated circuit (IC) packaging market from a volume standpoint, over the past few years most of the industry "buzz" has focused on the increasing use of leading-edge packaging techniques, such as chip scale packaging (CSP) and flip chip. Despite that they represent a small portion of the overall packaging volume, most industry analysts have been predicting very rapid growth rates for CSP and flip chip because, ultimately, they represent

Low-cost High-throughput Flip Chip Processing

Sat, 1 Jan 2000
Flip chip assembly technology is gaining increased acceptance in the electronics industry. Annual growth rates projected through the next decade are 40 percent or higher. While flip chip technology was developed more than 30 years ago and has been in production on ceramic substrates for decades, it has yet to achieve cost competitiveness with low-cost surface mount technology (SMT). In order to achieve cost competitiveness, new and innovative material systems and process technologies are require

Christmas in July

Thu, 6 Jun 2000
Every summer in Chicago, there's a special occasion called Christmas in July - a non-secular event during which companies and individuals donate their time to volunteer in their communities

Package or surface mount assembly?

Wed, 3 Mar 2000
A client recently posed the question, "Can you help us to define the difference between semiconductor packaging and surface mount assemblies?" "It`s obvious," you say? "Semiconductor packaging deals with bare die and surface mount assembly uses only packaged devices." But upon further consideration, the problem becomes far more complex and depends greatly on the perspective taken. Technically speaking, where would thick and thin film hybrids belong? And multi-layer ceramics? And how about multi-

Letter to the Editor

Wed, 3 Mar 2000
I was pleased to see the results of the Third Annual Semi Dice Inc. Bare Die Survey featured in the pages of the November/December issue of your magazine ("CSP No Match for Bare Die"). I want to clarify the results on the survey as they relate to Chip Scale Packaging. CSP is certainly a viable packaging option and has a bright future. The survey results clearly indicate that CSPs will have little impact on the Bare Die Market.

Ready, set...write!

Wed, 3 Mar 2000
In the short time I have worked for Advanced Packaging magazine, I have received many phone calls from potential authors who want to write for the magazine. Wonderful! Our best articles tend to come directly from those immersed in the industry, so these inquiries are always welcome. We are always looking for insightful articles that will help our readers better understand this industry - in effect, helping people connect the dots so everyone can excel in their jobs.

FCT signs flip chip license

Wed, 3 Mar 2000
Flip Chip Technologies (FCT) LLC, a joint venture of Kulicke & Soffa Industries and Delphi Delco Electronics Systems, has signed a 10-year technology transfer agreement with Siliconware Precision Industries Co. Ltd. (SPIL). SPIL will use FCT`s proprietary flex-on-cap wafer bumping and redistribution technologies to manufacture advanced flip chip packages at its Taichung, Taiwan, assembly facility.

PennWell acquires Advanced Packaging

Tue, 2 Feb 2000
LIBERTYVILLE, ILL. - PennWell, a diversified media company with magazines, trade shows and conferences in more than 40 markets worldwide, has acquired Advanced Packaging and four other magazine titles (SMT, Connector Specifier, Vacuum & Thinfilm and SMT International) from Libertyville, Ill.-based IHS Publishing Group.

Underfill: what designers applaud and manufacturers tolerate

Tue, 2 Feb 2000
Flip chip underfill is the enabling process for flip chip interconnect survival on printed circuit boards (PCB). Its function: to distribute shear stress normally placed on the solder bumps. Stress is a product of the dissimilar coefficients of thermal expansion between the silicon integrated circuit and the laminate. Also, underfill enables the use of larger flip chip die on ceramic substrates, which historically feature smaller flip chips assembled with only compliant solder bumps to absorb co

Patent Report for Packages

Sat, 1 Jan 2000
Montara, Calif. - The CSP, BGA and WLP Technology 2000 Report covers all the active U.S. patents relating to these packages, including wafer-level technologies, by summarizing and cross-referencing their characteristics. Suitable for use by companies actively involved in these packaging areas, it is said to be a valuable tool in searching for and understanding the covered ideas.

Auburn Installs SMT/ Flip Chip Assembly Line

Sat, 1 Jan 2000
Auburn, Ala. - With support from Cookson Electronics, Siemens and Heller Industries, Auburn University has completed the installation of an assembly line called the Laboratory for Electronics Assembly & Packaging (LEAP) for use by its engineering students. The line begins with a printer (MPM) having a paste inspection capability that also is able to print projects ranging from solder bumping of wafers and evaluations of lead-free solders for surface mount to high-temperature adhesive die attachm

Underfill Material Permits Flip Chip Rework

Sat, 1 Jan 2000
At the culmination of more than a year`s research and development, Loctite Corp. has introduced Loctite 3567 for flip chip, ball grid array (BGA) and chip scale packaging (CSP) assemblies. The material is said to provide the processing and reliability of conventional thermoset underfills with the added advantage of reworkability. Developed jointly with Cornell University, it relies on a patented epoxy monomer added to the formulation to permit thermal rework. The project is part of the National

Transport/Handling Solution

Wed, 3 Mar 2000
Fluoroware has launched the patent-pending JEDEC Style Waffle Pack Tray-in-Tray for chip scale packaging and wafer level packaging applications. This transport and handling solution allows waffle packs of varying pocket sizes to be used in conjunction with a JEDEC-compliant tray during assembly and test, which eliminates the need for tray retooling. The tray-in-tray solution consists of the company`s waffle pack trays, which are placed inside a JEDEC-compliant tray, allowing for interface with e

What, Me Worry?

Sat, 9 Sep 2007

Flux and Underfill Compatibility in a Lead-free Environment

Wed, 8 Aug 2007
Since their introduction nearly 20 years ago, the benefits of integrating flip chips into modern devices have been well proven.

SATS provider Carsem begins LED packaging and test

Fri, 5 May 2012

Semiconductor packaging and test services provider Carsem will assemble and test LED packages, partnering with a key customer and applying semiconductor packaging technologies for better LEDs.


GaN Systems collaborates with APEI to optimize power electronics packaging

Thu, 5 May 2012

GaN Systems and Arkansas Power Electronics International will co-develop a high-temperature, high-performance package optimized for gallium nitride (GaN) transistors and diodes.


NXP increases pad pitch while shrinking package form factor

Tue, 4 Apr 2012

NXP Semiconductors released the new SOT1226 "Diamond" package using a

EoPlex builds packaging facility in Malaysia

Tue, 4 Apr 2012

EoPlex Limited, a subsidiary of ASTI Holdings Limited, Singapore, will open a new factory for its xLC semiconductor package technology in Q2 2012, in Malaysia.


STATS ChipPAC adds Pasquale Pistorio, STMicroelectronics leader, to Board

Mon, 4 Apr 2012

Semiconductor packaging service provider STATS ChipPAC Ltd. (SGX-ST:STATSChP) appointed Pasquale Pistorio as a member of the Board of Directors, effective immediately.


Mold packaging meets metal TSV for 5-10x density of conventional substrates

Thu, 4 Apr 2012

Silex Microsystems brought its Met-Via full-wafer-thickness TSV technology into Chip Architectures by Joint Associated Labs for European Diagnostics, where it is being used to create cost-effective molded chip-level packaging with through metal vias.


ChipMOS expands semiconductor assembly and test services with new building in Taiwan

Mon, 4 Apr 2012

ChipMOS TECHNOLOGIES INC. (ChipMOS Taiwan), purchased a 393,173sq.ft. building adjacent to its existing facility in Southern Taiwan Science Park.


Advanced semiconductor packaging start-up Deca could take over SPWR fab

Mon, 4 Apr 2012

WLCSP start-up Deca Technologies might take over SunPower Corp.'s Fab 1, when the solar photovoltaics supplier consolidates its Philippine manufacturing operations to Fab 2 this quarter.


Georgia Tech targets thin 3D packaging with new consortium

Wed, 4 Apr 2012

Georgia Tech's Packaging Research Center proposes a new consortium on 3D semiconductor packaging called 3D ThinPack for ultra-miniaturized 3D heterogeneous, RF, digital and power modules in partnership with global companies.


Invensas face-down die packaging replaces SODIMM

Wed, 4 Apr 2012

Invensas Corporation, a wholly owned subsidiary of Tessera, unveiled a DIMM-IN-A-PACKAGE multi-die face-down (xFD) packaging architecture for memory semiconductors in low-profile devices.


Endicott Interconnect names David Van Rossum new CFO

Tue, 4 Apr 2012

Endicott Interconnect Technologies has appointed David W. Van Rossum to the position of Chief Financial Officer, effective immediately.


ONNN

Mon, 4 Apr 2012

ON Semiconductor (Nasdaq: ONNN) will develop a next-generation star tracker CMOS image sensor with the European Space Agency. The sensor will be used in star trackers, sun sensors and other scientific applications.


Terepac builds miniaturized embedded circuits with wireless connectivity

Tue, 4 Apr 2012

Terepac Corporation, developer of tiny digital electronics, has launched the TereTag miniaturized circuit design that is embedded in items to enable the "Internet of Things."


Cypress Semiconductor transfers back-end packaging lines to China

Tue, 3 Mar 2012

Cypress Semiconductor transferred 7 back-end semiconductor package assembly lines from its Philippines facility to Chinese packaging subcontractor Jiangsu Changjiang Electronics Technology Co.


TI adds bare die to small-quantity semiconductor packaging options

Tue, 3 Mar 2012

Texas Instruments Incorporated (TI, TXN) now offers bare die in quantities as low as 10 pieces for initial prototyping, and larger quantities (full waffle trays) for production volumes.


Imec ultrathin chip packaging yields improved

Fri, 3 Mar 2012

Research organization imec introduces important changes to its ultrathin chip packaging (UTCP) technology, increasing yields 15-20%.


Semiconductor wafer fab utilization rates bucked expectations in late 2011

Thu, 3 Mar 2012

The Global Semiconductor Alliance (GSA) released its GSA Q1 Wafer Fabrication & Back-End Pricing Reports, tracking fab utilization rates, wafer and mask costs, and package pricing.


2011 ITRS: DRAM, 3D Flash, MEMS, nano scaling steal the show

Wed, 2 Feb 2012

The 2011 International Technology Roadmap for Semiconductors (ITRS) has been publicly released. Several areas of advancement are highlighted in the 2011 ITRS: DRAM and Flash memory, and MEMS.


European microelectronics fab database tracks major changes over past 5 years

Mon, 2 Feb 2012

Yole Developpement released "European Microelectronic Fabs Database & Report 2012," a database and report on the European microelectronics and microsystem manufacturing fabs, pilot lines, and major R&D organizations.


Apple shares list of suppliers

Fri, 1 Jan 2012

For the first time, Apple Inc. has publicly published a list of over 150 companies that the electronics giant says represent 97% of its procurement expenditures for materials, manufacturing, and assembly of products worldwide.


Apple iPhone 4S steals smartphone show in Q4 2011; Samsung wins the year

Fri, 1 Jan 2012

While Apple's release of the iPhone 4S in Q4 2011 "unleashed tremendous pent-up demand" from consumers, Samsung used its broad range of smartphones to take the top spot, reports IHS.


Toshiba builds semiconductor fab in Thailand to replace flooded fab

Tue, 4 Apr 2012

Toshiba Corporation (TOKYO: 6502) will rebuild its semiconductor manufacturing operations in Thailand by relocating Toshiba Semiconductor Thailand Co., Ltd. (TST) to a new manufacturing facility.


ASMC will focus on productivity and technology challenges

Wed, 4 Apr 2012

The 23rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2012) will be held May 15-17 in Saratoga Springs, New York. The conference will feature presentations of more than 85 peer-reviewed manuscripts covering critical process technologies and fab productivity. This year’s event features a panel discussion on “Competing for R&D Dollars,” moderated by Solid State Technology Editor-in-Chief Pete Singer.


Conference Report: MRS Spring 2012, Day 3

Thu, 4 Apr 2012

Blogger Mike Fury reports from the MRS Spring 2012 meeting in San Francisco. Highlights from the third day: leakage and TDDB in low- κ dielectrics, flexible energy storage and conversion, Mn capping layers and diffusion barriers, hard masks for Cu interconnects, nanogenerators, Cu in RF, flexible temperature sensors, NEMS and MEMS in HDD, ZnO nanostructures, and various aspects of CMP.


David McCann of GLOBALFOUNDRIES to speak at The ConFab 2012

Thu, 5 May 2012

Solid State Technology is proud to announce that David McCann will speak at The ConFab 2012. David, the Senior Director for Packaging R&D at GLOBALFOUNDRIES in Malta, New York, will speak on the evolution toward silicon-based interconnect and packaging, which is having profound impact on how we think about technology development and the supply chain.


CMOS image sensor suppliers ramp up 300mm capacity

Fri, 5 May 2012

CMOS image sensors (CIS) are breaking sales records again, after several years without upward momentum, reports IC Insights. New portable systems and embedded imaging are lifting CIS to $6.3 billion in 2012 and new record sales each year through 2016.


Present at coolingZONE LED 2012 in Berlin

Thu, 2 Feb 2012

coolingZONE LED, May 29-31 in Berlin, is soliciting technical presentations on LED energy consumption, LED packaging, heat and air-flow simulations of LED products, and related topics.


SEMICON Europa 2012 seeks presenters

Fri, 3 Mar 2012

SEMI is seeking papers for technical sessions and presentations at the upcoming SEMICON Europa 2012, October 9-11 in Dresden, Germany. Technical presentation abstracts are due April 30.


Taiwan allows higher Chinese investments in LCDs, semiconductors, fab equipment, more

Wed, 3 Mar 2012

Taiwan raised investment ceilings for Chinese investors in LCDs, semiconductors, IC assembly and test, microelectronics production equipment, and metal tool manufacturing.


IBM drills optical vias in chip for 1Tbit/sec transmission

Fri, 3 Mar 2012

IBM scientists developed a prototype optical chipset, Holey Optochip, that can transfer 1Tbit per second as a parallel optical transceiver, using optical vias through a standard 90nm CMOS chip.


SEMI adds session, extends abstract deadline for China chip conference

Tue, 10 Oct 2012

SEMI has extended the deadline to submit proposed papers to next spring's China Semiconductor Technology International Conference 2013, and added a new symposium on circuit design, system integration, and application.


SEMI: Chip equipment slump extending into 2013, across-the-board rebound in 2014

Thu, 12 Dec 2012

Semiconductor equipment demand is persistently sluggish as the industry takes a break from a "multiyear expansion period" to digest recent investments and wrestle with a broader economic slowdown, acknowledges SEMI in its updated year-end forecast. But make no mistake: leading-edge technology investments are still happening, and growth will return in the typical cyclical pattern.


STATS ChipPAC to expand in South Korea

Mon, 11 Nov 2012

STATS ChipPAC Ltd. plans to expand its semiconductor assembly and test operation in South Korea.


IEDM 2012 slideshow 14

Tue, 12 Dec 2012

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IEDM 2012 slideshow 02

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IEDM 2012 slideshow 01

Tue, 12 Dec 2012

IEDM 2012 slideshow: Sneak preview of 14 conference papers

Tue, 12 Dec 2012

We've scanned the entire conference program for next week's 58th annual IEEE International Electron Devices Meeting (IEDM), to present a quick sampling of some of the more intriguing papers.


Rudolph enters back-end lithography market

Thu, 12 Dec 2012

Rudolph Technologies, Inc. (Nasdaq: RTEC) has entered the back-end advanced packaging lithography market, with the acquisition of Azores Corp., and the introduction of a new 2X reduction stepper called the JetStep.


The ConFab 2012: A retrospective

Thu, 8 Aug 2012

The ConFab, Solid State Technology’s invitation-only event for the semiconductor industry, took place in June, with presenters from top companies and analyst firms. If you couldn’t be there, check out all the coverage from the event -- reports, presentations, video interviews and more.


EMCORE switches fab management and process control to Camstar system

Fri, 7 Jul 2012

EMCORE, compound semiconductor-based components and subsystems supplier, will replace multiple legacy manufacturing systems in its compound semiconductor fab and back-end packaging operations with the Camstar Enterprise Platform.


Interviews with CEA-Leti researchers at SEMICON West

Thu, 7 Jul 2012

CEA-Leti presented research updates alongside SEMICON West this week. After the talks on device architecture, 3D and 2.5 packaging interconnects, large-scale computing and power consumption, and more, CEA-Leti’s researchers joined Solid State Technology to talk about their fields of interest.


Osram plans LED packaging facility in Wuxi

Fri, 6 Jun 2012

OSRAM AG will build a new LED assembly plant in Wuxi, Jiangsu, China, packaging LED chips fabbed at its Regensburg, Germany and Penang, Malaysia wafer processing facilities.


ECTC: Focus on 3D integration and TSVs

Fri, 6 Jun 2012

A main focus of this year’s Electronic Components and Technology Conference (ECTC), held this week in San Diego, is 3D integration and through silicon vias (TSVs).


Conference Report: International Interconnect Technology Conference, IITC

Tue, 6 Jun 2012

The 15th IITC (International Interconnect Technology Conference) opened Monday, June 4 at the Doubletree Hotel in San Jose, CA. Recurring themes this year were variations on 3D and TSV, novel systems and packaging, and back end memory. Mike Fury reports.


Imec at SEMICON West: Interview with Luc Van den hove

Tue, 7 Jul 2012

Luc Van den hove, president and CEO, imec, spoke with Solid State Technology, covering imec’s major announcements and research presentations to take place during SEMICON West 2012.


Silicon chip-on-board LED substrate enables best thermal dissipation

Mon, 6 Jun 2012

Daewon Innost achieved what it says is the LED industry’s best thermal dissipation performance on its Glaxum LED Array family, based on the proprietary Nano-Pore Silicon Substrate (NPSS) technology.


A*STAR and Hitachi to collaborate on 3D ICs

Fri, 9 Sep 2012

Singapore’s A*STAR’s Institute of Microelectronics (IME), and Hitachi Chemical Co., will be collaborating on a joint research program to develop high performance material technologies for thin wafer processing for 3D IC packaging.


UMC, ST to develop 65nm backside CMOS image sensors

Mon, 9 Sep 2012

Integrating power electronics design technologies

Thu, 8 Aug 2012

The field of power electronics, the application of electronics for the control and conversion of electric power, is underpinned by basic electrical principles that were established in the distant past by the pioneers of electrical science. But today, the need to supply, modify and control the voltage, current or frequency of electric power arises in a vast number of applications and products spanning a huge range in terms of power handling capability.


Devan Iyer, director of TI's semiconductor packaging operations, joins The ConFab advisory board

Tue, 10 Oct 2012

Devan Iyer, director of Semiconductor Packaging in Texas Instrument’s Manufacturing Group, has joined the advisory board of The ConFab.


Europe to unite research efforts in Silicon Europe cluster alliance

Mon, 10 Oct 2012

Four of the leading micro- and nanoelectronics regions in Europe are joining forces to form a cluster alliance called “Silicon Europe.”


STATS ChipPAC expands TSV work into mid-end-of-line

Wed, 8 Aug 2012

STATS ChipPAC says it has expanded its through-silicon via (TSV) capabilities with a 300mm mid-end manufacturing operation targeting mid-end-of-line semiconductor manufacturing, including microbump technology down to 40μm, temporary bond/de-bonding, backside via reveal, isolation, and metallization.


Hesse & Knipps introduces new heavy wire bondhead

Tue, 8 Aug 2012

Hesse & Knipps, Inc., the Americas subsidiary of Hesse & Knipps Semiconductor Equipment GmbH, added the HBK08 Loop Former Bondhead to its BONDJET BJ935 and BONDJET BJ939 fully automatic heavy wire bonders.


On-board heaters can self-heal flash memories

Thu, 9 Sep 2012

At the upcoming International Electron Device Meeting, Macronix researchers will describe how they built flash memories that could heal themselves by means of tiny onboard heaters that provide thermal annealing just at the spots where it is needed.


IEDM unveils 2012 program highlights

Mon, 9 Sep 2012

The 58th annual IEDM will take place December 10-12, 2012 at the San Francisco Hilton Union Square, preceded by a full day of Short Courses on Sunday, Dec. 9 and by a program of 90-minute afternoon tutorial sessions on Saturday, Dec. 8.


Horizontal channels key to ultra-small 3D NAND

Thu, 9 Sep 2012

The first working 3D NAND flash memory at sub-40nm feature sizes will be described by Macronix researchers at this year’s International Electron Devices Meeting (IEDM).


RRAM synapses mimic the brain

Thu, 9 Sep 2012

At this year’s IEDM, a team led by Korea’s Gwangju Institute of Science and Technology will detail a high-speed pattern-recognition system comprising CMOS “neurons” and an array of resistive-RAM (RRAM)-based “synapses,” which demonstrated STDP, a brain-like function.


Deca Technologies appoints Chris Seams as CEO

Mon, 6 Jun 2013

Deca Technologies, an electronic interconnect solutions provider to the semiconductor industry, today announced it has named semiconductor industry veteran Chris Seams its new CEO.


TSMC keynoter suggests WLSI at IITC

Fri, 6 Jun 2013

In a keynote at the IEEE International Interconnect Technology Conference (IITC), Douglas Yu from TSMC talked about Moore’s Law scaling becoming increasingly difficult.


"Generation Mobile": Advanced Packaging Technology at SEMICON West

Thu, 6 Jun 2013

Advanced packaging technology is undergoing dramatic changes as the smart phones and new sensor technologies demand continued improvements in form and function.


Fab equipment spending: 23% growth for 2014

Tue, 6 Jun 2013

Fab equipment spending will grow two percent year-over-year  (US$ 32.5 billion) for 2013 and about 23 to 27 percent in 2014 ($41 billion) according to the May edition of the SEMI World Fab Forecast.


Signetics announces plans to increase their flip chip package assembly capacity

Tue, 5 May 2013

Signetics Corporation today announced that it has again approved capex plans that will further expand their capacity for flip chip package assembly at their factory in Paju, South Korea.


Mentor Graphics and TSMC collaborate on 20nm IC physical verifications

Wed, 5 May 2013

Mentor Graphics Corp. today announced significant achievements in its continued collaboration with TSMC on 20nm physical verification kit optimizations.


Dow Corning and SÜSS MicroTec report new temporary bonding solution for 2.5D and 3D IC packaging

Wed, 5 May 2013

The semiconductor industry’s march toward broader 3D IC integration marked an important milestone this week at ECTC 2013, with the report of an advanced new temporary bonding solution for 3D TSV semiconductor packaging.


OMRON develops MEMS non-contact thermal sensor utilizing wafer-level vacuum packaging

Wed, 5 May 2013

OMRON Corporation today announced that they have finished development work on the world's first infrared sensor manufactured with wafer-level vacuum packaging technology to create a 16x16 element MEMS non-contact infrared thermal sensor capable of highly precise 90-degree area detection.


Mentor and Tezzaron optimize Calibre 3DSTACK for 2.5/3D-ICs

Mon, 5 May 2013

Mentor Graphics Corp. and Tezzaron Semiconductor Corp. today announced they are collaborating to integrate the Mentor Calibre 3DSTACK product into Tezzaron’s 3D-IC offerings.


Yole Developpement conducts 2.5D, 3DIC and TSV interconnect patent investigation

Wed, 5 May 2013

Yole Développement announced its 2.5D, 3DIC and TSV Interconnect Patent Investigation report. For this analysis of 3D packaging technology patents, more than 1800 patent families have been screened.


MOSIS collaborates with imec, Tyndall and ePIXfab on silicon photonics

Thu, 5 May 2013

MOSIS, a provider of low-cost prototyping and small volume production services for custom ICs, has teamed up with imec, Ireland's Tyndall National Institute and ePIXfab, the European Silicon Photonics support center providing low-cost prototyping services for photonic ICs.


EI

Thu, 5 May 2013

Endicott Interconnect Technologies, Inc. (EI) announced that its System-In-Package (SiP) technology performed successfully in a military test of a small hit-to-kill interceptor designed to defeat rocket, artillery and mortar attacks.  


SATS market grew 2.1 percent in 2012

Thu, 5 May 2013

The worldwide semiconductor assembly and test services (SATS) market totaled $24.5 billion in 2012, a 2.1 percent increase from 2011, according to final results from Gartner, Inc.


Amkor Technology appoints Steve Kelley president and CEO

Wed, 5 May 2013

Amkor Technology, Inc. today announced that Stephen D. Kelley has been appointed to serve as president and chief executive officer and as a director of the company, effective May 8, 2013.


Aptina and LFoundry to partner on CMOS image sensor manufacturing

Thu, 3 Mar 2013

LFoundry to manufacture wafers for Aptina following LFoundry’s purchase of Micron’s Avezzano, Italy semiconductor fabrication facility.


Memory, foundry and LED markets drive fab spending in southeast Asia

Thu, 4 Apr 2013

Increased spending in NAND and flash by Micron, LEDs by Philips and Osram, and continued investments by GLOBALFOUNDRIES will create new opportunities for equipment and materials suppliers in Southeast Asia.


Global semiconductor sales outpace last year through Q1 of 2013

Tue, 5 May 2013

Sales in March 2013 were up slightly compared to February 2013 and March 2012.


Silex joins ENIAC project to develop new solutions for TSV and wafer bonding

Mon, 5 May 2013

Silex Microsystems, the world’s largest pure-play MEMS foundry, today announced that it has joined an international European Union-funded program aimed at developing a new MEMS manufacturing platform based on advanced inkjet-based printing technologies.


SEMI reports March book-to-bill ratio of 1.14

Fri, 4 Apr 2013

North America-based manufacturers of semiconductor equipment posted $1.14 billion in orders worldwide in March 2013 (three-month average basis) and a book-to-bill ratio of 1.14, according to the March Book-to-Bill Report published today by SEMI.


Cracking the potential of the glass wafer market

Thu, 4 Apr 2013

Over the last few years, glass has gained considerable interest from the semiconductor industry due to its very attractive electrical, physical and chemical properties, as well as its prospects for a relevant and cost-efficient solution. The application scope of glass substrates in the semiconductor field is broad and highly diversified.


Ultra-low power processor operates at near-threshold voltage

Thu, 2 Feb 2013

At this week’s International Solid State Circuits Conference (ISSCC 2013), imec and Holst Centre presented an ultra-low power processor that operates reliably at near-threshold voltages.


Leti to coordinate European supply chain in silicon photonics

Wed, 2 Feb 2013

CEA-Leti today announced that it will coordinate a four-year project aimed at building a European-based supply chain in silicon photonics and speeding industrialization of the technology.


STMicroelectronics 28nm FD-SOI technology hits 3GHz operating speed

Wed, 2 Feb 2013

STMicroelectronics announced today another milestone in its testing of its 28nm FD-SOI Technology Platform.


2013: Continued strength in 200mm

Thu, 1 Jan 2013

80 percent of the devices used for portable and mobile applications are currently manufactured on 200mm or smaller wafers. How this plays out going forward could change who the dominant players will be.


2013: Advanced packaging requirements are more complex, require new solutions

Wed, 1 Jan 2013

Advanced packaging requirements are driving the evolution of back end manufacturing to become more similar to the front end.


2013: Thriving in the transition to 450mm

Wed, 1 Jan 2013

The development of innovative technologies that solve the critical issues for the transition and adoption of 450-mm manufacturing will be the defining factor for whether a company merely survives or thrives.


Silicon wafer revenues decline in 2012

Tue, 2 Feb 2013

Worldwide silicon wafer revenues declined by 12 percent in 2012 compared to 2011, according to the SEMI Silicon Manufacturers Group (SMG) in its year-end analysis of the silicon wafer industry.


SEMI China releases Top Ten list of packaging and assembling facilities

Thu, 2 Feb 2013

Although many are small companies manufacturing low-pin count devices, all of the world’s “Top 10” OSAT, Outsourced Semiconductor Assembly and Test, players have one or more assembly and testing facilities in China.


Econometric Forecast: Regional developments to affect growth of semiconductor industry

Thu, 2 Feb 2013

In the first of two installments, we examine the global issues facing the semiconductor industry, as released by Linx Consulting in The Econometric Semiconductor Forecast.


Econometric forecasting service predicts 6% growth in semiconductor wafers in 2013

Thu, 2 Feb 2013

A new econometric semiconductor industry forecast predicts semiconductor wafer area production to grow slightly less than 6% in 2013, according to Linx Consulting.


ISMI to partner with Araca

Wed, 2 Feb 2013

SEMATECH announced today that Araca Inc., a leading provider of products and services for chemical mechanical planarization research and development, and the International SEMATECH Manufacturing Initiative (ISMI) are partnering to deliver CMP processing and productivity solutions to help chip manufacturers increase yields, reduce equipment downtime and lower consumables costs.


Dow Corning and IBM scientists develop new materials for board-level photonics

Tue, 2 Feb 2013

Dow Corning and IBM scientists unveiled a major step in photonics yesterday at the Photonics West conference, using a new type of polymer material to transmit light instead of electrical signals within supercomputers and data centers.


Semiconductor R&D spending rises 7% despite weak market

Tue, 2 Feb 2013

Spending on research and development by semiconductor companies grew 7% in 2012 to a record-high $53.0 billion, even though the semiconductor market declined 1% to $317.6 billion.


BGA guideline features expanded focus on mechanical reliability

Wed, 1 Jan 2013

IPC recently released the C revision of IPC-7095, Design and Assembly Process Implementation for BGAs.


STATS ChipPAC and UMC unveil 3D IC developed under open ecosystem

Wed, 1 Jan 2013

STATS ChipPAC and UMC announced the world's first demonstration of TSV-enabled 3D IC chip stacking technology developed under an open ecosystem collaboration.


Renesas and J-Devices sign MoU on transfer of back-end facilities

Wed, 1 Jan 2013

Renesas and J-Devices signed a memorandum of understanding regarding the transfer of the semiconductor back-end production business of three facilities operated by Renesas’ wholly owned manufacturing subsidiaries


GlobalFoundries adding R&D facility to NY fab campus

Fri, 1 Jan 2013

GlobalFoundries says it plans to build a $2 billion "Technology Development Center" R&D facility at its Fab 8 campus in Saratoga County, NY, for semiconductor technology development and manufacturing:  EUV lithography photomasks to new interconnect and packaging technologies enabling 3D chip stacking, "and everything in between."


Five IC suppliers to hold one-third of 300mm wafer capacity in 2013

Wed, 2 Feb 2013

Samsung tops list; IC foundries expected to show biggest capacity gains through 2017.


300-millimeter thin-wafer products by Infineon now being shipped worldwide

Tue, 2 Feb 2013

In February, Infineon received the first customer go-aheads for products of the CoolMOS family produced by the 300-millimeter line at their site in Villach, Austria.


GaN Systems expands with new UK location

Tue, 2 Feb 2013

New marketing and technical support center opened in Reading, UK.


eMemory’s eNVM SIPs reach 5 million wafer production record

Wed, 3 Mar 2013
eMemory announced today that the accumulated number of customers’ wafers incorporating eMemory’s eNVM SIPs have now surpassed 5 million production mark.

Fab Spending Forecast: Equipment spending is expected to remain flat in 2013

Wed, 3 Mar 2013

Fab equipment spending for Front End facilities is expected to be flat in 2013, remaining around $31.7 billion, increasing to $39.3 billion in 2014 — a 24% increase.


EV Group to develop equipment to enable covalent bonds at room temperature

Tue, 3 Mar 2013

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today announced that it is developing equipment and process technology to enable covalent bonds at room temperature.


Peregrine Semiconductor to license its UltraCMOS design to Murata

Tue, 3 Mar 2013

Peregrine Semiconductor Corporation, a fabless provider of high-performance radio frequency integrated circuits (RFICs), yesterday announced plans to collaborate with Murata Manufacturing Company on a multisource arrangement for RF switches and other components based on Peregrine’s proprietary UltraCMOS technology


Flip-Chip expected to grow at a steady 9% pace, reaching $35 billion by 2018

Mon, 3 Mar 2013

Flip-Chip is big on value: in 2012, it was a $20B market, making it the biggest market in the middle-end area, and Yole Développement expects it to continue growing at a 9% clip, ultimately reaching $35 billion by 2018.


EV Group ships 300mm wafer bonding system to leading Chinese semiconductor foundry

Wed, 3 Mar 2013

Foundry to use wafers for 3D IC and advanced packaging volume production applications.


Signetics introduces an alternative to standard plastic ball grid array packages

Tue, 3 Mar 2013

Signetics Corporation today introduced their new MapBGA package to the industry. This alternative to standard PBGA packaging has improved reliability and design flexibility due to its unique assembly process.


India's efforts to appeal to semiconductor manufacturers

Thu, 2 Feb 2013

This week, India’s Finance Minister P Chidambaram offered incentives to chip makers to set up headquarters in India, in an effort to encourage local electronics manufacturing. However, the response from the industry has been less than positive. Many believe that is it is a good start, but far from sufficient.


AGC and nMode launch subsidiary to develop advanced packaging technology

Tue, 3 Mar 2013

Tokyo-based Asahi Glass Co., Ltd. and nMode Solutions Inc. of Tucson, Arizona, have invested $2.1 million to co-found a subsidiary business, Triton Micro Technologies , to develop via-fill technology for interposers, enabling next-generation semiconductor packaging solutions using ultra-thin glass.


InnoLas Semiconductor on course for 450mm

Wed, 3 Mar 2013

Wafers with a diameter of 450mm enable the micro-chip industry an increase in yield of up to 80%. This leads to an enormous increase in productivity. In order to control the product quality, these wafers receive a specific marking from the manufacturer.


Ferrotec Temescal introduces electron beam metallization system

Wed, 4 Apr 2013

The Temescal Division of Ferrotec Corporation today announced the Temescal UEFC-5700, a ultra-high efficiency electron beam metallization system for lift-off compound semiconductor applications.


PCB growth rate to slow to 2.7% in 2013

Fri, 3 Mar 2013

In 2012, global PCB industry saw a jump in terms of output value, benefitting in a large part from the rapid growth in the shipment of Apple and Samsung. However, there is no such possibility of a huge jump in 2013, as the report states the expected growth rate will slow down to 2.7%.


OneChip announces partnerships and plans to expand into the DCI and PON markets

Fri, 3 Mar 2013

OneChip Photonics this week revealed strategic, outsourcing plans to expand into new markets, with announcements of newly-established relationships with semiconductor foundry GCS and wafer supplier IQE. Both announcements related to OneChip’s bigger, strategic plan to expand its services into the high-volume DCI market.


GLOBALFOUNDRIES demonstrates 3D TSV capabilities on 20nm technology

Tue, 4 Apr 2013

GLOBALFOUNDRIES today announced the accomplishment of a key milestone in its strategy to enable 3D stacking of chips for next-generation mobile and consumer applications.


AMAT-conductor-etch-system-debut

Mon, 11 Nov 2010

Applied Materials (AMAT) speaks about its new conductor etch system -- the Centris AdvantEdge Mesa Etch -- released at SEMICON Japan this week. The company sees the gap in the lithography roadmap is an etch opportunity. Thorsten Lill, VP Etch Business Group, at Applied, told ElectroIQ that new steps in advanced transistors, double-patterning, and advanced packaging are driving growth in the conductor etch market (~$1.6B market in 2010).


Playing the field: Qualcomm embraces GlobalFoundries, reups with TSMC

Fri, 1 Jan 2010

Fabless giant Qualcomm has made two deals to reserve leading-edge semiconductor manufacturing capacity: one with longtime partner TSMC, and the other with upstart GlobalFoundries.


Thin wafer handling: Analysis of wafer-support tooling for stencil-print coating of thinned wafers

Mon, 9 Sep 2010

Jeff Schake, et al, DEK Printing Machines, discuss the flatness characteristics of available wafer pallets, and use them in an experiment with thinned wafers in automated printing. With thin wafers, and the requirement for low coating thickness, the wafer-support tooling surface metrology should have an appreciable impact on coating thickness control.Jeff Schake, et al, DEK Printing Machines, discuss the flatness characteristics of available wafer pallets, and use them in an experiment with thinned wafers in automated printing. With thin wafers, and the requirement for low coating thickness, the wafer-support tooling surface metrology should have an appreciable impact on coating thickness control.


Research updates on EUV, mask, cleaning, etc from Leti

Fri, 7 Jul 2010

In these three video interviews from SEMICON West 2010, Leti research directors speak with senior technical editor Debra Vogler. Yannick Le Tiec discusses cleaning; Michel Brillouet speaks on 3D packaging work, and Didier Louis updates us on advanced lithography.


Analyst: Massive profits, but modest recovery

Mon, 3 Mar 2010

The semiconductor industry is at its most profitable point now than any other time in the past decade thanks to industrywide efforts to aggressively manage costs and capacity -- but wild optimism about surging growth forgets the truth that this recovery only resets to levels from three years ago, according to iSuppli.


Foundry-orders-Nanometrics-TSV-metrology-system

Fri, 12 Dec 2010

Nanometrics Incorporated (Nasdaq: NANO) announced that a leading semiconductor foundry has ordered a UniFire 7900 metrology system for advanced 3D wafer-scale packaging process control.


Low-k dielectric family introduced by SBA Materials

Tue, 9 Sep 2010

The IC community has been searching for a manufacturable low-k dielectric which could scale to below K = 2.0, says Dr. Phil Garrou. Microindent photos of uLK 124, released by SBA Materials show a clean ductile indent. SBA reports that their uLK materials can be integrated into existing fab lines using equipment and process flows already in place.The IC community has been searching for a manufacturable low-k dielectric which could scale to below K = 2.0, says Dr. Phil Garrou. Microindent photos of uLK 124, released by SBA Materials show a clean ductile indent. SBA reports that their uLK materials can be integrated into existing fab lines using equipment and process flows already in place.


LED, WLP, SiGe metrology challenges of today

Thu, 8 Aug 2011

LEDs, SiGe semiconductors, and WLP bumps each present their own challenges to metrology systems, says Alon Kapel, Jordan Valley Semiconductor.


Imec ITF: Reduce LEDs costs 10x, says Philips Lumileds

Tue, 5 May 2011

In an exclusive series of blogs, imec reports from its International Technology Forum (ITF) last week in Brussels. Els Parton, science editor, imec, shares Jy Bhardwaj's (Philips Lumileds) points about LEDs costs improvements.


SEMICON West keynotes cover research, chip design, packaging

Tue, 6 Jun 2011

Tien Wu, ASE; Rama K. Shukla, Intel; and Luc Van den hove, imec, are the honored presenters for SEMICON West 2011.


Diodes keeps MOSFETs cool with new package

Thu, 12 Dec 2011

Diodes Incorporated (Nasdaq:DIOD) began packaging MOSFETs in the miniature DFN1212-3 package for cooler operation than the equivalent-footprint SOT723 package.


DAC seeks speakers bureau experts

Wed, 11 Nov 2011

The Design Automation Conference (DAC) is soliciting semiconductor industry experts for participation in invited sessions, panels, and other events at the 49th DAC, June 3-7, 2012 in San Francisco, CA.


SMC 2011: Materials projections, and China as an island

Tue, 1 Jan 2011

The final day of SEMI's Strategic Materials Conference (SMC) dug deeper into rare earth elements supplies, deposition precursors, projections for semiconductor packaging materials and fab equipment, and a geopolitical perspective on relevant markets, reports Techcet's Michael A. Fury.


Tessera focuses on semiconductor technologies beyond packaging

Thu, 4 Apr 2011

Tessera Technologies Inc. (Nasdaq:TSRA - News) began two corporate initiatives to expand its technologies in semiconductor microelectronics beyond packaging, and to potentially separate its Imaging & Optics business.


3D IC is only solution for scaling "up," says MonolithIC 3D exec

Thu, 3 Mar 2011

Transfer on top of processed wafer and replace gates (<400°C)Zvi Or-Bach, MonolithIC 3D, describes the TSV-beating monolithic IC fab process, and argues for scaling "up" rather than down. Or-Bach compares the costs of further semiconductor scaling to advanced packaging.


Intel honors 28 top suppliers, "achievers"

Wed, 4 Apr 2011

Twenty-eight companies get the nod from Intel's latest supplier awards, including four "Achievement" award winners.


ASICs and FPGAs could take a lesson from autos, says Xilinx

Thu, 5 May 2011

Ivo Bolsens, Xilinx, compares crossover cars -- sports car performance with station wagon utility -- to semiconductor ASICs (high-performance) and FPGAs (flexible, easy to use, less NRE). The semiconductor industry needs a programmable platform that has ASICs' capabilities.


IEDM Reflections, last day: Novel process technologies

Tue, 1 Jan 2011

Michael A. Fury of Techcet blogs about the papers he saw at IEDM 2010. The final afternoon continued with 4 parallel sessions and the halls and conference rooms were as crowded as they had been all week. I was compelled to spend nearly all of my time in the novel process technologies session.


Tackling the rising cost-of-test for semiconductor devices

Tue, 3 Mar 2011
Kenneth A Ramsey, Executive Vice President, MCT Worldwide, LLC, Minneapolis, MN USA

ISSI-spins-off-Giantec-Semiconductor

Tue, 1 Jan 2011

Integrated Silicon Solution Inc. (Nasdaq: ISSI) completed the spin-off of its subsidiary, Giantec Semiconductor Inc., which focuses on the ASSP business that includes EEPROM and SmartCard products.


SEMI: Chip materials topped records in 2010

Tue, 3 Mar 2011

Sales of semiconductor materials rose 25% in 2010 to a new record $43.55B thanks to surging device shipments, according to final tallies from SEMI.


Intel gives nod to 48 top suppliers

Mon, 3 Mar 2008
March 17, 2008 - Intel has given a nod to four dozen of its key suppliers from its roster of thousands of supply-chain partners, ranging from capital equipment manufacturers to materials, components, and service providers, as the 2007 winners of its awards for Preferred Quality Supplier (PQS) and Supplier Continuous Quality Improvement (SCQI).

KLA-Tencor scoops up ICOS for backend, LCD/solar play

Thu, 2 Feb 2008
Feb. 21, 2008 - The latest move in metrology industry consolidation has occurred with KLA-Tencor's proposed "friendly" acquisition of Belgium firm ICOS Vision Systems in a proposed €316.9M (US $465.8M) cash transaction.

Unisem, Flip-Chip ink WLP licensing deal

Tue, 6 Jun 2008
June 16, 2008 - Unisem Berhad and subsidiary Unisem-Advantpack Technologies (UAT) have agreed to license FlipChip International's wafer bumping and wafer-level packaging technologies, in exchange for a stake in UAT. The deal is seen as expanding Unisem's technology offerings, while broadening FlipChip's customer reach.

Ziptronix joins low-cost quest for true 3D-IC

Wed, 10 Oct 2008
Ziptronix execs reveal technical details on its direct bond interconnect technology, which the company says is key to low-cost wafer-to-wafer or chip-to-wafer bonding without high-temperature compression.

Suss swaps CEO over "differing" strategic views

Tue, 10 Oct 2008
Suss MicroTec has replaced board member and CEO Stefan Schneidewind with Christian Schubert effective immediately, citing "differing views regarding the future strategy of the company." A search for a new permanent CEO will take place.

SEMI Europe aims to increase region's competitiveness

Thu, 10 Oct 2008
In a keynote speech at SEMICON Europa, SEMI Europe president Heinz Kundert presented highlights from a paper urging renewed efforts to increase Europe's microelectronic industry competitiveness, highlighting increased R&D funding, cultivating the workforce, and protecting and enforcing IP.

Navigating the coming flood of used 200mm tools

Fri, 1 Jan 2008
Market analysts are projecting an imminent surge of 200mm wafer processing tools swamping the market, valued in billions of dollars each year through 2012. It seems clear that an extra 100 fabs will be for sale over the next few years, with MEMS and advanced packaging lines likely snapping up this extra manufacturing capacity -- but watch out if a used 200mm tool flood washes over into mainstream CMOS.

Rudolph snaps up RVSI assets to grow AP presence

Thu, 1 Jan 2008
Jan. 24, 2008 - Rudolph Technologies has acquired all IP and selected assets from privately held RVSI Inspection in Hauppauge, NY, in a move to add the firm's flagship 3D wafer inspection to its own 2D macrodefect inspection technologies, and strengthen its presence in advanced packaging applications.

SEMI: 500K jobs at risk with EU chip decline

Thu, 12 Dec 2008
In a pre-emptive measure to avert an increase in unemployment throughout Europe, SEMI is appealing to EU and national policymakers to invest in Europe's semiconductor industry, citing its importance to the health and global competitiveness of the EU economy.

siXis partners with SVTC to commercialize silicon circuit boards

Mon, 8 Aug 2009
August 24, 2009 -- SVTC was chosen by technology startup siXis, Inc. to supply silicon manufacturing services for their compact, high-speed embedded computing modules that bridge the gap between programmable devices and costly, customized semiconductors.

Commercializing a WLCSP passivation layer solution

Mon, 8 Aug 2009
Lord Corp. exec Russell Stapleton talks with SST about the company's first-generation passivation layer solution for wafer-level chipscale packaging, due to launch in 1Q10.

Nemotek Technologie sizes up its future in wafer-level cameras

Tue, 9 Sep 2009
Jacky Perdrigeat, CEO of Nemotek Technologie, discusses the company's technology and business strategy, as it opens a new logistics center in Hong Kong with electronics component distributor Anglia.

Memory sector upended, driven by 3D packaging tech, says Yole

Fri, 5 May 2009
New integration trends and disruptive packaging technologies, notably 3D TSVs, will cause major technical changes in the memory semiconductor sector, but ultimately pave the way for future growth, according to a recent report from Yole Développement.

Intel gives nod to 40 top suppliers

Wed, 3 Mar 2009
Intel has handed out its annual Preferred Quality Supplier (PQS) and Supplier Continuous Quality Improvement (SCQI) awards to more than three dozen of its key suppliers from its roster of thousands of supply-chain partners, ranging from capital equipment manufacturers to materials, components, and service providers.

EV, Brewer system targets ultrathin wafer handling

Wed, 7 Jul 2006
July 19, 2006 - Austria's EV Group and US-based Brewer Science Inc. say they are codeveloping a temporary wafer-bonding system for handling ultrathin wafers, designed to allow high-temperature advanced packaging processes followed by quick debonding.

Freescale touts "breakthrough" packaging replacement for BGA, flip-chip

Tue, 7 Jul 2006
July 25, 2006 - Freescale Semiconductor says it has developed a new "redistributed chip packaging" technology that could replace ball grid array (BGA) and flip-chip for packaging and assembly, and claims to have already fabricated a device targeting use in mobile phones.

SST's Haavind wins Gold at ASBPE awards

Fri, 8 Aug 2006
August 4, 2006 - Solid State Technology editorial director Bob Haavind has won a gold national award from the American Society of Business Publication Editors (ASBPE), for two of his editorials in SST's September and November 2005 issues, addressing topics in education and government.

Flextronics adds Tessera's WLP for camera modules

Thu, 9 Sep 2006
September 7, 2006 - Flextronics International Ltd., an electronics manufacturing services (EMS) provider and the world's largest manufacturer of camera modules, has signed a deal with Tessera Technologies Inc. to incorporate wafer-level packaging technology in its entire camera module line.

Kulicke & Soffa snaps up die bonder supplier Alphasem

Thu, 10 Oct 2006
October 12, 2006 - Kulicke & Soffa Industries Inc. says it is entering the die bonder market with an agreed-upon $30 million acquisition of equipment supplier Alphasem, a subsidiary of Dover Technologies International Inc.

TAP partner Amkor joins IBM/Chartered/Samsung alliance

Tue, 9 Sep 2006
September 26, 2006 - The chipmaking manufacturing alliance led by IBM, Chartered Semiconductor Manufacturing, and Samsung Electronics Co. Ltd. has added another supplier to their roster. Amkor Technology Inc. is collaborating with the group to qualify 90nm and 65nm flip-chip packaging and design capabilities for the group's "Common Platform," and has begun 45nm qualifications for next-generation semiconductor applications.

SEMI tips details about SEMICON West backend pavilion

Mon, 5 May 2006
May 8, 2006 - SEMI has announced additional details about its backend technology-themed content pavilion at this year's SEMICON West, developed in conjunction with leading industry associations and companies including FSA, the International Electronic Manufacturing Initiative (iNEMI), the Microelectronics Packaging and Test Engineering Council (MEPTEC), and TechSearch International.

Report: Taiwan relaxing chip packaging export restrictions to China

Thu, 4 Apr 2006
April 27, 2006 - Taiwan reportedly has removed restrictions on export of low-end semiconductor packaging and testing technology toChina, perhaps signaling a rethinking of broader restrictions on semiconductor manufacturing technology transfers to the mainland.

ASE gains $247M in facility fire settlement

Wed, 6 Jun 2006
June 28, 2006 - Semiconductor packaging service provider Advanced Semiconductor Engineering Inc. has reached a final settlement with nine insurance companies regarding a fire at its facilities in Chung-Li in May 2005.

Wafer-level packaging in the 3D present

Tue, 11 Nov 2006
Wafer-level packaging (WLP) may finally reach the mainstream for ICs, according to industry vendors and analysts at the 3rd annual International Wafer-Level Packaging Conference (Nov. 1-3 in San Jose, CA). Packaging leader Amkor showed that this technology will soon be applicable to ~85% of all ICs by unit volume, and should see market growth of 25% CAGR over the next five years. Analysts presented details of the markets and applications driving this slow revolution in mainstream packaging.

Intel gives nod to top suppliers

Wed, 3 Mar 2006
March 22, 2006 - Intel Corp. has handed out its annual awards to more than three dozen suppliers from its roster of thousands of supply-chain partners, ranging from capital equipment manufacturers to materials, components, and service providers.

Japan firm boosting packaging output

Fri, 4 Apr 2006
April 21, 2006 - Ibiden Co. reportedly plans to invest 8.5 billion yen (about US $72 million) to build a new semiconductor packaging facility in Ogaki, Gifu Prefecture, to tap demand for chip packaging used in PCs and mobile phones.

PennWell names David Barach group publisher of Solid State Technology and Advanced Packaging

Thu, 2 Feb 2006
February 9, 2006 -- PennWell Corporation has named veteran publisher David Barach to the position of group publisher of Solid State Technology and Advanced Packaging Packaging magazines, effective February 1.

NEC touts new optical nanoprobe

Wed, 2 Feb 2006
February 22, 2006 - NEC Corp. has developed what it claims is the world's smallest fiber-optic electric field probe, to be used for evaluating electrical characteristics inside high-density LSI packages.

Honeywell debuts flexible phase-change material

Fri, 3 Mar 2006
March 17, 2006 - Honeywell Electronic Materials has developed a new screen printable phase-change material to give chipmakers more flexibility in applying the heat-conducting materials during the semiconductor packaging process.

Samsung develops DRAM stack with TSVs

Mon, 4 Apr 2007
April 23, 2007 - Samsung Electronics Co., Ltd., has developed an all-DRAM stacked-memory package using through-silicon vias (TSVs) housed in aluminum pads to avoid performance slow-downs caused by the redistribution layer.

Gartner: Backend chip services surged 26% in 2006

Mon, 2 Feb 2007
February 26, 2007 - Worldwide sales of semiconductor assembly and test services (SATS) marked the fifth consecutive year of double-digit growth in 2006, due to accelerated transition to and integration with new packaging technologies, according to data from Gartner Dataquest.

Honeywell expanding packaging center

Fri, 2 Feb 2007
February 16, 2007 - Honeywell Electronic Materials, Tempe, AZ, says it will invest >$1 million to expand its advanced packaging materials R&D center in Spokane, WA.

Getter services for MEMS WLP

Mon, 4 Apr 2007
April 23, 2007 - Innovative Micro Technology has begun offering getter deposition services of wafer-level packaging (WLP) of MEMS devices and other components requiring a hard vacuum, saying it has demonstrated vacuum levels below 10 mTorr for inorganic devices, equal to or better than industry standard.

Ultratech shareholder demands sale

Tue, 1 Jan 2007
January 16, 2007 - Thales Fund Management, claiming to be the largest shareholder in San Jose, CA-based photolithography toolmaker Ultratech Inc., is seeking a sale of the company, saying growth prospects can be better monetized as part of a larger organization.

IBM, SUSS ramp C4NP pilot line

Fri, 7 Jul 2007
July 20, 2007 - IBM is now ramping pilot production of its first controlled collapse chip connection new process (C4NP) production line in East Fishkill, NY, just over a year after completing initial reliability testing for 300mm C4NP solder-bumped wafers.

Amkor, IMEC sign agreement for 3D WLP

Wed, 7 Jul 2007
July 18, 2007 - At SEMICON West, Amkor Technology Inc., a provider of advanced semiconductor assembly and test services, and IMEC, the independent nanoelectronics and nanotechnology research center based in Belgium, announced that they have entered into a 2-year collaboration agreement. They will develop cost-effective, 3D integration technology based on wafer-level processing techniques.

Materials establishing firm foothold in advanced packaging

Thu, 7 Jul 2007
At Wednesday's (July 18) Packaging Materials Trends TechXPOT, sponsored by IMAPS, industry experts shared insights and developments in packaging materials and applications, and how innovations will help device packaging address functionality, form factor, and reliability challenges.

SEMICON WEST REPORT: Interconnect symposium heralds exciting year

Wed, 7 Jul 2007
Participants in Tuesday's Interconnect Symposium hosted by Kulicke & Soffa and Advanced Packaging magazine, examined a list of trends, challenges, and opportunities in advanced packaging (e.g., wire-bonding and flip-chips) that are being thrust into the semiconductor manufacturing spotlight. "If you're an advanced packaging engineer, you're finally getting the recognition you deserve," noted TechSearch International president E. Jan Vardemann.

SEZ: Single-wafer cleaning gaining favor in BEOL

Wed, 7 Jul 2007
Cleaning wafers for flip-chip applications represents a growing area for Zurich, Switzerland-based SEZ, says Kurt Lachenbucher, executive VP and CEO. Though it's a niche market, it is an increasingly important area (~20% growth regularly), he explained. At the 45nm and 32nm technology nodes, particle issues become so critical that single-wafer cleaning can improve semiconductor yields. Cleaning can damage the wafer surface; therefore, methods that prevent damage grow in importance.

SUSS spins off device bonder unit

Fri, 7 Jul 2007
July 27, 2007 - SUSS MicroTec has carved out its device bonder division through a management buyout initiated by SUSS France president Gael Schmidt, in order to gain independence from the parent company which has little strategic synergies.

Vistec combines litho groups

Thu, 7 Jul 2007
July 18, 2007 - Vistec Semiconductor Systems says it will combine its electron beam and lithography business groups in order to "better meet customers' requirements and improve synergy across the organization."

Test startup decloaks with "virtual probe" for SiPs

Mon, 7 Jul 2007
July 16, 2007 - Scanimetrics Inc. has debuted at SEMICON West with its first product targeting the test sector: a noncontact "virtual probe" technology for system-in-package testing during assembly that it claims can cut manufacturing costs in half.

ASMI ramps production with AIT's SiP

Mon, 1 Jan 2007
January 29, 2007 - AMI Semiconductor is in full production mode with Advanced Interconnect Technologies' (AIT) stacked-die quad flat package no leads (QFN) modules, which AMI will incorporate into several consumer electronics applications, the companies said today.

PACKAGING BEAT: Substrates, thin packaging highlight ITRS changes

Tue, 1 Jan 2007
A minor update to the International Technology Roadmap for Semiconductors was released in December, before next year's full ITRS revision. An examination of the new content in the assembly and packaging chapter illuminates concerns about package substrates keeping up with advances in silicon technology, as well as a variety of challenges in thinned-die packaging.

Dealing with silicon-package interactions

Wed, 5 May 2007
Chip design, foundry/fab, and packaging partners must work in concert to reduce risk on new technology offerings, according to Mike Barrow, SVP, flip chip technologies, Amkor. Giving the packaging group early access to advanced silicon can result in chip and package interaction (CPI) solutions that are market-ready upon silicon node release. Further, package and laminate design are in the critical path, and need to be co-designed with the silicon to deliver cost-effective solutions.

MagnaChip: "CUP" structure cuts chip size by 30%

Thu, 6 Jun 2007
June 21, 2007

IBM tips integrated packaging in blazing optical transceiver chipset

Mon, 3 Mar 2007
March 26, 2007 - IBM says it has developed a prototype optical transceiver chipset for supercomputing applications that incorporates optical and CMOS components in one system-in-package (SiP).

IMEC signs frame agreement with Flemish government

Mon, 3 Mar 2007
March 12, 2007 - IMEC, the independent research center based in Belgium, has announced that the Flemish Minister of Science and Innovation, Fientje Moerman, signed a new frame agreement between IMEC and the Government of Flanders for the period 2007-2011.

Emerging MEMS manufacturers look beyond auto apps

Wed, 9 Sep 2007
September 12, 2007 - MEMS revenue will double from $5B in 2005 to $10B in 2011, with a "select group of large, well-established MEMS suppliers" benefiting from growth in the automotive sector, and "new, emerging entrants" to the MEMS market capitalizing on opportunities in consumer, communications, and portable end-product sectors, according to Semiconductor Partners.

TSMC approves 300mm WLP packaging plan, 0.18-micron upgrade

Wed, 8 Aug 2007
August 15, 2007 - TSMC board members have given their approval to a pair of proposals targeting capacity investments for 300mm wafer-level packaging and an upgrade to its 200mm/0.18-micron logic process.

Singapore firm launches $1.6B buyout of Stats ChipPAC

Thu, 3 Mar 2007
March 1, 2007 - Singapore Technologies Semiconductors Pte. Ltd. (STS), a subsidiary of state-owned holding firm Temasek Holdings Ltd., has filed a $1.6 billion cash offer to acquire full ownership in backend services firm Stats ChipPAC.

QLP adds manufacturing site in CA

Thu, 8 Aug 2007
August 23, 2007

Surfect launches wafer-bumping service

Thu, 8 Aug 2007
August 23, 2007 -- Surfect Technologies says it has launched a wafer bumping service program utilizing its single-cell electroplating process for 200mm and 300mm IC manufacturers and OEMs performing low-volume production, preliminary wafer-level packaging, R&D, or new product introduction (NPI), or evaluating wafer-bumping systems.

TDI ramps InGaN substrates for LEDs

Mon, 8 Aug 2007
August 17, 2007 - Technologies and Devices International Inc. (TDI) says it is now producing indium-gallium-nitride (InGaN) substrates for packaging GaN-based high-brightness LEDs and blue and green laser diodes, targeting volume production for early 2008.

Tracking growth in PAT, and the rise of outsourcing

Tue, 9 Sep 2007
Global packaging and testing (PAT) revenues are expected to grow at half the rate in 2007 that they did in 2006, and will improve marginally in 2008, according to new data from Gartner Dataquest. A closer look inside the numbers reveals the emergence of outsourced semiconductor assembly and test services (SATS), which is poised to balloon by nearly a third over the next three years and reach equal footing with IDMs.

"CATRENE" program to lead EU micro/nano R&D beyond 2008

Tue, 10 Oct 2007
October 30, 2007 - A new public/private R&D initiative is being laid out to replace the MEDEA+ program for cooperative R&D in microelectronics that is set to expire in 2008, which over the past seven years has watched over three generations of CMOS technology, and spearheaded work on fields ranging from smart cards, image sensors, and automotive electronics.

Cookson expands India R&D center

Fri, 10 Oct 2007
October 12, 2007 - Cookson Electronics is finalizing a three-year expansion of its India Research Center, moving to a 32,000-sq.ft. facility in Bangalore where it will focus on semiconductor manufacturing and packaging technologies as well as solar technologies.

Semicon Europa sneak peek: Tracking Europe's present, future in PV, R&D, TAP, MEMS

Tue, 10 Oct 2007
After bouncing around on the calendar and in venue, Semicon Europa, formerly a springtime event in Munich, Germany, is ready to open its doors next week in Stuttgart (conveniently at the same time as Germany's second-biggest beer festival, Cannstatter Volksfest...complete with multistory fruit tower). Here follows a quick scan of highlights from Europa's program schedule, and sessions you'll want to bookmark.

Toshiba licenses Tessera's image-enhancement tech

Mon, 12 Dec 2007
December 3, 2007 - Tessera Technologies says it has licensed its OptiML Focus image-enhancement technology to Toshiba, for use in camera modules for next-generation mobile phones and PDAs.

Report from IMAPS: Biomedical devices present unique challenges, opportunities

Tue, 11 Nov 2007
The Body Worlds exhibit at The Tech Innovation Museum, where real cadavers are preserved to expose the makeup of the human body, provided a fitting backdrop to a half-day session on "Biomedical Materials, Devices, and Packaging" at IMAPS 2007, the International Microelectronics And Packaging Society's 40th annual international symposium on microelectronics.

CEA-Leti, SET develop new bonder

Thu, 11 Nov 2007
November 15, 2007 - SET, the former SUSS MicroTec device bonder division spun off earlier this year, says that a partnership with CEA Leti has resulted in a new high-accuracy (0.5-micron), high-force (4000 N) device bonder for processing up to 300mm wafers.

Infineon, ASE tip new "eWLB" chip package

Mon, 11 Nov 2007
November 12, 2007 - Infineon Technologies says it has developed a new packaging technology in collaboration with Advanced Semiconductor Engineering Inc. (ASE) that offers "an almost infinite number of contact elements" in a 30% smaller package form vs. conventional lead-frame laminate packages.

MEMS, packaging groups to support others' efforts

Mon, 11 Nov 2007
November 19, 2007 - The MEMS Industry Group, a trade association representing MEMS and microstructure industries, and the MicroElectronics Packaging and Test Engineering Council (MEPTEC) have formed a strategic alliance to support each other's goals and industry events, through a variety of marketing programs.

Infineon, Parlex to form JV company for advanced substrates

Thu, 12 Dec 2004
December 30, 2004 - Parlex Corp. and Infineon Technologies AG have agreed to establish a joint venture company to manufacture and sell advanced technology substrates for secure mobile electronic identification products, said Parlex officials earlier this week. The joint venture will be headquartered in Hong Kong with manufacturing facilities in China.

Amkor, SECAP 300mm electroplated solder bumping line reaches volume production

Thu, 11 Nov 2004
November 11, 2004 - Amkor Technology Inc., its Unitive subsidiaries, and the Semiconductor Equipment Consortium for Advanced Packaging (SECAP) have established a high-volume 300mm electroplated solder bumping line, according to SECAP. The line, which was set up in 2003 at Unitive Semiconductor Taiwan (UST), located in Hsinchu, Taiwan, has reached volume production.

K&S selling flip chip biz

Mon, 2 Feb 2004
February 9, 2004 - Kulicke & Soffa Industries Inc., Willow Grove, PA, said it has sold its flip-chip business to FlipChip International LLC for $3.4 million in cash and liabilities.

Tessera, Oki sign packaging deal

Mon, 1 Jan 2004
January 26, 2004 - Oki Electric Industry Co. Ltd. has licensed semiconductor packaging technology from Tessera Technologies, San Jose, CA, for use in devices including microcontrollers and ASICs.

Amkor to buy Unitive in backend deal

Wed, 7 Jul 2004
July 21, 2004 - Amkor Technology Inc., Chandler, AZ, has agreed to acquire Unitive Inc., Research Triangle Park, NC, for $48 million, gaining technology and capacity for 300mm electroplated wafer bumping, lead-free wafer bumping and wafer-level packaging, and bump/probe assembly and test capabilities in Taiwan and the US.

Amkor and IBM ink long-term test and assembly agreement

Tue, 5 May 2004
May 17, 2004 -- Amkor Technology Inc. has entered into a strategic long-term agreement with IBM for semiconductor assembly and test services. Some of the details include Amkor acquiring IBM's manufacturing complex in Shanghai, China, and its Singapore test operations.

IBM and SUSS agree to develop lead-free packaging technique

Mon, 9 Sep 2004
September 13, 2004 - IBM and SUSS MicroTec AG have signed an agreement to develop and commercialize IBM's next-generation, 100% lead-free semiconductor packaging technology.

Advanced Semiconductor Engineering reports fire accident at Chungli facility

Mon, 5 May 2005
May 2, 2005 - Advanced Semiconductor Engineering Inc. yesterday reported a fire at its semiconductor packaging and testing facilities in Chungli, Taiwan, which caused damage and injuries, but no deaths. The fire broke out at one of ASE's production buildings at approximately 2 pm following what it suspects was a boiler explosion on the ground floor of the 11-story building. The fire was contained by firefighters within two hours.

SECAP disbands after successfully achieving goal

Tue, 6 Jun 2005
June 21, 2005 - The Semiconductor Equipment Consortium for Advanced Packaging (SECAP) has announced that it will disband now that the consortium has successfully established 300mm wafer-level packaging as a functional technology, and full-volume production on the first installed wafer-bumping line is underway.

Renesas, Casio to collaborate on device packaging technology

Wed, 1 Jan 2005
January 19, 2005 - Casio Computer Co. Ltd. and Renesas Technology Corp. have agreed to an arrangement whereby Casio will license its wafer level package (WLP) semiconductor device packaging technology to Renesas. The agreement marks the first time Casio has made its WLP technology available to another Japanese semiconductor device manufacturer.

IMEC develops high-performance 90nm CMOS platform for RF applications

Mon, 7 Jul 2005
July 25, 2005 - IMEC has developed a 90nm low-cost RF-CMOS platform targeting applications in the 5-24GHz range, according to IMEC's July newsletter on this paper, which was presented at the 2005 VLSI Conference.

Increased co-design needed to advance electronics miniaturization

Fri, 7 Jul 2005
July 22, 2005 - Semiconductor industry leaders gathered last week at the 2005 Electronic Product Miniaturization Symposium in San Francisco to share ideas and explore new technologies for designing next-generation electronic products. A number of innovative miniaturization and integration technologies, such as smart industrial design, semiconductor design tools, semiconductor packaging, and thermal analysis were explored.

Tessera partners with U. of Alaska and North Dakota U. to develop microelectronics centers

Thu, 8 Aug 2005
Aug. 18, 2005 - Tessera Technologies Inc. has transferred its MicroBGA chip-scale packaging technology to the University of Alaska Fairbanks and to North Dakota State University. This licensing and transfer of technology is a part of the development of an advanced technology center on both campuses.

Feinfocus joins forces with Innov-X for analysis products

Wed, 8 Aug 2005
August 10, 2005 - Feinfocus, a Comet business unit and manufacturer of x-ray inspection systems, has entered into a technology alliance with Innov-X Systems, a Woburn, MA manufacturer of high-performance, portable x-ray fluorescence analyzers.

Phoenix Precision, Intel co-establish new-generation flip chip line

Mon, 6 Jun 2002
June 10, 2002 - Taipei, Taiwan - Packaging-substrate maker Phoenix Precision Technology Corp. of Taiwan will team up with Intel Corp. to set up an NT$4 billion (US$117.64 million) line to make 3G flip-chip substrates.

NEXX Systems joins SECAP

Tue, 7 Jul 2002
July 2, 2002 - Munich, Germany - NEXX Systems, a spin-off of ASTeX established in August 2001, and a supplier of PVD systems, has joined the Semiconductor Equipment Consortium for Advanced Packaging (SECAP).

Last years IPOs - where are they now?

Tue, 4 Apr 2002
It seems that the semiconductor IPO well has begun to run dry, at least for the time being. It has been months since a chip-related company has filed for its initial public offering. And yet, if one looks at companies that went IPO during late 2000 into 2001, it seems that the public market has been kind to them.

ChipPAC to more than double capacity in China

Wed, 8 Aug 2002
Fremont, CA - ChipPAC Inc., a provider of semiconductor assembly and test services, plans to more than double its manufacturing capacity in China.

Fairchild Semi opens packaging design center in Korea

Wed, 9 Sep 2002
Sept. 18, 2002 - South Portland, ME - Fairchild Semiconductor, a global supplier of high performance power products for multiple end markets, has opened a Package and Technology Knowledge Center in Bucheon, South Korea.

Nanotechnology: Still too early for tool industry's attention?

Mon, 7 Jul 2002
RAVE LLC CEO Barry Hopkins attended the NanoBusiness Spring 2002 conference in hopes of discovering the next generation of customers and applications for his company's photomask-repair tools - hopefully customers in the emerging field of nanotechnology, which could possibly run counter-cyclical to the chip industry's peaks and valleys.

Motorola Malaysia to invest some $65.9M on plant expansion

Fri, 7 Jul 2002
Kuala Lumpur - Motorola Malaysia Sdn. Bhd. will invest some $65.9 million (250 million ringgit) to expand the capacity of its semiconductor plant and on the transfer of technology, which will see the creation of 500 new jobs.

BOC acquires Hydromatix

Fri, 1 Jan 2002
Jan. 25, 2002 - Wilmington, MA - BOC Edwards, a supplier of chemical and exhaust gas management systems for the microelectronics industry, announced that it has acquired 100% of Hydromatix Inc., a manufacturer of high-efficiency, process-critical liquid purification systems based in Santa Fe Springs, CA.

ASE plans to expand its Bluetooth business

Mon, 2 Feb 2002
Feb.25, 2002 - Kaohsiung, Taiwan - Semiconductor packaging and testing company, Advanced Semiconductor Engineering Inc. (ASE), said that its Taiwanese facilities will take a strategic role in Bluetooth's development.

K&S to cut 200 jobs; expand China ops

Mon, 2 Feb 2002
Feb. 4, 2002 - Willow Grove, PA - Kulicke & Soffa Industries Inc. is set to cut 200 jobs, and restructure its organization.

Is the advanced packaging town big enough?

Mon, 2 Feb 2002
It's a testament to the growing importance of advanced packaging technology that two consortiums have sprung up in the past year and a half to lend some corporate organization to the sector - the Semiconductor Equipment Consortium for Advanced Packaging (SECAP) and the Advanced Packaging and Interconnect Alliance (APiA).

Shipley Co., Numerical partnership for low K1 lithography imaging

Fri, 11 Nov 2002
Nov. 1, 2002 - Marlborough, MA - Shipley Company L.L.C., a provider of electronic materials and process innovations for advanced circuit board technology, semiconductor manufacturing, and advanced packaging, has established a partnership for low k1 lithography imaging with Silicon Valley-based Numerical Technologies Inc.

K&S considers future of non-core operations

Tue, 11 Nov 2002
Nov. 5, 2002 - Willow Grove, PA - Kulicke & Soffa Industries, the supplier of semiconductor assembly and test interconnect equipment, materials and technology, has announced that it is exploring options for certain of its non-core business units.

Tessera, Hitachi expand agreement

Thu, 10 Oct 2002
Oct. 17, 2002 - San Jose, CA -- Tessera Technologies Inc., a provider of chip-scale and multi-chip packaging solutions, has expanded the scope of an existing licensing agreement with Hitachi Ltd.

STATS qualifies 300mm capabilities

Tue, 2 Feb 2003
Feb. 11, 2003 - Singapore, and Milpitas, CA - ST Assembly Test Services Ltd. (STATS), an independent semiconductor test and advanced packaging service provider, has completed qualification of its frontend assembly operations for the packaging of high performance chips from 300mm wafers.

Average annual growth rate in wafer demand up38%, says FSA

Thu, 3 Mar 2003
March 6, 2003 - San Jose, CA - The Fabless Semiconductor Association (FSA), has announced the results of its annual "Wafer Supply & Demand and Packaging Survey", with analysis provided by Gartner Dataquest and conducted in conjunction with PricewaterhouseCoopers, LLP.

Stepper suppliers hit skids in 2002

Tue, 7 Jul 2003
July 8, 2003 - IC stepper suppliers fell victim to the same market downswing as the rest of the industry in 2002, according to new research from VLSI.

ASAT moves US offices

Thu, 10 Oct 2003
September 25, 2003 - Semiconductor packaging and test firm ASAT Holdings Ltd. has relocated its US headquarters from Fremont, CA, to Pleasanton, CA.

New flip-chip company created

Thu, 8 Aug 2003
August 5, 2005 - Polymer Assembly Technology, Billerica, MA, has opened up shop to offer flip-chip technology using polymer conductive adhesives. Founder and president Jim Clayton is the former director of R&D at Polymer Flip Chip Corp.

IBM Plans Chip Facility in China

Fri, 10 Oct 2000
Shanghai, China--Oct. 27, 2000--IBM Corp. plans to invest $300 million to build a chip packaging manufacturing facility in Shanghai, China to support the company's growing semiconductor business around the world.

STATS Offers Lead-Free IC Packaging Solution

Tue, 10 Oct 2000
Singapore--Oct. 24, 2000--As part of a lead-free initiative, ST Assembly Test Services (STATS), an independent semiconductor testing and advanced packaging service provider, has selected a pure tin solder alternative solution for its leaded product offering.

Amkor Expands Prototype Development Lab

Thu, 10 Oct 2000
Chandler, Arizona--Oct. 19, 2000--In response to increased focus on advanced flip chip and system-in-package production, Amkor Technology--a worldwide provider of contract microelectronics manufacturing services--has added the latest equipment from several manufacturers to its expanding prototype package development lab.

Ultratech Stepper introduces stepper for flip-chip R&D

Wed, 11 Nov 2000
San Jose, California--Ultratech Stepper, Inc., a supplier of photolithography systems used to manufacture semiconductors, micromachined devices and thin film heads (TFH) for disk drives, today announced the introduction of the Prisma-ghi, a low-cost research and development (R&D) and pre-production flip-chip (bump) stepper.

STATS develops strip handler for multi-testing of ICs

Mon, 11 Nov 2000
Milpitas, California--Nov. 20, 2000--ST Assembly Test Services (STATS), a provider of semiconductor testing and advanced packaging services, has developed a strip handler for the multiple testing of integrated circuits (ICs).

STATS expecting flat Q4

Tue, 12 Dec 2000
Singapore--ST Assembly Test Services Ltd. (STATS) is now expecting fourth quarter (Q4) revenues to be flat compared to third quarter revenues of US$90.5 million, with diluted earnings per ADS of about $0.06 to $0.07. The revised expectation for revenues represents a reduction from the prior guidance of 8% to 10% sequential revenue growth, reports the company.

K&S Receives $15 Million Order from ChipPAC

Thu, 8 Aug 2000
New York -- August 29, 2000 --Kulicke & Soffa Industries Inc. said it received a $15 million order for its Model 8028 IC Ball Bonders from ChipPAC Inc.

Amkor, Toshiba Plan Japanese Packaging and Testing Venture

Mon, 8 Aug 2000
CHANDLER, Ariz.—Aug. 28, 2000—In a move to gain a strategic advantage in Japan, Amkor Technology Inc. today announced plans to create a joint semiconductor packaging and testing venture with Toshiba Corp.

Zuken USA Wins $1 Million Order from Medtronic

Wed, 8 Aug 2000
SANTA CLARA, Calif.--Aug. 23, 2000--Zuken USA is announcing an order valued at $1 million from medical electronics device manufacturer Medtronics for its CR-5000 Advanced Packaging solution.

STATS Adds Agilent's VLSI Test Platform

Fri, 6 Jun 2000
MILPITAS, CA--June 16, 2000--Test and advanced packaging service provider ST Assembly Test Services (STATS) has installed Agilent's 83000 VLSI test platform in its Test Development Center. The center is located in San Jose, Calif.

Companies Complete Flip Chip Technology Transfer

Thu, 8 Aug 2000
KAOHSIUNG, Taiwan--August 2, 2000--Advanced Semiconductor Engineering flip chip factory has received wafer bumping and redistribution technology from Kulicke & Soffa Industries and Flip Chip Technologies.

STATS Introduces Upgraded RF Test Capability

Tue, 8 Aug 2000
SINGAPORE and MILPITAS, Calif.--July 31, 2000--With demand rising for high-speed testing, independent semiconductor test and advanced packaging service provider ST Assembly Test Services (STATS) is expanding its RF test development and production testing capabilities to support frequencies up to 6 GHz.

Ultratech Named Exclusive Lithography Supplier by IEP/Casio

Tue, 7 Jul 2000
SEMICON West '00--July 11, 2000--Ultratech Stepper Inc. has been awarded exclusive supplier status by IEP/Casio (Integrated Electronics & Packaging Technologies Inc.).

ASE launches volume production of wafer-level chip scale packages

Thu, 10 Oct 2001
October 11, 2001 - Santa Clara, CA - Advanced Semiconductor Engineering Inc., a semiconductor packaging and testing company, will launch volume production of wafer-level chip scale packages (CSP) this quarter, ramping up to 2.4 million chips/month.

STATS sets up FastRamp test services; expands test operations

Mon, 10 Oct 2001
October 29, 2001 - Singapore and Milpitas, CA - ST Assembly Test Services Ltd. (STATS) and ST Assembly, an independent semiconductor test and advanced packaging service provider, have established a wholly owned subsidiary, FastRamp Test Services Inc., to provide high-end engineering and pre-production test services in Silicon Valley.

LSI Logic licenses flip chip packaging technology to Advanced Interconnect Technologies

Wed, 10 Oct 2001
October 17, 2001 - Milpitas, CA - LSI Logic and Advanced Interconnect Technologies (AIT) announced a licensing agreement in which AIT will license LSI Logic's organic laminate flip chip FPBGA technology. AIT joins a growing number of companies licensing LSI Logic's flip chip technology, the companies said.

Kulicke & Soffa, Amkor expand flip chip technologies license agreement

Thu, 11 Nov 2001
November 8, 2001 - Willow Grove, PA & Chandler, AZ - Kulicke & Soffa Industries Inc. and Amkor Technology have expanded the 10-year technology transfer agreement between Amkor and Flip Chip Technologies, L.L.C. (FCT), a wholly-owned subsidiary of Kulicke & Soffa.

Kulicke & Soffa, Amkor Technology complete flip chip technology transfer

Wed, 12 Dec 2001
Dec. 5, 2001 - Willow Grove, PA & Chandler, AZ - Kulicke & Soffa Industries Inc. and Amkor Technology have successfully transferred K&S Flip Chip Division's wafer bumping and redistribution technologies to Amkor's wafer bump fabrication facility in Gwanju, Korea.

Electroglas named newest member of SECAP consortium

Wed, 12 Dec 2001
Dec. 5, 2001 - San Jose, CA - Electroglas, a supplier of test and inspection equipment, has joined the Semiconductor Equipment Consortium for Advanced Packaging (SECAP).

STATS introduces IC package

Mon, 1 Jan 2001
Singapore--ST Assembly Test Services (STATS), an independent semiconductor testing and advanced packaging service provider, has introduced another IC package for the wired and wireless communications markets. Known as the Stacked Die Ball Grid Array (SDBGA), it is distinguished by its stacking feature, combining various ICs in one package, which can significantly reduce manufacturing costs, testing time, and real estate on the motherboard.

CR Technology expands headquarters

Mon, 1 Jan 2001
Aliso Viejo, California--CR Technology has expanded its worldwide headquarters by 30% to meet the significant increase in demand for its advanced line of vision and x-ray inspection systems. The new 26,000-sq-ft facility allows the company to accommodate the growing sales generated by the printed circuit board (PCB) assembly and semiconductor packaging industries.

National Semiconductor licenses Kulicke & Soffa's wafer bumping technology

Wed, 1 Jan 2001
Willow Grove, Pennsylvania--Kulicke & Soffa Industries Inc. and its Flip Chip Technologies, LLC (FCT) joint venture today announced that National Semiconductor Corp., Santa Clara, CA, has signed a license for FCT's wafer bumping technology.

Amkor files packaging patent infringement suit against STATS

Wed, 2 Feb 2001
February 21, 2001--Amkor Technology has filed a packaging patent infringement suit against ST Assembly Test Services, Inc. in Milpitas, CA, and ST Assembly Test Services Ltd. in Singapore. In its suit, Amkor alleges that STATS infringes its U.S. Patent No. 6,143,981 by making, selling, offering for sale, or importation into the U.S. the Quad Leadless Package, which Amkor says infringes one or more of the 19 separate MicroLeadFrame packaging technology claims in the '981 patent.

ASE, Conexant to exchange advanced packaging technologies

Tue, 2 Feb 2001
FEB. 20 Santa Clara, California--Advanced Semiconductor Engineering Inc. (ASE) and Conexant Systems, Inc. today announced a cross-licensing agreement in which both companies will exchange advanced semiconductor assembly technologies.

Siliconware expands capacity, licenses K&S technology

Thu, 2 Feb 2001
FEB. 15 Willow Grove, Pennsylvania--Kulicke & Soffa Industries Inc. and its Flip Chip Technologies, LLC (FCT) joint venture today announced that Siliconware Precision Industries Co. Ltd. has signed a license for FCT's Ultra CSP wafer-level packaging technology. In addition, Siliconware is expanding capacity for wafers bumped with FCT's Flex-on-Cap (FOC) wafer bumping and redistribution technologies by 80%, under a 10-year technology transfer agreement with FCT signed in December 1999.

Flip chip technology patents awarded to Endwave

Tue, 2 Feb 2001
FEB. 13 Sunnyvale, California--The U.S. Patent Office has awarded three new patents to Endwave Corp. that cover key aspects of its flip chip IC (FCIC) technology, the core technology that powers Endwave's ultra-broadband wireless systems. The technologies covered in the patents include: Patent No. 6,094,114--Slotline-to-Slotline Mounted Flip Chip; Patent No. 6,034,580--Coplanar Band Pass Filter; and Self-Biasing RF Transistor Circuit.

Unitive plans worldwide wafer level bumping and flip chip facilities

Tue, 2 Feb 2001
Research Triangle Park, North Carolina--Unitive Inc., a provider of outsourced advanced semiconductor packaging technologies, has closed a $30 million round of equity financing led by Onex Corp. and now plans to build and acquire state-of-the-art wafer level bumping and flip chip fabrication facilities throughout the U.S., Europe, and Asia.

Kimball International opens microelectronics facility in California

Wed, 3 Mar 2001
March 14, 2001--Jasper, Indiana--Kimball International, Inc. today announced the opening of its new 40,000-sq.-ft. microelectronics facility in Valencia, CA. As Kimball Electronics Group's (KEG) Microelectronics Center of Excellence, the facility will support wafer and die processing, design and manufacturing of standard and custom monolithic devices, multi-chip modules (MCM's), chip-on-board (COB), and surface mount (SMT) assemblies.

Microsemi receives patent for microwave flip chip technology

Wed, 3 Mar 2001
March 14, 2001--Santa Ana, California--Microsemi Corp. has received a patent for its breakthrough Monolithic Microwave Surface Mount semiconductor packaging technology that eliminates costly ceramic and metal packages commonly used for components operating at frequencies up to 12 GHz in high-speed microwave applications.

Unitive supports production requirements for Amkor

Wed, 8 Aug 2001
August 29, 2001 - Research Triangle Park, NC - Unitive Inc. and Amkor Technology announced the qualification of Unitive's wafer bumping technology for use in Amkor's flip chip product family.

K&S licenses Flip Chip Technologies' wafer bumping technology to STATS

Thu, 8 Aug 2001
August 23, 2001 - Willow Grove, PA.- Kulicke & Soffa Industries Inc. announced that ST Assembly Test Services Ltd. (STATS) has signed a technology licensing agreement for wafer bumping technology with Flip Chip Technologies L.L.C. (FCT), which is wholly owned by K&S.

STS Receives Order for DRIE Tool from TU Dresden

Thu, 3 Mar 2008
(March 20, 2008) Newport, Wales, UK — Surface Technology Systems plc (STS) has announced that they have sold a Pegasus deep reactive ion etch (DRIE) tool to the Institut f

3D Packaging — Which Way to Go?

Mon, 1 Jan 2008
adapted for print by AP editors

This article, the first in a series of three on 3D packaging technology, summarizes information presented during a November 2007 webcast produced by Advanced Packaging magazine. Participants were Jean-Christophe "J.C." Eloy, founder and GM of Yole D

From the Editor: Getting My Fix

Tue, 1 Jan 2008
I'm becoming an emerging technology junkie. One of the great things about my job is learning about new developments before everyone else in the world. Most of the time, I get to write about what I learned. Sometimes I don't. It's that word "embargoed" and the phrase "off-the-record" that hold me back. Eventually, I usually get to write about it — hopefully before anybody else does.

Mouser Electronics and HI-TECH Software Ink Global Distribution Agreement

Tue, 1 Jan 2008
(January 22, 2008) Mansfield, TX — Mouser Electronics Inc. has signed a global distribution agreement with HI-TECH Software. HI-TECH software is used in a variety of embedded microcontroller product families from Microchip Technology and Cypress Semiconductor.

High-performance Socket for QFN Packages

Mon, 1 Jan 2008
The SG-MLF-7025 high-performance QFN socket is designed to accommodate 0.5-mm pitch IC packages. Simply attach the socket to the PCB, drop in chip, and place the lid. The open lid allows probing of die or direct injection of heat or cooling air.

Protecting Modern Wafer-level Packages

Mon, 1 Jan 2008
By Alan Hardy, Specialty Coating Systems

The demand for smaller sizes and lighter weights in consumer electronic devices is feeding the demand for continued package miniaturization. With expanded systems integrated onto ultra-thin wafers, these exotic final assemblies are extremely delicate. Creating complex nano-devices that function is not enough. They must keep working, and to do that, they need protection.

Microsemi to Acquire TSI Microelectronics

Tue, 1 Jan 2008
(January 8, 2008) IRVINE, CA — Microsemi Corp. today announced its recent acquisition of substantially all of the assets of TSI Microelectronics Corp. (TSI). TSI's revenue in the last 12 months totaled $1.2M and the company was profitable. Total consideration for TSI was $2.0M in cash, which includes the company's cash position of approximately $0.6M.

BiTS Workshop: A Success Story

Mon, 4 Apr 2008
By Gail Flower, editor-in-chief
The ninth annual Burn-in and Test Socket Workshop (BiTS 2008) on March 9-12, 2008 in Mesa, AZ, presented an interactive, growing, and technical successful forum for experts dedicated to sharing knowledge. BiTS brought together 350 conference attendees and 60 exhibitors worldwide from users of sockets, boards, burn-in systems, handlers, packaging engineers, and suppliers to the industry.

SEMICON China Expanding

Mon, 4 Apr 2008
By Gail Flower, editor-in-chief
On March 18-19 2008, a constant stream of visitors flowed in to SEMICON China, held in the Shanghai New International Expo Centre, to attend grand new product introductions and educational forums that addressed the latest in growth areas for electronics. What a clip of activity surrounded the conference. All of the familiar players were there doing business.

Lee to Deliver Keynote at MEPTEC MEMS Packaging Symposium

Fri, 4 Apr 2008
(April 18, 2008) Medicine Park, OK — Luke P. Lee, Ph.D., from the Department of Bioengineering at UC Berkeley has been selected as keynote speaker for MEPTEC's 6th Annual MEMS Packaging symposium titled "MEMS Market Evolution: From Technology Push to Market Pull" on May 22, 2008. This one-day event will take place at the Wyndham Hotel, San Jose, CA.

3D Packaging Technologies Expected to Dominate Industry

Wed, 4 Apr 2008
(April 23, 2008) Palo Alto, CA— 3D packaging is expected to emerge as a dominant performing solution in the electronic/chip packaging industry. Its performance promises to drive efforts across the entire supply chain to successfully deploy it, according to analysis reports from Frost & Sullivan's Global Trends in Electronic/Chip Packaging. Analysis indicates that the industry is moving beyond system on chip (SoC) to explore various forms of system in package (SiP).

Yole Releases WLP Report

Fri, 2 Feb 2008
(February 15, 2008) Lyon, France — Yole Developpement has just released a new report entitled "WLP & Embedded Die Technologies 2008". This report presents the manufacturing challenges faced by the wafer level packaging industry in terms of MEMS, CMOS image sensors and semiconductor ICs.

SEMICON West Courses Announced

Tue, 2 Feb 2008
(February 19, 2008) — Going to SEMICON West? PTI Seminars and SEMI have announced semiconductor courses at the San Francisco show in July. Some courses of interest include: Fundamentals of MEMS Design and Fabrication, Introduction to Chip and Wire Assembly in Microelectronics Packaging, and Low-cost Flip Chip, WLCSP, and Lead-free Technologies.

MEPTEC Finalizes Program for 4th Thermal Management Symposium

Thu, 2 Feb 2008
(February 21, 2008) — MEPTEC, the MicroElectronics Packaging and Test Engineering Council, has finalized the program for its 4th Annual Thermal Management symposium titled "The Heat Is On: Thermal Technology Solutions for Advanced Products." This one-day technical event will be held on February 28, 2008, at the Wyndham Hotel, San Jose, CA.

Indium Corp. Presents Award to Zen Voce

Thu, 2 Feb 2008
(February 21, 2008) — Indium Corp.'s Semiconductor Packaging Materials team presented their Equipment Partner of the Year Award to Zen Voce. The award, presented in Singapore, was given to Zen Voce's GM, Jeffrey Mah, by Indium's managing director for Asia-Pacific operations, Pang Weng Fai.

IPC Sponsors Endicott Technology Interchange: Will You Be Ready?

Wed, 2 Feb 2008
(February 27, 2008) Bannockburn, IL — Technological advances on the horizon and future industry demands: this is the focus of "Will You Be Ready?: An Endicott Technology Interchange," sponsored by IPC, the Association Connecting Electronics industries. On May 14, Endicott Interconnect Technologies Inc. will open up its headquarters in Endicott, NY, for a day of information exchange and networking in order to provide a vision of future direction and needs.

Amkor Technology Introduces Novel Package Platform

Thu, 2 Feb 2008
(February 28, 2008) CHANDLER, AZ — Amkor Technology, Inc. introduced FusionQuad, a novel package technology designed for applications that call for high electrical and thermal performance at low cost. Broad application of this package includes consumer electronics, Ethernet, and a variety of applications across all semiconductor markets.

Zygo Acquires Assets of Solvision, Enters Semiconductor Back-End Inspection Market

Fri, 2 Feb 2008
(February 29, 2008) Middlefield, CT — Zygo Corp. has announced that it has acquired the assets of Solvision Inc., a Canadian-based company, including the shares of its Singapore subsidiary. With this acquisition, Zygo enters the market for in-line inspection of flip chip substrates and packaged ICs.

China Packaging Society President to be Speaker at GBC Conference

Fri, 2 Feb 2008
(February 29, 2008) Scottsdale, AZ — The IMAPS Global Business Council (GBC) is pleased to announce that Bi Keyun, PhD and president of the China Electronic Packaging Society, will head a delegation from China and will speak at GBC Spring Conference in Scottsdale, AZ, on March 16 and 17, 2008.

Line of Assembly Materials
Heraeus Contact Materials Division

Mon, 3 Mar 2008
This company's latest versions of its assembly materials will include conductive and nonconductive adhesives for die attach and flip chip applications, heat conductive adhesives for thermal management, and dippable solder pastes for BGA packaging. Given the increasing complexity of BGA packages and the sensitivity of the polymer substrates to multiple thermal processes, the ball dippable (BD) paste series enables manufacturers to utilize SOP substrates while maintaining outstanding yields.

Advanced Placement System
Juki Corp.

Mon, 3 Mar 2008
The CX-1 advanced placement system is capable of placing SiP, MCM and other mixed-technology applications. The CX-1 is built on the base of a standard SMT machine, but with highly accurate glass linear encoders. Special software periodically checks and calibrates to ensure ultra-high accuracy.

SMTA's 3D/SiP Symposium Promotes Industry-wide Collaboration

Tue, 5 May 2008
Last week's 3D/SiP Symposium hosted by SMTA, and co-sponsored by Advanced Packaging magazine, turned out to be an intimate gathering of approximately 55 attendees representing not only the U.S., but Canada, France, Japan, Taiwan, United Kingdom, Austria and the Republic of Korea.

Oerlikon Esec Introduces Product Family at SEMICON Singapore

Mon, 5 May 2008
(May 5, 2008) Cham, Switzerland and Singapore — Oerlikon Esec, provider of automated chip assembly equipment and system solutions for the semiconductor industry, formally introduced the introductory platform of an entirely new product family at an official unveiling during SEMICON Singapore. The Die Bonder 2100 xP targets the high-volume epoxy die attach market.

Flip Chip Goes 3D

Tue, 5 May 2008
By Daniel F. Baldwin, Ph.D. and Paul Houston, ENGENT, Inc.
With advances in wafer-thinning technology, 3D packaging now provides a robust platform for achieving high levels of integration, small package footprints, and thin package profiles. Further component miniaturization with the added benefit of 3D integration can be realized by face-to-face bonding of fine-pitch flip chip components and low-profile passives onto a redistribution layer (RDL) of another silicon component.

Renesas Adopts Cadence Tool for Large Scale SoC and Flip Chip Design

Mon, 5 May 2008
(May 12, 2008) San Jose, CA — Cadence Design Systems, Inc. announced that Renesas Technology Corp. has successfully taped out its most advanced and large-scale system-on-chip (SoC) design to date using the Cadence SoC Encounter system. Hisaharu Miwa, general manager, Design Technology Division LSI Product Technology Unit at Renesas credits the system's memory capacity and fast turnaround time as the reason for the successful tape out.

STATS ChipPAC Completes Qualification of Fan-in PoP

Tue, 5 May 2008
(May 13, 2008) SINGAPORE — STATS ChipPAC Ltd. announced the completion of full internal qualification of its Fan-in Package-on-Package (FiPoP) technology. Fully functional electrical samples are available, and production volumes are expected to ramp by the end of 2008.

Vietnam - Chipscale Advanced Packaging Services Receives Certification

Wed, 5 May 2008
(May 14, 2008) Hanoi, VIETNAM — Vietnam-Chipscale Advanced Packaging Services, an outsource semiconductor assembly and test services provider based in Vietnam, has been presented with its investment certificate from th Vietnamese government, recognizing the company as a 100% foreign owned venture.

SiP Seminar to Address Design Issues

Mon, 5 May 2008
(May 19, 2008) Cambridge, UK — The National Microelectronics Institute (NMI) and TWI will hold the third in a series of annual one-day seminars addressing System-in-Package (SiP) trends, technologies, and applications at TWI, Granta Park, Cambridge, June 3, 2008. The program focuses on Design for SiP, a topic that has been long recognized as one of the key barriers to SiP adoption. Jan Vardemann, of Techsearch International, will deliver the keynote in SiP design and applications.

3D Integration Tour: Are TSVs the Future of Advanced Packaging?

Thu, 5 May 2008
By Julia Goldstein, contributing editor
(May 22, 2008) San Jose, CA — The "3D Integration North American Tour" came to San Jose on May 15 after stops in Durham, NC and Dallas, TX. The event, hosted by SUSS MicroTec, Surface Technology Systems (STS) and NEXX Systems outlined the current state of the art in through silicon vias (TSVs) and related technology.

Barry Industries Introduces Semiconductor Packaging Line

Tue, 5 May 2008
(May 26, 2008) Newburyport, MA — Barry Industries has introduced a line of semiconductor packaging featuring high temperature cofired ceramic (HTCC) technology for aerospace, RF/microwave, semiconductor, and optoelectronic devices.

ECTC 2008 Gets Underway in Lake Buena Vista

Tue, 5 May 2008
(May 27, 2008) Lake Buena Vista, FL — The 58th Electronic Components Technology Conference (ECTC), an international conference that brings together the best in packaging, components and microelectronic systems in science, technology and education gets under way Wednesday, May 27, in Lake Buena Vista, FL, with more than 340 technical papers being presented in 36 oral sessions, two poster sessions and a special student poster session.

Determining the Right Wafer Bumping Solution

Thu, 5 May 2008
By M.K. Chew and H.G. Su, Unisem-Advanpack Technologies
Wafer bumping is fast becoming the interconnect of choice for wafer level chip scale packages (WLCSPs). This migration is primarily driven by applications like power management devices, ASIC and memory chips, display drivers, Internet routers, microcontrollers, D/A converters, and RF devices that are transitioning from wire bond plastic encapsulated units to flip chips and WLSCPs.

DEK Names Business Manager

Thu, 7 Jul 2007
(July 12, 2007) SAN JOSE, CA — DEK appointed Aram Kardjian as western regional business manger, promoting developing applications such as materials deposition in semiconductor packaging, medical electronics, fuel cells, and other markets. He will also be responsible for customer support, and implementing and supporting growth targets and corporate development in the western U.S.

Fjelstad Joins Mirror Board

Mon, 7 Jul 2007
(July 16, 2007) IRVINE, CA — Joe Fjelstad joined the technical advisory board of Mirror Semiconductor, contributing "diverse talents" to the company, according to Martin Hart, president and founder. Fjelstad is co-founder of SiliconPipe Inc. (San Jose), and an Advanced Packaging editorial advisory board member.

SEMICON Attendees Choose ACA Winners

Thu, 7 Jul 2007
(July 19, 2007) SAN FRANCISCOAdvanced Packaging and Solid State Technology Magazines presented the Attendee's Choice Awards (ACAs) in six front-end and final manufacturing categories to exhibitors at SEMICON West. The awards were voted on by show attendees, and presented on the tradeshow floor.

Universal Launches Monthly Seminars With Flip Chip

Fri, 7 Jul 2007
(July 20, 2007) SHANGHAI, China — Universal Instruments will hold a free seminar August 10, 2007, at its Advanced Process Laboratory in Shanghai, focusing on flip chip assembly processes, materials, and requirements. The seminar is open to customers and all interested parties.

TechXPOT Focus: Packaging Material Trends

Fri, 7 Jul 2007
By Françoise von Trapp, managing editor, Advanced Packaging

Material science has a firm foothold in the future of advanced packaging. At SEMICON West's Wednesday, July 18, Packaging Materials Trends TechXPOT, sponsored by IMAPS, industry experts shared insights and developments in packaging materials, their applications, and how these innovations will help device packaging address functionality, form factor, and reliability challenges.

RFMD Expands China Packaging

Mon, 7 Jul 2007
(July 23, 2007) GREENSBORO, NC — RF Micro Devices, Inc. (RFMD), will expand its Beijing, China, facility with increased capacity and new advanced packaging processes to enable flip chip, wire bond, test capabilities, and proprietary self-shielding RF assemblies.

Moore's Law — the Z-dimension: a Decade Later

Thu, 12 Dec 2008
By Sergey Savastiouk, ALLVIA
Almost 10 years ago (January 2000) I wrote an article for SST titled "Moore's Law — the Z-dimension". The call was to shift focus towards Moore's Law in the z-dimension and then invest in affordable, vertical miniaturization and integration, rather than continue to invest in further feature size reduction. A new term—through silicon vias (TSVs)—was first introduced in that article and is now commonly used.

Letter to the Editor

Mon, 12 Dec 2008
I would like to clarify the comments you attributed to me as a result of our conversation at IMAPS International. I do not believe I said that through silicon vias (TSVs) were a pipedream, nor did I doubt that they would be adopted. What I said was that they would not be adopted at the rate projected. That is why I referenced the flip chip vs. wire bond issue as an historical reference.

Industry Outreach: Collaborating with MEPTEC

Mon, 12 Dec 2008
By Gail Flower, editor-in-chief
One of the best parts of our industry is the spirit of cooperation, camaraderie, and outreach that seems to embody all that's best in human nature. Advanced Packaging often collaborates with industry organizations to plan and/or co-sponsor events. I recently returned from a cooperative effort with MEPTEC in honor of its 30th anniversary with a program titled, Packaging Developments and Innovations: From System Design to Integrated Delivery.

Learn, Explore, Share at BiTS Workshop 2009

Thu, 12 Dec 2008
By Fred Taber, BiTS Workshop
(December 11, 2008) MESA, AZ — The Burn-in and Test Socket Workshop (BiTS), co-sponsored by Advanced Packaging magazine, celebrates its tenth annual gathering, March 8

Chemical Monitoring and Replenishing Systems

Tue, 5 May 2008
The Qual-Fil QF Series combines ECI Technologies' chemical monitoring technology with dosing capabilities to address the need for precision metal plating in advanced packaging applications. The modular system supports both electroplating and electroless deposition. It can manage multiple plating baths simultaneously due to online monitoring and automatic replenishment of multiple components.

Multi Flip Chip Bonder for MCM/SiP

Mon, 5 May 2008
The 8800 CHAMEO Multi Flip Chip Bonder from Datacon was developed for high-volume, high-throughput MCM / SiP assembly. Based on the same high-precision, dual-head architecture of its predecessor, the 8800 FC Quantum, it adds multi-flip-chip/MCM/SiP assembly and wafer handling capabilities as required in today's advanced manufacturing environments.

People in Packaging

Thu, 2 Feb 2008
February 20, 2008 — Since the beginning of February, a number of companies have announced significant shifts in management and personnel. Among them were Amkor, who's COO accepted a CEO position elsewhere; Tessera Technologies, who appointed former CTO of Flextronics to their board; Asymtek, who promoted their European sales and marketing manager to general manager; SUSS MicroTec, who appointed a V.P of sales; and...

Taking Care of Business and Working Overtime

Sun, 10 Oct 2006
How often have we heard, “Nothing personal; I know it’s not right, but it is good business”? To that I say, “No way.

Tessera and Flextronics Sign Licensing Agreement for Shellcase CF

Sun, 10 Oct 2006
SAN JOSE, CA - Further paving the way into the consumer optics arena, Tessera announced the first licensing agreement for their wafer-level image sensor packaging technology, Shellcase CF, to Flextronics International Ltd.

New Products

Sun, 10 Oct 2006
Dage’s computerized tomography (CT) option for digital X-ray inspection systems uses a digital geometric process to generate a 3-D image model from a series of individual 2-D X-ray image “slices” taken around a single axis of rotation.

Solid-state Memory Growth for Packaging

Sun, 10 Oct 2006
The removable solid-state storage (RS3) market posted strong growth in 2005, as consumer demand for flash cards and universal serial bus (USB) flash drives continued.

Measuring 3-D Semiconductor Packages

Wed, 2 Feb 2006
Meeting the Challenge

Commonly Asked Lead-free Cleaning Questions

Wed, 3 Mar 2006
When considering cleaning lead-free residues, what needs to be asked first: must I, should I, can I, can I afford to, or can I afford not to?

Flip Chip Technology

Sat, 7 Jul 2006
Mainstream At Last

Advanced Packaging: On the Move

Fri, 9 Sep 2006
This Roadshow thing is taking on a life of its own. Our latest trip literally took us from coast-to-coast and back again.

In the News

Fri, 9 Sep 2006

Dare to Share

Wed, 11 Nov 2006
It’s amazing how much you learn when you reach out to others. My father often told me figuring out what I would do with my life was a quandary to him.

Advanced Packaging: on the road again

Sat, 7 Jul 2006
We had such a great time, met such interesting people, and learned so much on our first Roadshow trip that we knew it was just the beginning of a great new element of Advanced Packaging.

The Latest in Packaging Research

Fri, 4 Apr 2005
Every now and then, it’s especially good to step out of your normal activities and see what’s going on at other companies and universities.

Subcontractor Update: Up in 2004, Uncertainty into 2005

Fri, 4 Apr 2005
The major assembly and test subcontractors ended 2004 with revenues up significantly over 2003, but with a slowing trend leading into 2005.

Starting a New Year

Tue, 2 Feb 2005
I recently talked to many engineers and forecasters to see how this year has begun and what forces are at work.

Evolution of Organic Flip Chip Packaging

Fri, 4 Apr 2005
Packaging Technology Ready For Change

Touting the Next Big Thing

Fri, 7 Jul 2005
Have you noticed how electronics experts are all searching for the next piece of news, the next new product that will blow away the competition, or that one bit of “secret stuff” that no one else knows about?

3-D Packaging: A Growing Level of Functional Integration

Fri, 7 Jul 2005
Feature-rich cell phones, pocket PCs, digital cameras, and other handheld consumer products require maximum functional integration, including memory, DSP, ASIC, RF, MEMs, and other devices in the smallest footprint, lowest profile, and lowest cost package available.

Advanced Packaging Celebrates the APAs in Style

Fri, 9 Sep 2006
On July 12, 2006, Advanced Packaging celebrated the 6th Annual APA Awards ceremony with style and panache.

Chip-package Co-optimization

Fri, 9 Sep 2006
The packaging engineer’s long-time lament is the challenge of an over-designed or too large chip.

A New Year Begins

Thu, 1 Jan 2004
Each New Year brings with it a hope for continued growth and prosperity. This year is no exception. Let's face it; the last two years in electronics assembly have been grim. However, most signs point upward for 2004.

In the News

Thu, 1 Jan 2004

Neurons on Chip: Bridging the Gap Between Biology and Microelectronics

Thu, 1 Jan 2004
To bridge the gap between biology and electronics in neurons on chip, IMEC, the University Hospital of Leuven (Leuven, Belgium) and Hebrew University (Jerusalem, Israel) researchers are exploring new transducer concepts, surface chemistry solutions and packaging techniques. We believe that the key to efficient and reliable ionoelectronic devices is surface chemistry.

New Products

Thu, 1 Jan 2004

In the News

Sat, 1 Jan 2005

Keeping Up With the Joneses: The Evolution of Leadframes

Sat, 1 Jan 2005
We all know array packaging

R&D: Critical to Future Technologies

Sat, 1 Jan 2005
Research and development is critical to future technologies of every sort. In the realm of electronics, R&D is both the heart and life

Adhesive Interconnect Flip Chip Assembly

Tue, 3 Mar 2005
The search for lead solder alternatives is stimulating interest in isotropic conductive adhesive assembly for flip chip interconnection.

Focus on Flip Chips

Mon, 5 May 2006
Don’t you just love being right? It took a long time for flip chips to go mainstream, but now that they have made it, it’s very satisfying.

Advanced Packaging Hits the Road

Mon, 5 May 2006
Advanced Packaging thought it was time for a fresh look at what’s really happening in the semiconductor packaging industry, so we’ve hit the road.

Rolling Along and Shifting Gears

Sun, 1 Jan 2006
Like baseball and apple pie, innovation has long been a hallmark of American culture.

Material Sets: The Next Outsourcing Trend

Sun, 1 Jan 2006
The never-ending quest to reduce manufacturing costs while still maintaining fast product development cycles and delivering reliable products is a dilemma that faces all electronics manufacturers.

The Role of X-ray Inspection in RFID Assembly

Sun, 1 Jan 2006
Providing a Critical Link

A Celebration of Packaging

Wed, 10 Oct 2008
A packaging engineer living in this Information Age has an obligation to keep on top of everything that’s happening.

From End to End

Wed, 10 Oct 2008
In semiconductor manufacturing, there’s a lot of talk about ends. First, there’s the front-end and the back-end.

fcPiP: The Marriage of Flip Chip and Wire Bond

Wed, 10 Oct 2008
Cellular handsets and mobile handheld products are defining a new application space that goes beyond the realm of traditional flip chip and 3D packaging.

Nanos Are Coming

Wed, 3 Mar 2006
It’s official - the nanos are coming. While not yet battering our packaging gates, they are within sight of our walls, and advancing rapidly.

Flip Chip Interconnection Using Copper Wire Bumps

Wed, 3 Mar 2006
Various flip chip systems have been used for advanced packages, including chip scale packages (CSPs) and ball grid arrays (BGAs).

In the News

Sat, 4 Apr 2006

Breaking Down the Barriers for True Innovation

Sat, 4 Apr 2006
Senior executives at semiconductor companies worldwide have an innovation crisis on their hands.

SEMICON WEST (BACK END) DAY 3 NEWS

Thu, 7 Jul 2003
(July 18, 2003) K&S Announces a Volume Purchase Agreement with National Semiconductor; Semiconductor Companies Take Center Stage at AP Award Program; Tessera Presents 3-D Packaging Symposium

SEMICON WEST NEW PRODUCTS (PART 3 OF 3)

Thu, 7 Jul 2003
The following is a selection of new products that you will see on the exhibitor floor at SEMICON West in San Jose, Wednesday, July 16, to Friday, July 18. See the SEMICON WEST EXHIBITOR LIST for booth numbers.

NEW PRODUCT HIGHLIGHTS

Fri, 10 Oct 2003
Amkor's power SiP addresses thermal challenges
(February 3, 2004) Chandler, Ariz.—Amkor Technology Inc. is using its system-in-package (SiP) technology to solve the challenges of thermally demanding DC/DC power-conversion applications.

Joe Fjelstad Releases Flexible Circuit Technology, 3rd Edition

Wed, 11 Nov 2006
SEASIDE, OR - The third edition of Flexible Circuit Technology features new technologies and applications that have developed over the eight years since the second edition was published.

Tin Pest in Tin-rich Solders

Wed, 11 Nov 2006
Tin is a common component of solders because of its desirable properties such as low melting point, high diffusivity, low surface tension in the liquid phase, and others.

What's up with Flip Chips?

Sun, 8 Aug 2004
On June 21 in Austin, Texas, I moderated a panel for the Global Business Council (GBC) of IMAPS covering the global flip chip business overview.

The Time Machine and Its Lessons

Sun, 8 Aug 2004
About 10 years ago, I held an aluminized silicon wafer in hand, curiously regarding a dull, non-reflective square covering most of the surface.

The Inspection Connection 2

Thu, 12 Dec 2005
Latest Technologies in Optical Inspection

Lead-free WLCSP Qualification

Tue, 11 Nov 2005
A Consumer Electronics Case Study

Looking Forward

Thu, 12 Dec 2005
In the month of December, as one year nears its close, I begin to think about where the world of advanced packaging has been and will go.

Wafer-level Processes are Going Backwards-compatible

Thu, 12 Dec 2005
Whichever way you read the data or interpret the signs, modern product lifecycles are diminishing quickly enough to stretch the limits of feasibility.

Semiconductor Assembly and Test Providers: The New Technology Frontier

Mon, 8 Aug 2005
As device manufacturing continues down the path of smaller geometries and increased densities laid out by Moore’s law, the importance of packaging technology to the overall performance of the device continues to grow in parallel.

A Breath of Fresh Air

Thu, 9 Sep 2005
Someone once said that to do the same thing over and over while expecting a different result is the definition of insanity.

Advanced Packaging Salutes Innovative Excellence

Thu, 9 Sep 2005
It is with great pleasure that once again, Advanced Packaging Magazine congratulated the participants and winners of the 2005 Advanced Packaging Awards (APAs).

London Bridges

Sat, 5 May 2004
Late in March, Advanced Packaging's editors and publisher arrived at Windsor Castle Hotel in Windsor, England for a "Meet the Editors" Reception.

In the news

Sat, 5 May 2004

Flip Chip Solder Joint Failure Modes

Sat, 10 Oct 2005
High Electric-Current Density Testing

In the News

Mon, 3 Mar 2004

Shedding the 'Subcontractor' Moniker

Mon, 3 Mar 2004
Those involved with the assembly and packaging end of semiconductor manufacturing are seeing a fundamental change in the role of a few suppliers who used to be lumped under the moniker "subcontractors."

New Products

Mon, 3 Mar 2004

The Roadmap Challenge to Design Services

Mon, 3 Mar 2004
MARKET REQUIREMENTS LEAD TO ADOPTION OF NEW TECHNOLOGIES

Bump Arrays for RF Applications: Step 5

Sat, 5 May 2004
Modeling Methodology

A Look at IMAPS

Mon, 8 Aug 2005
There are just so many tradeshows that you can attend each year, but if you have to choose just a few for back-end assembly, SEMICON West and IMAPS should be high on your list.

Minding Our Business

Wed, 1 Jan 2003
This year we are increasing the scope of our coverage of the packaging world by adding a focus on business issues.

Subcontractor Update: Positive Signs

Wed, 1 Jan 2003
Business has taken a distinct upturn in the last six months at the major assembly and test subcontractors.

Outsourced Assembly and Test

Mon, 11 Nov 2004
At Amkor, we are addressing opportunities to expand the outsourced semiconductor assembly and test (OSAT) industry.

Advanced Packaging Techniques Impact High-energy Physics Research

Mon, 11 Nov 2004
Scientists at the Fermi National Accelerator Laboratory (Fermilab) are working on a new major high-energy physics project, the BTeV (B physics at the Tevatron) experiment.

Global Trends in Lead-free Soldering

Sun, 2 Feb 2004
PART II OF A II-PART SERIES ON LEAD-FREE

Flip Chip Cleaning with Vapor Phase Solvents

Sun, 2 Feb 2004
Active Solvent Concentration is Essential Driver for Cleaning

Feeling Bullish

Mon, 3 Mar 2004
ost everywhere you look in our industry, good news abounds.

You Said It

Sun, 2 Feb 2004
In the period of time between the end of winter holidays and the buildup to spring activities, readers become a little more social.

Electronics Interconnections for Extreme Environments

Sun, 2 Feb 2004
In January 2004, NASA landed two rovers named Spirit and Opportunity on Mars to explore the surface and gather geologic information to beam back to Earth.

Advances in Bioelectronics Lead to Retinal Prosthesis

Fri, 10 Oct 2004
Chronically implantable retinal prostheses currently are under development to restore useful vision to blind patients with degenerative retinal diseases such as age-related macular degeneration and retinitis pigmentosa.

Semiconductor Packaging Grows While Industry Lags

Thu, 5 May 2003
While relatively unnoticed, the packaging industry has been slowly but steadily growing over the past 18 months.

System-on-Chip-in-Package

Sat, 2 Feb 2003
System-on-chip (SOC) design and fabrication technology is beginning to provide single-chip wireless products.

Pyramids, Purgatory and 76 Trombones

Thu, 5 May 2003
We humans are fascinated with eternity. In books, movies or our portfolios, we are always looking for the perfect long-term solution.

Cover Story: Flip Chip and BGA Solder Joint Reliability

Thu, 5 May 2003
The trend in flip chip and ball grid array (BGA) packages to increase I/O counts drive the interconnecting solder joints to be smaller in size and, thus, have higher current density.

Alphabet Soup

Sun, 6 Jun 2003
There are some things that this industry really needs, such as a solid dictionary to sort out the various elements of alphabet soup and to standardize the language of the field engineer.

Winning, Losing, and Staying in the Game

Wed, 12 Dec 2004
There are few things that mark a person's character more than the way they accept defeat; unless, of course, it's the way they persist through each day and each challenge.

Packaging Alternatives

Thu, 7 Jul 2004
NEW PACKAGING CONCEPT PROVIDES RELIABILITY

Advanced Wafer-level Cleaning Method

Thu, 7 Jul 2004
DEVELOPMENT OF ADVANCED STRIPPING CHEMISTRIES

Design for Reliability of Stacked Die CSPs

Thu, 7 Jul 2004
FATIGUE MODELING

Overmolded Electronic Assembly Packaging

Thu, 7 Jul 2004
OVERMOLDING PROVIDES COST, RELIABILITY AND MANUFACTURING IMPROVEMENTS

Simplicity of Selling?

Sat, 2 Feb 2003
One of the very few constants this time of year is Girl Scout Cookies. While many of us have peered over our shoulders and stared down declines in markets that would have been unheard of just two years ago, one simple constant remains.

Product Preview

Sat, 3 Mar 2003
A series of low-volume ProFlow transfer heads reduce costs and enhance the precision of high-accuracy mass imaging, using small quantities of high-value materials. These include fine particle, low-alpha solder pastes and high gold content compounds used to create grid arrays and other features in advanced packages such as CSP and flip chip. These new additions are said to achieve high accuracy and repeatability in processes requiring individual deposits less than 200 mg.

Getting to Know You

Tue, 4 Apr 2003
Many of you may already know me, perhaps under the name of Gail Stout, since I've been the editor-in-chief of SMT Magazine for many years.

Stud Bumping and Die Attach for Expanded Flip Chip Applications

Wed, 9 Sep 2004
SUPPORT FOR TODAY'S EMERGING APPLICATIONS

When Companies Acquire Companies

Wed, 9 Sep 2004
There are lots of reasons why companies buy other companies.

Cost Implications of Package Proliferation

Wed, 9 Sep 2004
Although the proliferation of semiconductor packages has been a part of the industry for the past 20 years, the last several years have seen the rate of proliferation accelerate.

Exploring New Frontiers in Power- and Nano-Electronics

Wed, 9 Sep 2004
The Electronic Packaging Lab at the University at Buffalo has earned a reputation for its cutting-edge work in developing computational and experimental measurement tools for facilitating the development of the next-generation microelectronics packaging.

Recognizing Excellence in Innovation

Wed, 9 Sep 2004
It is once again with great pleasure that Advanced Packaging Magazine congratulates the winners and participants of the 2004 Advanced Packaging Awards.

Variable Flip Chip Assembly for High-volume Production

Tue, 6 Jun 2004
Solder bump and adhesive flip chip advantages

Who Will Regulate Lead-free Compliance?

Thu, 7 Jul 2004
We all know that you can do well by doing good, right? When it comes to lead-free, many advanced packaging OEMs have already made an announcement of compliance.

SATS Outsourcing Growth Is Blossoming

Thu, 7 Jul 2004
Last week, the Microelectronic Packaging and Test Engineering Council (MEPTEC) held what it hopes to be the first of many semiconductor assembly and test services (SATS) investor conferences.

Evolution of Wafer-level Packaging

Thu, 7 Jul 2004
Sandia National Laboratories and Fujitsu conceived the wafer-level package (WLP) in the mid 1990s.

The Latest New Thing

Wed, 10 Oct 2003
Though markets tend to go in and out of fashion, it's important for those covering the industry to keep in touch. The optoelectronics market, for instance, has always been a bit elusive, just tantalizing us with possibilities.

**NEW** SPECIAL SERIES COMPILATION

Mon, 1 Jan 2002
The 2001 Back-End Process: Step-by-Step
Industry newcomers and veterans alike benefit from our monthly series of step-by-step articles that outline the packaging process -- how it's changed, how it's stayed the same and how it's applied today. Click here for this special reference tool.

THE 2002 ADVANCED PACKAGING AWARDS

Wed, 1 Jan 2002
synopsis

THE 2002 ADVANCED PACKAGING AWARDS

Tue, 2 Feb 2002
Click here for and entry sheet

THERMAL AND POWER MANAGEMENT CONFERENCE

Thu, 2 Feb 2002
Cool Chips 2002 Conference Lineup
Intertech has a set agenda for its power and thermal management development conference, "Cool Chips 2002 -- Developing New Market, Material and Design Strategies for Thermal and Power Management," which will be held April 3-4 in Monterey, California. With packaging being a critical part of thermal management in electronic products, Advanced Packaging magazine is acting as the media partner for the event.

HAPPY BIRTHDAY ADVANCED PACKAGING!

Fri, 2 Feb 2002
10th Anniversary Insights Series
In 2002, Advanced Packaging included a special guest column where industry experts discuss the changes they've witnessed during the past 10 years.
Click here to read the columns for 2002.

MEETING REPORT

Tue, 5 May 2002
Updates on folded flex and thin packaging at ICAPS
RENO, NEV.
The International Microelectronics and Packaging Society held its first International Conference on Advanced Packaging and Systems (ICAPS) in March in Reno. The event featured sessions on most critical areas of advanced packaging technology, including design and test, 3-D packaging, MEMS packaging, and thermal management. Tabletop exhibits accompanied the two parallel technical sessions.

ADVANCED PACKAGING NEWS

Fri, 5 May 2002
Demmin to Speak at IMAPS Chapter Meeting Tonight
Jeffrey C. Demmin, editor-in-chief of Advanced Packaging magazine, will discuss "The Packaging Landscape -- Business and Technology" today at the IMAPS New England chapter meeting. (June 18)

SEMICON West San Jose - Program Highlights

Fri, 6 Jun 2002
(June 24, 2002) San Jose, Calif. -- Held here July 17 through 19, 2002, at the San Jose Convention Center, SEMICON West (Final Manufacturing) is packed with courses, classes and networking opportunities.

PUZZLE OF THE WEEK

Wed, 7 Jul 2002
Think Tank Classics: Noon Day Meal

Click here for the answer to last week's puzzle and a note about the future of Think Tank Classics.

Advanced Packaging Editor Demmin Presents The Packaging Landscape: Business and Technology at IMAPS Meeting

Mon, 7 Jul 2002
BOXBOROUGH, MASS. At the IMAPS New England Chapter Annual Meeting here on June 18, Advanced Packaging Editor-in-Chief Jeff Demmin shared his thoughts on the state of the advanced packaging marketplace, as well as future directions. (July 16)

Advanced Packaging Announces the Winners of the 2002 Advanced Packaging Awards

Thu, 7 Jul 2002
SAN JOSE, CALIF. On Wednesday, July 17, Advanced Packaging announced the winners of the 2002 Advanced Packaging Awards at a ceremony in the Club Regent Room of the Fairmont Hotel here. (July 18)

The Advanced Packaging and Interconnect Alliance (APiA) to Supply ACE Semiconductor with 200 mm Advanced Packaging Process Line in China

Thu, 8 Aug 2002
APiA to open 200 mm development center within ACE Semiconductor's newest advanced packaging fab in Shanghai China

Cookson Electronics -- Semiconductor Products Introduces No-Flow Underfill for Flip Chip Applications

Thu, 8 Aug 2002
ALPHARETTA, GA - July 9, 2002 -- Cookson Electronics - Semiconductor Products has introduced STAYCHIPTM NUF-2076E, no-flow underfill used to perform the dual functions of a solder flux and an underfill between a flip-chip die and a substrate, or an area array device and a printed circuit board.

Palomar Technologies Introduces the Gold Connection for Gold Ball Bump and Flip Chip Thermocompression Bonding

Thu, 8 Aug 2002
Vista, Calif. - July 17, 2002 - Palomar Technologies, the leading manufacturer of automated high-precision assembly systems for broadband communications, introduces Palomar's Gold ConnectionTM, consisting of Palomar's new Gold Bumper(tm) and Flip Chip TCB(tm) (Thermocompression Bonder).

Tegal Joins APiA, The Advanced Packaging and Interconnect Alliance

Fri, 8 Aug 2002
PETALUMA, Calif., July 16, 2002 - Tegal Corporation (Nasdaq: TGAL) today announced that it has been accepted as an associate member of the Advanced Packaging and Interconnect Alliance (APiA), further exemplifying Tegal's commitment to serving the needs of the packaging applications market.

Adept Technology Chosen as New Automation Member of Advanced Packaging and Advanced Packaging and Interconnect Alliance (APiA)

Fri, 8 Aug 2002
Adept Joins Alliance as Wafer Handling Automation Expert to Address Packaging Challenges and Solutions

Newport Corp. to Introduce New MRSI-375FC Flip Chip Bonder at SEMICON West

Fri, 8 Aug 2002
10 Micron Placement Accuracy

MRSI-175UF Capillary Underfill Dispenser Introduced for the Flip Chip Market

Fri, 8 Aug 2002
North Billerica, Mass., USA - MRSI, a Newport Corporation Company, announces the addition of a new underfill system to its 175 product line of dispense systems with the introduction of the MRSI-175UF. This system is targeted specifically to the flip chip underfill dispense market.

In the News

Wed, 2 Feb 2006

SEMICON Europa’s Advanced Packaging Conference Shifts Focus from TSV to WLP

Fri, 8 Aug 2008
STUTTGART, GERMANY — Shifting away from focus on 3D IC and TSV processes, this year’s Advanced Packaging Conference, at SEMICON Europa, titled “Technologies, Manufacturing And Supply Chain”, will focus on more immediate issues facing the back-end sector of the semiconductor industries.

Advanced Packaging and Solid State Technology Applaud 2008 ACA Winners

Fri, 8 Aug 2008

Advanced Packaging Awards 2008: Signs of Hope

Fri, 8 Aug 2008
In a slowing economy, everyone looks for signs of hope for a strong future. Unfortunately at times like these, funding for R&D often takes a back seat to the basic needs of a company to conduct commerce and basically stay in business by doing the same things in the same way just to keep pace.

Tessera Introduces µZ-Ball Stacked Memory Package for Computing and Portable Electronic Products

Fri, 8 Aug 2002
Breakthrough Technology Delivers up to Eightfold Increase in Memory Density while Significantly Driving Down Stacked Package Costs

ESEC Introduces 5 µm Die Attach Solution

Fri, 8 Aug 2002
Cham/Switzerland, July 17, 2002 - ESEC, a leading provider of chip-assembly equipment and system solutions for the semiconductor industry, announces the introduction of a 5 µm Die Attach solution on its Micron 5003 Die and Flip Chip Attach Machine. This tool fulfills an important request from ESEC's customers and will insure more accurate bonding performance and overall superior results.

ESEC Introduces Revolutionary Bondhead Technology at Semicon West

Fri, 8 Aug 2002
Cham/Switzerland, July 18, 2002 - ESEC, a leading provider of chip-assembly equipment and system solutions for the semiconductor industry, will be presenting a revolutionary technology based on a rotating bondhead, at the world's largest semiconductor trade fair, Semicon West, taking place on July 17-19, 2002, in San Jose, California/USA.

Amkor and Unitive Form Manufacturing Alliance for Asian Supply Chain

Fri, 8 Aug 2002
CHANDLER, Ariz. and RESEARCH TRIANGLE PARK, N.C., July 18, 2002 -- Amkor Technology, Inc. (Nasdaq: AMKR) and Unitive, Inc. have expanded their two-year relationship by entering into a strategic manufacturing alliance to collaborate on turn-key manufacturing services using Unitive's wafer level packaging solutions and Amkor's advanced ackaging and test capabilities.

Universal Reveals New Flip Chip Capabilities

Fri, 8 Aug 2002
San Jose, California, July 22, 2002 -- Universal Instruments is launching its newest flip chip capabilities at SEMICON West 2002 in San Jose at booth 11627. These new offerings include the ability to process bumped devices directly from wafers using either ink dot recognition or wafer map input.

U.K. REPORT

Tue, 10 Oct 2002
U.K. Companies Find Packaging Niches LONDON The United Kingdom is not known as a critical location for semiconductor packaging, but there are numerous companies doing some interesting work there. On a recent vacation to the U.K., I took the opportunity to visit a few places: assembly and test subcontractor Atlantic Technology, equipment manufacturer DEK, and test and inspection specialist Dage Precision Industries. (October 8)

Author Guidelines for Advanced Packaging Magazine

Wed, 11 Nov 2002
As the premier technology source for advanced IC packaging, Advanced Packaging Magazine is dedicated to uncovering the latest research and technology for our global audience. We strive to help engineers and decision-makers in the packaging industry excel at their jobs by offering a unique mix of cutting-edge processes and new technology initiatives. We do this by focusing on materials, design, assembly and reliability, and by encouraging peer collaboration industry-wide.

Advanced Packaging Magazine now monthly

Mon, 1 Jan 2001
Nashua, NH - PennWell's Advanced Packaging magazine, the premier technology source for advanced semiconductor packaging, goes monthly starting with January issue.

Advanced Packaging launches Asia editions

Thu, 2 Feb 2001
NASHUA, N.H./TAIPEI, TAIWAN - PennWell Publishing and Arco Publishing introduce Chinese/English editions of Advanced Packaging magazine

Dates Set for APEX 2002

Fri, 3 Mar 2001
NORTHBROOK, IL - IPC announces that the APEX 2002 Exhibition and Conference will take place January 20-24, 2002 in San Diego, CA.

Postmark Entries by Monday for New Awards Program

Fri, 3 Mar 2001
NASHUA, NH - You can't win if you don't enter! Advanced Packaging magazine has launched a new awards competition to celebrate product excellence in semiconductor packaging. Entries need to be postmarked by this Monday (April 16).

EXCLUSIVE PACKAGING SUPPLEMENT

Thu, 4 Apr 2001
Packaging: The Next Step
The editors of Solid State Technology and Advanced Packaging magazines joined forces to create a special supplement for our readers. From electroplating to flip chip to the basics, we're certain you'll learn something in this must-read issue. Enjoy!

Attention SEMICON West Exhibitors!

Thu, 5 May 2001
If you are an exhibitor at SEMICON West 2001 this year in San Jose, don't miss this opportunity to have one of your debut products listed in our special July issue. Click here for more details.

THE 2001 ADVANCED PACKAGING AWARDS

Fri, 5 May 2001
Award Entries Surpass Expectations
In just a few short months, the industry will have a few more stars among them. Partnering with SEMICON West 2001, envelope seals announcing the winners of the the 2001 Advanced Packaging Awards program will be broken on Wednesday, July 18.

TECHNOLOGIST OF THE YEAR AWARD

Thu, 6 Jun 2001
Nominations Due August 1
Third Annual MicroElectronics Packaging Technologist Award sponsored by MEPTEC and Advanced Packaging magazine recognizes innovative technology in the world of semiconductor packaging and assembly. Click here for more information and a nomination form.

INDUSTRY ASSOCIATION LINKS

Wed, 6 Jun 2001
So When Is That Meeting Again?
Don't miss out on the latest news, events and meetings put together by your favorite associations. A list of assocations is right here ready for you to use.

THE 2001 ADVANCED PACKAGING AWARDS

Thu, 7 Jul 2001
And the Award Goes To...
At SEMICON West this year, we revealed the winners of The 2001 Advanced Packaging Awards program. Click here to see which products and companies won.

ATTENTION IMAPS 2001 EXHIBITORS

Mon, 7 Jul 2001
Editorial Call Deadline Today
If you are an exhibitor at IMAPS 2001 this year in Baltimore, don't miss this opportunity to have one of your debut products listed in our special September issue. The deadline is today. Click here for more details.

WEB EXCLUSIVE

Tue, 7 Jul 2001
Semi Dice Celebrates 25 Years of Service
LOS ALAMITOS, CALIF.
For the past 25 years, Semi Dice Inc. has been supplying bare die components to the hybrid, MCM and COB communities. In a recent interview with Advanced Packaging magazine, Mitch Myers, COO of Semi Dice, reflected on the past 25 years in the industry.

CALL FOR PAPERS

Thu, 8 Aug 2001
Wafer Level CSP and Flip Chip Packaging
The international workshop will be held in Stone Mountain, Georgia, on March 1-3, 2002. Abstracts are due November 19.

Who’s Who at BiTS, SEMICON China and IMAPS Device Packaging Symposium

Thu, 5 May 2008
The Advanced Packaging editors covered a lot of ground this spring as co-sponsors of the Burn-in and Test Socket (BiTS) Workshop in Mesa, AZ, attending SEMICON China in Shanghai, and the IMAPS Device Packaging Symposium in Scottsdale, AZ.

Cleaning High-power Electronics A closed-loop SOlvent-Based Approach

Thu, 5 May 2008
Flux residues must be be removed from flip chip components prior to subsequent processes to prevent malfunctions in high-power electronics.

Choosing the Best Bump for the Buck

Thu, 5 May 2008
Flip chip interconnect offers the advantages of smaller footprint on the PCB, improved electrical performance, reduced manufacturing steps at assembly, and excellent long-term reliability.

Solder Joint Reliability of High-end FCSiP

Tue, 7 Jul 2008
Challenges of high-end FCSiP include routability with acceptable signal and power integrity, package thermo-mechanical behaviors, and long term reliability performance.

NEW! THE WEEKLY WRAP FROM WAFERNEWS

Fri, 8 Aug 2001
A Few SEMICON Superlatives
Now that the dust has settled, we can report on some of the other interesting things from SEMICON West last month. Instead of the usual updates about who claimed the largest market share, read on for an update on Razor Scooters and booth decor.

THOUGHTS ON THE NEWS

Mon, 8 Aug 2001
Proliferation of Flip Chip Licensing
Recent announcements are an indication that the flip chip processes of a small number of companies are being adopted more and more by IC manufacturers and subcontract assembly houses. This is leading to process consolidation in the industry, with de facto standards arising.
Click here for analysis on this news and more.

ATTENTION APEX 2002 EXHIBITORS

Thu, 10 Oct 2001
Editorial Call Deadline Today
If you are an exhibitor at APEX 2002 this year in San Diego, don't miss this opportunity to have one of your debut products listed in our special January issue. Click here for more details.

PENNWELL MEMORIAL AWARD ESTABLISHED

Wed, 10 Oct 2001
PennWell Establishes Fire Engineering Award Honoring NYFD
PennWell Corp. (parent company of Advanced Packaging, SMT, and Solid State Technology magazines) has established the Fire Engineering Courage and Valor Foundation in honor of the firefighters from the September 11 tragedy.

About the Site

Thu, 6 Jun 2000
Advanced Packaging serves those in operations that integrate electronic component packages into circuitry of their end products. Advanced Packaging magazine debuted in 1992 to the IC packaging engineering community.

Advanced Packaging Magazine goes monthly starting with January 2001 issue!

Sun, 10 Oct 2000
Nashua, NH - PennWell Publishing has announced that Advanced Packaging magazine, the premier business-to-business technology source for advanced semiconductor packaging, will move to a monthly (12-time) schedule in 2001

Advanced Packaging Redesign

Wed, 11 Nov 2000
Check Out Advanced Packaging's New Redesign!

Package-on-package (PoP) with Through-mold Vias

Tue, 1 Jan 2008
Package on Package (PoP) stacking has become the preferred method for 3D integration of baseband ICs or ASICs with high-performance memory in mobile multimedia applications.

Intellectual Property (IP) Management in Electronic Design

Sat, 11 Nov 2008
Typically, when we hear the phrase intellectual property, we immediately think about theft and protection.

Discovery may lead to new methods to create nanowires

Thu, 11 Nov 2003
(November 13, 2003) West Lafayette, Ind.—A research team led by engineers at Purdue University and physicists at the University of Chicago has made a discovery about the formation of drops that could lead to new methods for making threads, wires and particles only a few nanometers wide.

ASAT, Amkor ink patent agreement

Fri, 11 Nov 2003
(November 14, 2003) Chandler, Ariz. and Hong Kong, China—Amkor Technology Inc.and ASAT Holdings Ltd. have entered into a comprehensive patent cross-license agreement for their respective quad flat no-lead (QFN) packaging technologies.

BTU achieves ISO 90001:2000 certification

Fri, 12 Dec 2003
(December 12, 2003) North Billerica, Mass. — BTU International Inc., a supplier of advanced thermal processing equipment for semiconductor packaging, surface mount and advanced materials processing, has achieved ISO 9001:2000 certification.

Fujitsu technology increases connection density

Mon, 12 Dec 2003
(December 15, 2003) Tokyo, Japan— Fujitsu Ltd. has developed technology that enables the formation of ultrafine-pitch 35-micron solder bumps, and high-precision flip chip bonding interconnection—increasing connection density approximately 50 times compared to conventional flip chip interconnections.

ASE's QFN packaging solution selected for advanced automotive functions

Wed, 12 Dec 2003
(December 17, 2003) Taipei, Taiwan—Advanced Semiconductor Engineering Inc. (ASE), a semiconductor packaging and testing company, announced that international semiconductor supplier austriamicrosystems' new low-power radio transmitter/receiver ASIC has been packaged using ASE's quad flat no lead (QFN) solution.

STATS, Simmtech form substrate alliance

Mon, 12 Dec 2003
(December 29, 2003) Singapore—ST Assembly Test Services Ltd. (STATS), an independent semiconductor test and advanced packaging service provider, has announced the formation of a strategic alliance with SimmTech Co. Ltd., a provider of semiconductor substrate material and telecommunications-related printed circuit boards (PCB) for substrate support and technology.

STATS appoints Eleana Tan Ai Ching to board

Wed, 12 Dec 2003
(December 31, 2003) Singapore—ST Assembly Test Services Ltd. (STATS), an independent semiconductor test and advanced packaging service provider, has appointed Eleana Tan Ai Ching as alternate director to non-executive director, Tay Siew Choon, effective January 2, 2004. She replaces Gan Chee Yen, who stepped down.

Machine Micro Lenses

Mon, 12 Dec 2007
The HR65D-VI series of machine micro lenses (MMLs) has been designed for high-resolution discrete part inspection in semiconductor manufacturing operations including die bonding, flip chip bonding, chip on glass and chip on film machining.

Scalable Dispensing Platform

Fri, 12 Dec 2007
The Spectrum S-920 series of scalable dispensing platforms adapts to the needs and requirements of high-volume microelectronics manufacturing and PCB assembly such as flip chip and CSP underfill. The platforms feature technologically advanced and integrated software and hardware control based on Fluidmove XP software with process control features.

Underfill Epoxy

Tue, 5 May 2006
123-38A/B-187 thermally conductive underfill epoxy is designed specifically for flip chip assembly. It is a nitride-filled, 2-component compound designed to release entrapped air rapidly during cure, resulting in a smooth, pinhole-free surface.

Freescale Orders SUSS Production Wafer-bonding System

Thu, 5 May 2006
Munich, Germany — Freescale Semiconductor recently ordered one of SUSS MicroTec's ABC200 automated production wafer-bonding systems. Silicon wafer bonding is a critical wafer-level packaging technology and an enabling technology for the mass production of cost-effective MEMS accelerometers for Freescale, so SUSS' automated production wafer bonders ideally suit their needs.

FlipChip International and Engent Form Strategic Alliance

Fri, 5 May 2006
Phoenix, AZ — Aiming to speed up development and deployment of 3-D wafer-level chip-scale packages(WLCSP) for integrated stack-die packages, FlipChip International (FCI) and Engent have formed a strategic alliance. FCI specializes in wafer-level bumping, while Engent's focus is 3-D flip chip assembly.

Platform-based Pick-and-Place

Tue, 5 May 2006
AdVantis XS mixes semiconductor and standard surface mount assembly in one machine with proprietary VRM linear motors for accuracy and repeatability at ±9 µm at ±3 sigma. AdVantis XS provides a low-cost alternative for placing flip chips and other advanced packages with high accuracy.

Substrate Possibilities and Limitations

Mon, 7 Jul 2006
By Meredith Courtemanche, assistant editor

A recent report analyzing delivery time length and prices of laminate flip chip build-up substrates found that increased demand for the substrate in 2005 created supply deficiencies. TechSearch International, who created the report, expects the problem to continue through 2006, and possibly into 2007 and 2008 as well.

Lead-free Wave Solder Alloy Gets Nod

Thu, 7 Jul 2006
(July 13, 2006) JERSEY CITY, NJ — LG Electronics DS Division approved the ALPHA Vaculoy SACX lead-free alloy, from Cookson Electronics Assembly Materials, for wave solder. They will use it as their lead-free wave solder in the CD-ROM division. The alloy demonstrates faster wetting speeds and lowered bridging defects, according to the company.

Advanced Packaging Award Winners Lauded

Fri, 7 Jul 2006
(July 13, 2006) SAN FRANCISCOAdvanced Packaging Magazine announced its Sixth Annual Advanced Packaging Awards recipients during a presentation at the San Francisco Museum of Modern Art on July 12, 2006. The nominees gathered at the Wattis Theater to accept awards and mingle at a reception that followed.

StratEdge Moves Facilities, Increases Offerings

Fri, 11 Nov 2007
(November 09, 2007) SAN DIEGO, CA — StratEdge, a designer and producer of semiconductor packages for microwave, millimeter wave, and high-speed digital devices, has moved its headquarters to new, state-of-the-art facilities. Still located in San Diego, the new site enables StratEdge to increase capabilities and space for package design, manufacturing, assembly, and test.

ASE, Infineon Produce Embedded Wafer-level BGA

Tue, 11 Nov 2007
(November 13, 2007) KAOHSIUNG, Taiwan, and NEUBIBERG, Germany — Advanced Semiconductor Engineering Inc. (ASE) and Infineon Technologies have developed a new packaging technology using embedded wafer-level ball grid arrays (eWLB) that reportedly offer an almost infinite number of contact elements in a 30% smaller package form vs. conventional lead-frame laminate packages.

FlipChip's EDC Enables Embedded Die Packaging

Wed, 11 Nov 2007
(November 14, 2007) PHOENIX, AZ — FlipChip International has introduced its new Embeddable Die Customization (EDC) technology targeted at readying integrated circuits and other devices for integration into emerging 3D packaging solutions. EDC enables the embedding of semiconductor devices within printed circuit boards or other interconnection schemes, thereby enabling lower profile, more reliable packaging schemes for applications including next generation cell phones.

Partnership Between CEA-Leti, S.E.T. Produces New Bonder

Thu, 11 Nov 2007
(November 15, 2007) SAINT-JEOIRE, France — S.E.T., the former SUSS MicroTec Device Bonder Division, has announced that the partnership between S.E.T. and CEA Leti has resulted in a radically new-generation, high-accuracy (0.5 µm), high-force (4000 N) device bonder for wafer diameters up to 300 mm. The FC300 bonder includes a built-in chamber for collective reflow in a gas or vacuum environment and also features nanoimprinting capabilities.

Cleaning to Increase Long-term Reliability

Fri, 11 Nov 2007
By Umut Tosun, ZESTRON America; and Stefan Strixner, ZESTRON Europe

Flip chip technology was introduced in the early 1960s and used in the computer manufacturing process. Development for automotive applications followed in the 1970s. Since then, the importance of the flip chip technology has increased due to size, performance, flexibility, and cost compared to other packaging methods.

Joanne Solomon Named Amkor Technology CFO

Mon, 11 Nov 2007
(November 19, 2007) CHANDLER, AZ — Amkor Technology Inc. has announced that Joanne Solomon has been appointed Corporate VP and CFO, succeeding Ken Joyce in that position. Solomon will continue to report to Joyce, who has been named to the new position of Chief Administrative Officer.

From the Editor
Keeping the Home Fires Burning

Mon, 11 Nov 2007
Most of our editors covered events in opposite time zones last week — Meredith Courtemanche in sunny San Jose, covering the 40th International IMAPS symposium, and Gail Flower, first in San Diego at the MEMS Congress, and then at Productronica in Munich, braving the cold, snow, and Deutsche Bahn strike. It was my turn to stoke the fires of Advanced Packaging from home base, with the help of Julie MacShane, our web news editor.

STATS ChipPAC to Offer Full Flip Chip Turnkey in China

Tue, 11 Nov 2007
(November 20, 2007) SHANGHAI, China — STATS ChipPAC Ltd. has announced that it is expanding its flip chip offering to provide customers a complete turnkey solution in China. STATS ChipPAC's operation in Shanghai, China will provide high -olume, low cost, full turnkey flip chip solutions encompassing wafer bump, sort, assembly, and final test.

SUSS MicroTec Receives Multiple Wafer Level Packing Equipment Orders from ASE

Wed, 11 Nov 2007
(November 21, 2007) MUNICH, Germany — SUSS MicroTec has received significant multiple orders for its lithography production equipment from the ASE Group, a provider of independent semiconductor manufacturing services in assembly and test.

AMD Opens Second Facility in Bangalore

Thu, 11 Nov 2007
(November 29, 2007) BANGALORE, India — AMD has announced the opening of a new 52,000-square-foot silicon design and platform R&D facility in Bangalore to accommodate a rising number of employees. The facility will also provide room for future growth. AMD will continue operating its first facility in the city, using the existing office space for administration, sales, and marketing staffs.

PennWell names Barach Group Publisher of Advanced Packaging

Thu, 2 Feb 2006
Nashua, NH — PennWell Corp. has named veteran publisher David Barach to the position of Group Publisher of Advanced Packaging Magazine, effective February 1st.

UTStarcom, Tessera Sign Licensing and Development Agreement

Thu, 2 Feb 2006
San Jose, CA — Tessera Technologies and UTStarcom have signed a licensing and development agreement, in which Tessera will license its Tessera Compliant Chip (TCC) semiconductor packaging technologies to UTStarcom. Both companies have collaborated on developing UTStarcom's MobileCard technology, which is an ultra-miniaturized mobile phone module that is equivalent to the size of two SIM cards.

INDUSTRY EVENT HIGHLIGHTS

Tue, 2 Feb 2006
MEPTEC Symposium Wrapup
By Julia Goldstein, Ph.D., Advanced Packaging contributing editor
Thermal management continues to be a "hot" area, and MEPTEC's second annual "The Heat is On" symposium on February 16th packed the hall despite the plethora of events covering the topic.
(February 28, 2006)

INDUSTRY EVENT HIGHLIGHTS

Mon, 3 Mar 2006
IPC/JEDEC Lead-free Conference
By Julia Goldstein, Ph.D., Advanced Packaging contributing editor
A combination of logistical and technical information was the focus of the IPC/JEDEC 12th International Conference on Lead Free Electronic Components and Assemblies, held March 7–9.
(March 13, 2006)

Indium to Showcase Offerings at IMAPS Device Packaging

Thu, 3 Mar 2006
Clinton, NY — Indium Corp. of America will exhibit its wafer and chip bumping and semiconductor packaging materials offerings at IMAPS' International Conference and Exhibition on Device Packaging (DPC 2006), to take place March 20–23, 2006, in Scottsdale, Arizona, at booth #35.

Registration Closing for iNEMI Roadmap Workshop

Wed, 3 Mar 2006
Herndon, VA — Registration for the International Electronics Manufacturing Initiative (iNEMI)'s 2007 Roadmap workshop, to be held together with SEMICON Europa in Munich, Germany, on April 5th, closes on March 28, 2006, barring full capacity prior to the date. The full-day meeting will give attendees a first-look at draft chapters of the 2007 Roadmap, including two key market segments and eight technology and infrastructure areas the Roadmap covers.

SUSS Installs Probe Systems in IMEC Research Center

Thu, 3 Mar 2006
Munich, Germany — SUSS MicroTec AG has installed PA300PS ProbeShield semiautomatic probe systems with ReAlign and ContactView technology and PA300 probe systems for RF-noise and S-parameter measurements at IMEC, a Leuven, Belgium-based nanoelectronics research center. The two companies will also collaborate on enhancing 300-mm probe systems in the future.

Device Packaging Conference Takes Off

Fri, 3 Mar 2006
Phoenix, AZ — The second annual IMAPS Device Packaging Conference, March 20–23, drew double the audience of last year. Sessions were crowded, exhibit space was sold out, and excitement was high. The conference, which this year incorporated the former IMAPS Flip Chip Workshop, offered three keynote speakers and five parallel tracks, with 26 sessions totaling about 100 papers.
By George Riley, Ph.D., contributing editor

IMEC and Georgia Tech Set Out to Solve Packaging Interconnect Gap

Tue, 10 Oct 2007
(October 16, 2007) Leuven, Belgium — IMEC and the Packaging Research Center (PRC) at Georgia Tech have put out the call for interested parties to join in their advanced research program on next-generation flip chip and substrate technology. The program addresses key IC-to-package-to-board packaging interconnect issues for 32nm ICs and beyond.

STATS ChipPAC Opens Second China Manufacturing Facility

Tue, 10 Oct 2007
(10/23/2007) SINGAPORE — STATS ChipPAC Ltd., an independent semiconductor test and advanced packaging service provider, today announced the grand opening of a second 371,000 sq. ft. manufacturing facility in Shanghai, China.

MEPTEC Finalizes Program for Substrates Symposium

Fri, 10 Oct 2007
(October 25, 2007) — MEPTEC, the MicroElectronics Packaging and Test Engineering Council, has finalized the program for its upcoming technical symposium titled, "Substrates: The Foundation of Semiconductor Packaging," at the Holiday Inn San Jose in San Jose, CA on Thursday, Nov 8th.

Test Socket for QFN Packages — Antares Advanced Test Technologies

Tue, 10 Oct 2007
Quatrix Kelvin QFN, the latest test socket from Antares, uses a single set of photolithographic-based contacts, with two distinct electrical connections per terminal, on an IC package. Developed for the migration of Kelvin-configuration testing of QFN packages, it suits test processes from the R&D environment to mass production down to 0.5 mm pitch.

Wafer Inspection System — RVSI

Tue, 10 Oct 2007
The WS-3800 Xpress, RVSI's next-generation model in its WS-Series Wafer Inspection Systems, is said to perform macro-defect inspection on up to 115 wafers-per-hour, offering high throughput while maintaining the same high-resolution, advanced macro-inspection capability as its predacessor.

ASE Orders Ultratech's Litho System for WLP Expansion

Thu, 11 Nov 2007
(November 1, 2007) SAN JOSE, CA — Ultratech Inc., a supplier of lithography and laser-processing systems used to manufacture semiconductor devices, has received an order from Advanced Semiconductor Engineering Inc. (ASE) for its 300mm, advanced-packaging lithography system.

Productronica 2007 Preview

Mon, 11 Nov 2007
Things just keep getting smaller. Two years ago at Productronica 2005, MicroNanoWorld was launched to address the increasing importance of micro-electronics production. It was continued at Electronica 2006, which alternates bi-annually with Productronica. This year, micro-electronics production is set to take center stage, as "Productronica 2007: Micro-Production in the Limelight" gets under way from November 13-16, 2007 at New Munich Trade Fair Center, Munich, Germany.

Keynote Explains 3-D Stacking

Mon, 4 Apr 2006
The main purpose of 3-D stacking of semiconductor die is not to save space — it is to save time. "To bring cells closer together by stacking them vertically, so that they are connected through only the thickness of the silicon," explained Philip Garrou, Ph.D., of RTI International. "Die stacking is not bringing more integration into the IC, but disassembling it."
By George Riley, Ph.D., contributing editor

DuPont, Fraunhofer Join Forces in Applications Development

Thu, 4 Apr 2006
Research Triangle Park, NC — DuPont Semiconductor Packaging & Circuit Materials and the Fraunhofer Institute for Reliability and Microintegration IZM recently joined together in an applications development agreement, in which Fraunhofer will help to refine and optimize the processes of DuPont's expanding wafer-level and chip scale packaging (CSP) materials portfolio.

IC Packaging Market Hits $23.1B in '05

Fri, 4 Apr 2006
San Jose, CA — In 2005, a reported 116 billion ICs were produced worldwide in 2005, bringing the IC packaging market's value to $23.1 billion, claims Electronic Trend Publications (ETP) in its latest report, The Worldwide IC Packaging Market — 2006 Edition. ETP reports that out of the 116 billion ICs, 37 billion were assembled by contract packaging companies, totaling $9 billion.

Taiwan Relaxing Chip Packaging Export Restrictions to China

Fri, 4 Apr 2006
Taiwan has announced it is removing restrictions on export of low-end semiconductor packaging and testing technology to mainland China, according to an Associated Press report. The news suggests significant progress in revision of Taiwan policies regarding semiconductor manufacturing technology transfers between the island and mainland China, which expired at the end of 2005.
By James Montgomery, News Editor, Solid State Technology Magazine

Photoresist Coating/Spray Nozzle

Mon, 4 Apr 2006
Nano Spray technology achieves conformal coating of extreme surface topographies, demonstrating conformal coatings of vertical via walls 300-µm deep and 100-µm in diameter. This enables further lithography steps in the bottom of the via to create through-wafer interconnects.

RIO Design Automation Releases Next-generation EDA Tool

Tue, 6 Jun 2006
Santa Clara, CA — Rio Design Automation Inc, an electronic design automation (EDA) company, announced that RioMagic, their chip design software tool, now includes full support for wire bonding and flip chip designs. This next-generation release reportedly has added rules-driven I/O sequencing, prototyping, and redistribution routing (RDL) support to its capabilities.

Another Word on Nano

Tue, 6 Jun 2006
The day after I wrote my last editorial entitled Nano-inspiration, I attended the MEMS and Nanotechnology session at the IMAPS New England Symposium, May 16, in Boxborough, MA. There was so much discussion about nano-hype, multiple definitions of nano, how nanomaterials are made, and what you can do with them that I wished the session had occurred a few days earlier.

SEMI Holds Meeting on MEMS Packaging Standards

Tue, 6 Jun 2006
(June 6, 2006) SAN JOSE, CA — If you're like most people who responded to SEMI's survey on MEMS packaging standards, you're not aware that SEMI has published three MEMS-related standards. Existing standards cover microscale fluidic systems, terminology, and wafer bonding. SEMI's MEMS technical committee has identified MEMS packaging as a task force area, and standardization efforts are just beginning.

EV Group and Brewer Science Seek Handling Solution

Fri, 7 Jul 2006
(July 21, 2006) ROLLA, MS and ST. FLORIAN, Austria — EV Group, which specializes in wafer bond systems, and Brewer Science Inc., a multidivisional technology company, are co-developing a solution for handling ultra-thin wafers. EV Group and Brewer Science's research for high-temperature advanced packaging processes involves temporary wafer bonding for the ultra-thin wafers.

Structural Desiccants

Mon, 7 Jul 2006
Designed to protect semiconductors in sealed environments that are vulnerable to moisture ingress through packaging material, NatraSorb 900 and Multiform desiccants remove water vapor and provide crush-resistance at up to 8,000 lb per in2. Multisorb produces the desiccants in pre-molded shapes or blanks for custom fabrication, to be integrated into semiconductor or packaging design.

Register Now for the Lead-free Success Stories Webcast

Fri, 1 Jan 2006
Nashua, NH — Advanced Packaging, in collaboration with Connector Specifier and SMT Magazines, will host a "Lead-free Success Stories" webcast on February 15, 2006, at 1:00 p.m. EST.

Palomar Names Hueners as New Company President

Mon, 1 Jan 2006
Carlsbad, CA — Palomar Technologies has named Bruce W. Hueners as its new president, having most recently held the position of COO. Since joining the company in 1981 when it was Hughes Aircraft, he has played significant roles in elevating Palomar to its market position in the optoelectronics industry, bringing about a series of acquisitions and partnerships, and in expanding the company's business in the U.S., Europe, and Asia.

Stepper Technology Enables Wafer-level Packaging Adoption

Fri, 11 Nov 2007
By Manish Ranjan, Ultratech Inc.

Semiconductor assembly and test service (SATS) houses, packaging foundries, and integrated device manufacturers (IDMs) are increasingly turning to wafer-level packaging (WLP) to address the demand for miniaturization, lower cost, enhanced functionality, and higher reliability in today's personal digital devices.

Clamshell Burn-in Sockets for Standard QFN Packages

Mon, 11 Nov 2007
The 880 series of clamshell burn-in sockets accommodates standard QFN packages down to 0.35mm pitch. The compression-mount clamshell is designed to allow chipmakers to remove or replace the sockets and retain production capacity if, for whatever reason, they were to damage them.

MEPTEC Substrates Symposium Focuses on Cost and Co-design

Mon, 12 Dec 2007
By Jeffrey C. Demmin, contributing editor

"Substrates: The Foundation of Semiconductor Packaging," MEPTEC's final technical symposium of 2007, identified cost and co-design as pivotal issues for the most critical component of semiconductor packaging.

EV Group and Brewer Science Demo New Ultrathin-Wafer Bonding Technology

Tue, 12 Dec 2007
(December 4, 2007) ST. FLORIAN, Austria, and ROLLA, MO — In their ongoing joint development work, EV Group (EVG) and Brewer Science Inc. unveiled they have demonstrated temporary wafer bonding capabilities for a wide range of backside processes, including through-silicon vias (TSVs) and backside metallization.

Cascade Microtech Names Geoff Wild New CEO

Fri, 12 Dec 2007
(December 7, 2007) BEAVERTON, OR — The Board of Directors of Cascade Microtech has named Geoff Wild president and CEO of the company. Wild has most recently been president and CEO of Nikon Precision Inc., a wholly owned subsidiary of Nikon Corp., where he has worked since 2002. He is expected to start at Cascade in January.

Flip Chip Bonder Equipment Market Briefing Announced

Fri, 12 Dec 2007
(December 7, 2007) PALO ALTO, CA — The Surface and Mount Technology Group at Frost & Sullivan will hold its 2007 Quarterly Analyst Briefing Presentation on the flip chip bonder equipment market on Wednesday, December 12, at 12:00pm CST/1 pm EST. As the call for higher integration and increased functionality of semiconductor packages continues, various end-user segments will likely become more receptive to flip chip technology, Frost & Sullivan said.

Nano-interconnect Progress

Fri, 12 Dec 2007
by George A. Riley, Contributing Editor
Nanotechnology is alive and creeping closer in university and industry research labs. Last month's Boston meeting of the Materials Research Society included 91 sessions with the term "nano" somewhere in the title. While most addressed material characteristics and laboratory techniques, two focused on carbon nanotube (CNT) large scale integration (LSI) device interconnections and related issues.

Tegal Announces Cluster Tool Sale

Tue, 6 Jun 2006
(June 21, 2006) PETALUMA, CA —Tegal Corp announced that a global leader in wafer-level packaging (WLP) purchased its Endeavor AT PVD cluster tool for under-bump metallization (UBM). Sputtered Films, a subsidiary of Tegal, received the order. The cluster tool is reportedly the fifth of its kind this customer has ordered.

Cadence and ARC Unite Against Sub-100-nm Problems

Fri, 6 Jun 2006
(June 30, 2006) ELSTREE, England and SAN JOSE, CA — Sub-100-nm processes require extra attention to ensure that designs are manufacturable with acceptable yield. Cadence Design Systems and ARC address this situation by integrating the Cadence Encounter digital IC design platform into ARC's ARChitect processor configuration tool. "The product integration will really help designers," said Lou Scheffer at Cadence.

Metamorphosis

Tue, 8 Aug 2006
As I pulled into the parking lot at PennWell this morning, I realized that I forgot my electronic pass card, and would have to go in through the main lobby. This has happened to me many times before, but for some reason — maybe it was the beautiful summer weather, or the fact that I took the elevator instead of the stairs — coming into the building that way reminded me of the first time I walked into the building for my job interview almost exactly a year ago.

IMAPS Consolidates ITRS and iNEMI Roadmaps

Wed, 8 Aug 2006
(August 9, 2006) WASHINGTON — The IMAPS Global Business Council (GBC) will undertake a project to interpret industry roadmaps' coverage of semiconductor packaging challenges. IMAPS began a study of two widely-used industry roadmaps — the International Technology Roadmap for Semiconductors (ITRS) and the roadmap of the International Electronics Manufacturing Initiative (iNEMI) — after discussions at IMAPS GBC workshops, and with their National Technical Committee (NTC).

Robert Haavind Wins ASBPE Gold

Thu, 8 Aug 2006
(August 10, 2006) Nashua, NH — Robert Haavind, editorial director for Solid State Technology Magazine, received a national gold award from the American Society of Business Press Editors (ASBPE). Haavind's editorials in the September 2005 and November 2005 issues of Solid State Technology — titled "Educating innovators" and "The future of energy" — were chosen as the best editorials for all business-to-business (B2B) magazines with a circulation under 80,000.

INDUSTRY NEWS ARCHIVE

Fri, 10 Oct 2003
Missed a Prior Industry News Article?
(Updated November 20)
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INDUSTRY NEWS

Fri, 10 Oct 2003
Bell Labs' creation may enable laser-on-chip applications (November 3, 2003) Murray Hill, N.J.—A team led by scientists from Bell Labs has built a novel semiconductor laser that may have numerous applications ranging from advanced optical communications to sensitive chemical detectors.

Click here for the full story.

ChipMOS to purchase test and assembly assets from FICTA

Tue, 8 Aug 2004
(August 24, 2004) Hsinchu, Taiwan—ChipMOS Technologies Ltd. has, through its subsidiaries ChipMOS Technologies Inc. and ThaiLin Semiconductor Corp., entered into an agreement with First International Computer Testing and Assembly Technology, Inc. (FICTA) whereby ChipMOS will purchase all of FICTA's testing and assembly assets from its Hsinchu, Taiwan operation. The transaction is valued at approximately US$30 million.

It's official: Amkor Technology acquires Unitive

Fri, 8 Aug 2004
(August 27, 2004) Research Triangle Park, N.C.—The acquisition announced last month of Unitive Inc. by Amkor Technology, Inc. is complete. Unitive, a leading provider of wafer level technologies and services for flip chip and wafer level packaging applications, now operates as a subsidiary of Amkor.

Novel way to make circuits at atomic scale

Mon, 8 Aug 2004
(August 30, 2004) Ithaca, N.Y.—Time is fast running out for the semiconductor industry as transistors become ever smaller and their insulating layers of silicon dioxide, already only atoms in thickness, reach maximum shrinkage. In addition, the thinner the silicon layer becomes, the greater the amount of chemical dopants that must be used to maintain electrical contact. And the limit here also is close to being reached.

THOUGHTS ON THE NEWS

Mon, 9 Sep 2004
Much More Than Moore
News Analysis by Jeffrey C. Demmin, Advanced Packaging contributing editor
I must admit that the title of this was stolen from Carlo Cognetti of ST Microelectronics, who gave a very interesting keynote talk titled that at the Napa KGD workshop recently.
(September 27, 2004)

MEPTEC to host microelectonics packaging symposium

Wed, 9 Sep 2004
(September 8, 2004) Mountain View, Calif.—The MicroElectronics Packaging and Test Engineering Council (MEPTEC) will host a technical symposium titled "Innovations in Equipment and Materials for Microelectronics Packaging: Complexity Drives Collaboration," on November 11, 2004 at the Hyatt San Jose in San Jose, Calif.

Ultratech receives 300 mm AP lithography-system orders from top Japanese semiconductor manufacturers

Fri, 9 Sep 2004
(September 10, 2004) San Jose, Calif.—Ultratech, Inc., a supplier of lithography and laser-processing systems used to manufacture semiconductors, announced that it received 300 mm advanced packaging lithography-system orders from three of Japan's top five semiconductor manufacturers. These companies will use the Ultratech tools—expected to ship by the end of 2004—for solder-bump applications.

ATMI sells Emosyn business to Silicon Storage Technology

Mon, 9 Sep 2004
(September 13, 2004) Danbury, Conn.—ATMI, Inc., a materials packaging supplier to semiconductor manufacturers, announced the sale of its Emosyn smart card business to Silicon Storage Technology, Inc. (SST) through a newly formed subsidiary, Emosyn International. Emosyn International will be held jointly by SST and ATMI.

IBM unveils next-gen lead-free packaging technique

Mon, 9 Sep 2004
(September 13, 2004) Munich, Germany and East Fishkill, N.Y.—IBM and SUSS MicroTec AG are working together to commercialize IBM's next-generation, lead-free semiconductor packaging technology, known as C4NP.

STATS ChipPAC achieves ISO/TS16949 certification

Thu, 9 Sep 2004
(September 23, 2004) Singapore and Fremont, Calif.— STATS ChipPAC Ltd.'s Singapore operation has achieved ISO/TS 16949:2002 certification by PSB Certification Pte Ltd. This certification marks the fifth STATS ChipPAC operation to do so.

AIT Leverages Patented Technology with High-density Package Family

Thu, 11 Nov 2004
(November 4, 2004) Singapore—Advanced Interconnect Technologies (AIT) announces the availability of a new family of etched leadless packages (ELP) that delivers design flexibility, increased density, and a reduced footprint.

SEMI SMG Reports Third Quarter 2004 Silicon Wafer Area Shipments

Thu, 11 Nov 2004
(November 4, 2004) San Jose, Calif.—Worldwide silicon wafer area shipments in the third quarter increased 1% sequentially and 25% from the third quarter of 2003, according to the SEMI Silicon Manufacturers Group (SMG) in its quarterly analysis of the silicon wafer industry. Silicon wafer area shipments totaled 1,629 million sq. in. during the most recent quarter, compared to the 1,619 million sq. in. in shipments reported during the previous quarter.

STATS ChipPAC Introduces Two New Leadframe Package Styles

Wed, 11 Nov 2004
(November 10, 2004) Singapore—STATS ChipPAC says that it has expanded its die stacking technology to include two leadframe-based performance packages, called the exposed pad thin quad flat pack (TQFP-ep) and the quad flat no-lead (QFN). Die stacking in TQFP-ep and QFN-type packages offers high performance and low cost for consumer, communication, wireless handheld, and portable consumer applications.

SRC and SIA Announce SoC Design Challenge

Thu, 11 Nov 2004
(November 11, 2004) The Semiconductor Research Corporation (SRC) and the Semiconductor Industry Association (SIA) announce their co-sponsorship of a contest open to North American university students and faculty to create novel, low-power SoC designs that demonstrate the value of greater systems integration in IC design.

Amkor, Unitive, and SECAP Conclude Venture for Wafer Bumping Line

Mon, 11 Nov 2004
(November 15, 2004) Munich, Germany—The Semiconductor Equipment Consortium for Advanced Packaging (SECAP) announces the conclusion of the venture between Amkor, its Unitive subsidiaries, and SECAP to establish the world's first high-volume, 300-mm electroplated solder bumping line using Unitive's technology.

Kulicke & Soffa Reports Revenue Down 24%, Bonder Sales Plunging 49%

Thu, 11 Nov 2004
(November 18, 2004) Willow Grove, Pa.—Kulicke & Soffa recorded net income of $29.1 million in the March quarter and $22.7 million in the June quarter, but now it's back to lean times. Reported net income of $3.3 million or $0.05 per fully diluted share on net revenues of $147.5 million for the quarter ended September 30, 2004.

Study Shows Capacity Expansion Required to Meet Growth in Flip Chip and Wafer-level Package Demand

Mon, 12 Dec 2004
(December 6, 2004) Austin, Texas — TechSearch International's new study, Flip Chip and Wafer Level Packaging Trends and Market Forecasts, projects a compound growth rate of over 28% in this market between 2004 and 2009. The report profiles drivers for the demand and requirements by market, investigates the state of the technology, and details the supply base.

FlipChip International achieves high-volume lead-free bumping and wafer-scale packaging production

Wed, 3 Mar 2004
(March 17, 2004) Phoenix, Ariz.—FlipChip International LLC has achieved high-volume production of lead-free bumping and wafer-scale packaging services for several customers, according to the company.

Amkor, CASIO team up to assemble/test wafer-level packages

Tue, 3 Mar 2004
(March 23, 2004) Chandler, Ariz.—Amkor Technology Inc., CASIO COMPUTER Co. Ltd. and CASIO MICRONICS Co. Ltd. have established business and technology licensing agreements for assembly and test of wafer-level semiconductor packages.

Unitive opens die level processing facility

Thu, 4 Apr 2004
(April 15, 2004) Research Triangle Park, N.C.—Unitive Inc. has opened a new Die Level Processing (DLP) facility, which the company says represents the industry's most advanced turnkey chip scale packaging capability. Integrated services include design, wafer bumping, multilayer redistribution, backgrind, dicing, probe, tape and reel, backside laminate, backside metallization and laser marking.

SEMI sees continued strength in bookings and billings

Tue, 4 Apr 2004
(April 20, 2004) San Jose, Calif.—North American-based manufacturers of semiconductor equipment posted $1.32 billion in orders in March 2004 (three-month average basis) and a book-to-bill ratio of 1.10, according to SEMI's latest report.

Advanced Packaging Awards

Tue, 4 Apr 2004
Advanced Packaging magazine is seeking the finest examples of creative advancement in technology in 19 critical areas. Be sure to enter your company's products and services! The deadline has been extended a week, so you still have time to enter. All entries must be postmarked no later than Monday, April 26, 2004. Click here for the Official Entry Form.

Semiconductor sales on the rise, SIA says

Mon, 5 May 2004
(May 3, 2004) San Jose, Calif.—Worldwide sales of semiconductors rose to $16.28 billion in March, a sequential increase of 4.4 percent from the $15.58 billion reported in February and a 32.3 percent increase from March of 2003, the Semiconductor Industry Association (SIA) reports.

U.S. Electronic Polymer Market to Reach $4.5 Billion in 2008

Thu, 5 May 2004
(May 13, 2004) Cleveland, Ohio—Demand for electronic polymer products is on target to expand 13.3 percent per year to $4.5 billion by 2008, according to Electronic Polymers, a recent study from The Freedonia Group Inc., an industrial research firm. Production of these products will require 510 million lbs. of resin valued at $2.2 billion, and growth is expected to be driven by a strong recovery in the semiconductor industry and a shift to new technologies.

WSC meets, recommends actions to promote industry growth

Mon, 5 May 2004
(May 17, 2004) Busan, Korea—The World Semiconductor Council, representing the European, Japanese, Korean, Taiwanese and U.S. semiconductor industries, met last week in Busan, Korea for its 8th annual meeting to address a number of public policy issues, including intellectual property, environment, trade and other issues.

Tessera Leapfrogs WLP Competition

Tue, 11 Nov 2005
By George Riley, Ph.D., Advanced Packaging contributing editor
Tessera Technologies' November 1, 2005 announcement that they will purchase the intellectual property and various assets of Shellcase Limited proves this chip scale package pioneer is determined to establish a similar leading position in wafer-level packaging (WLP).

IWLPC Highlights

Wed, 11 Nov 2005
By George Riley, Ph.D., Advanced Packaging contributing editor
San Jose, Calif. — The second International Wafer Level Packaging Conference, held Nov. 3–4 in San Jose, highlighted industry changes since last year. Talk was of rapid growth, new market opportunities, and technology improvements. The keynote speaker stimulated that enthusiasm by discussing the just-announced purchase of Shellcase Limited assets.

Lead-free Forum and Workshop Highlights Compliance Challenges

Tue, 11 Nov 2005
By Françoise von Trapp, Advanced Packaging Associate Editor
Haverhill, Mass. — Like it or not, agree with it or not, or prepared for it or not, lead-free is a reality and it's time to get on board. This was the overall message at last week's Lead-free Technology Forum and Workshop. The event was sponsored by Dage Precision Industries, Ltd., and hosted by the Circuit Technology Center in Haverhill, Mass.

Advanced Micro-CT X-ray Inspection Scans in 3-D

Tue, 11 Nov 2005
Stamford, CT — FEINFOCUS, a COMET business unit, and Xradia, a developer of ultra-high-resolution X-ray imaging systems for 3-D tomography, have joined forces to develop an advanced 3-D X-ray inspection technology for the semiconductor packaging and medical device industries. The microXCT defect detection system uses non-destructive 3-D tomography to view the complete structure of advanced packages, scanning packages in 3-D at full resolution.

Newport Updates Financial Guidance for Q4 2004

Thu, 12 Dec 2004
(December 30, 2004) Irvine, Calif. — Newport Corp. has updated its financial guidance for Q4 2004, confirming that it expects its sales for Q4 2004 to be within the range announced in October 2004 of $100 million to $103 million.

Advanced Packaging Wishes You a Happy New Year!

Thu, 12 Dec 2004
The editors and staff at Advanced Packaging would like to wish you all a happy and healthy 2005.

APEX EXTRAVAGANZA

Fri, 3 Mar 2003
The following companies will be exhibiting these products at APEX 2003, taking place Monday, March 31 through Wednesday, April 2 in Anaheim, Calif. Be sure to visit them to see their latest innovations, and pick up SMT's official Show Daily for more product coverage. ( March 28)
Click here for these and more product briefs.

SEMICON WEST 2003 SYMPOSIUM

Tue, 7 Jul 2003
Tessera 3-D Symposium Demonstrates Greater Supply Chain Cooperation, Advanced Packaging Media Sponsor SAN JOSE, CALIF. Driven largely by the wireless handset market and emerging high-performance computing requirements, the semiconductor industry is increasingly looking to advanced packaging solutions ... (July 17, 2003)

ADVANCED PACKAGING AWARDS 2003

Tue, 7 Jul 2003
Semiconductor Companies Take Center Stage at Advanced Packaging Award Program SAN JOSE, CALIF. On Wednesday, July 16, Advanced Packaging magazine honored top supplier companies and their staffs with the 2003 Advanced Packaging Awards at a ceremony held here at the McEnery Convention Center. (July 22, 2003)

A NOTE FROM THE EDITOR

Fri, 7 Jul 2003
(July 16, 2003) Welcome to Day 1 of From the SEMICON West Tradeshow Floor, your e-show daily for the backend of SEMICON West in San Jose. For the Final Manufacturing (San Jose) portion...

SEMI WEST NEW PRODUCTS (PART 1 OF 3)

Fri, 7 Jul 2003
SEMI WEST NEW PRODUCTS (PART 1 OF 3) The following is a selection of new products that you will see on the exhibitor floor at SEMICON West in San Jose, Wednesday, July 16, to Friday, July 18. See the SEMICON WEST EXHIBITOR LIST in the next section of this newsletter for booth numbers.

SEMICON WEST (BACK END) DAY 2 NEWS

Wed, 7 Jul 2003
(July 17, 2003) Asymtek Awarded Patents for Underfill Dispensing and Conformal Coating Techniques; BTU Debuts Integrated Line for Reflow Processing; Carsem Receives ISO/TS 16949:2002 Quality Management Systems Certification; Future Growth in Semiconductor Manufacturing will Rely on International Co-operation, Not Regional Rivalries; Camstar and Pilgrim Software Announce Partnership

Xilinx issues product advisory

Fri, 1 Jan 2004
(January 16, 2004) San Jose, Calif.—Xilinx Inc. recently issued a product advisory potentially affecting certain lots of its Viretex-II Pro and XC2V6000 products using flip chip technology. The affected parts were manufactured using improper solder material that may cause random upset of device configuration.

Amkor chosen by Oki for advanced packaging solutions

Tue, 1 Jan 2004
(January 20, 2004) Chandler, Ariz.—Oki Electric Industry Co. Ltd. has chosen Amkor Technology Inc. to assemble and test single- and stacked-die chip scale packages for its broad range of advanced semiconductor devices, including microcontrollers, application-specific digital audio controllers and SoC ASICs.

ASAT to provide flip chip technology to Shanghai Fudan Microelectronics

Tue, 1 Jan 2004
(January 20, 2004) Pleasanton, Calif.—ASAT Holdings Ltd. and ASAT Inc., global providers of semiconductor package design, assembly and test, will provide flip chip land grid array (LGA) technology to Shanghai Fudan Microelectronics Co. Ltd. (Hong Kong, China) for multimedia applications.

Amkor reports surge in demand, plans capacity expansion

Fri, 1 Jan 2004
(January 23, 2004) Chandler, Ariz.— Amkor Technology Inc., citing an accelerating demand for advanced packaging solutions for cell phones and other handheld applications, is aggressively expanding capacity for stacked chip-scale packages (S-CSPs). Amkor's factories in Korea and Japan already produce stacked packages. The company will install S-CSP capacity in its factories in Taiwan and China early in 2004.

Tessera and Oki sign licensing agreement

Mon, 1 Jan 2004
(January 26, 2004) San Jose, Calif.—Tessera Technologies Inc. and Oki Electric Industry Co. Ltd. have signed a new licensing agreement. Oki and their subcontract assemblers plan to use Tessera's semiconductor packaging technology in devices such as microcontrollers and ASICs.

'SiPs or SoCs?' conference is coming right up

Tue, 2 Feb 2004
(February 3, 2004) Why do companies continue to work on development of SoC solutions rather than focusing on a SiP solution? This will be the focus of an upcoming 1-day technical symposium presented by the MicroElectronics Packaging and Test Engineering Council (MEPTEC) organization on February 19. Some of the speakers of the upcoming conference have offered their insights into the pros and cons of the two technologies.

ChipPac, STATS plan merger

Tue, 2 Feb 2004
(February 10, 2004) Singapore and Fremont, Calif.—STATS and ChipPAC have signed a definitive agreement to merge in a stock-for-stock transaction that will result in an independent semiconductor assembly and test solutions company that is one of the larger test houses in the world.

K&S sells advanced packaging segment

Tue, 2 Feb 2004
(February 10, 2004) Willow Grove, Penn.—Kulicke & Soffa Industries Inc. has sold all the assets associated with its advanced packaging technology segment, which consisted solely of the flip chip business.

Blending plastics, semiconductors to form flexible chips

Thu, 3 Mar 2004
(March 11, 2004) Fayetteville, Ark.—Disposable cell phones, flexible computer screens and wristwatch computers could be within technology's grasp if organic plastics and electronic materials are combined to share a few traits.

Plastic packaging materials market set for growth, led by laminate substrates

Thu, 3 Mar 2004
(March 11, 2004) San Jose, Calif.—The market for semiconductor packaging materials is expected to grow from $7.9 billion in 2003 to $11.7 billion by 2008, according to a just-released study, 'Global Semiconductor Packaging Materials Outlook,' by SEMI and TechSearch International.

China IC packaging and testing firm to offer chip-scale packaging

Mon, 10 Oct 2004
(October 4, 2004) Taipei—China-based Jiangyin Changdian Advanced Packaging (JCAP) is setting up chip-scale packaging lines and wafer-bumping lines, slated for mass production next year.

STATS ChipPAC reaches milestone in wafer-level chip scale package (WLCSP) production

Tue, 10 Oct 2004
(October 5, 2004) Singapore and Fremont, Calif.—STATS ChipPAC announces reaching a milestone in its scale-up of full turnkey wafer-level chip scale package (WLCSP) wafer bumping, probe, and back-end processing services, with production run rates exceeding 4 million packaged units per month.

MEPTEC to Offer Technical Symposium in November

Fri, 10 Oct 2004
(October 8, 2004) San Jose, Calif.—MEPTEC, the MicroElectronics Packaging and Test Engineering Council, plans to shake things up a bit with its next technical symposium, titled "Innovations in Equipment and Materials for Microelectronics Packaging: Complexity Drives Collaboration," on November 11, 2004 at the Hyatt San Jose.

Kester to Hold Lead-free Mini-Clinic at Mexitr

Wed, 10 Oct 2004
(October 13, 2004) Des Plaines, Ill.—As the WEEE and RoHS directives take effect in Europe, and with the increased production of lead-free products in Asia, lead-free assembly in North America is gaining momentum.

Kulicke & Soffa Announces New Maunfacturing Facility in Taiwan

Fri, 10 Oct 2004
(October 15, 2004) Willow Grove, Pa.—Kulicke & Soffa Industries will hold a grand opening event on October 15, 2004 at its new state-of-the-art probe card manufacturing facility located in Hsin Chu, Taiwan.

EV Group and Datacon Announce Cooperation on Advanced Chip-to-wafer Technology

Fri, 10 Oct 2004
(October 15, 2004) Scharding and Radfeld, Austria—EV Group, a supplier of wafer-bonding and lithography equipment, and Datacon Technology AG, a supplier of flip chip and die bonding equipment, announces a development agreement in the field of advanced-chip-to-wafer (AC2W) technology. The two companies also have agreed on joint strategic marketing and sales activities to promote the cooperation.

GlobalSpec Announces Expanded Partnership with PennWell

Mon, 11 Nov 2004
(November 1, 2004) Troy, N.Y.—GlobalSpec, the specialized search engine and online resource for engineers and technical buyers, announces an expanded partnership with PennWell Corporation, a business-to-business media company providing print and online publications across multiple industries.

Semiconductor sales at highest point since July 2000

Tue, 6 Jun 2004
(June 1, 2004) San Jose, Calif.—Worldwide sales of semiconductors rose to $16.94 billion in April, a sequential increase of 4.1 percent from the $16.28 billion reported in March, and a 36.6 percent increase from April 2003, according to the Semiconductor Industry Association (SIA). April is traditionally a strong month for semiconductor sales.

Kester, Flip Chip International Collaborate on Development of New Wafer Bumping Solder Paste

Mon, 6 Jun 2004
(June 14, 2004) Des Plaines, Ill. and Phoenix — In a joint collaboration, Kester and FlipChip International (FCI) have worked side by side to introduce SE-CURE 7501, a low void wafer bumping solder paste formula designed for FCI's proprietary wafer bumping application.

Cookson to implement tin surcharge

Fri, 7 Jul 2004
(July 2, 2004) Jersey City, N.J.—Cookson Electronics Assembly Materials will implement a tin surcharge on all invoices for ALPHA solder paste as soon as the London Metal Exchange (LME) price exceeds $9,500 per metric ton. The surcharge will cover the dramatic increase in the cost of tin, which has more than doubled in the last six months versus the previous two-year average.

ASAT to present paper at IMAPS Flip Chip conference

Tue, 7 Jul 2004
(PRNewswire-FirstCall, June 15, 2004) Pleasanton, Calif.—ASAT Holdings Limited, a global provider of semiconductor assembly, test and package design services, announced its participation at the International Microelectronics and Packaging Society (IMAPS) Flip Chip Technology Conference, which takes place June 24 in Austin, Texas.

Semiconductor industry giants sign licensing agreement

Wed, 7 Jul 2004
(Business Wire, July 7, 2004) San Jose, Calif.—Tessera Technologies, Inc., a semiconductor packaging technology developer, announced that it signed a technology licensing agreement with NEC Electronics Corporation of Kawasaki, Japan, one of the world's ten largest semiconductor manufacturers. NEC Electronics uses Tessera's technology in a broad range of its semiconductor devices, including application-specific integrated circuits and logic devices.

SEMI names new chairman

Wed, 7 Jul 2004
(July 14, 2004) San Francisco, Calif.—SEMI, an international association for companies in the microelectronics and display industries, announced yesterday the appointment of Tetsuro (Terry) Higashi as its new chairman of the board of directors. The results of the association's annual elections were released at the SEMICON West exposition in San Francisco. Higashi, current chairman of Tokyo Electron Limited, succeeds George Chamillard, who served as SEMI's chairman for the past year.

Amkor to acquire Unitive

Wed, 7 Jul 2004
(July 21, 2004) Chandler, Ariz.—Amkor Technology, Inc. signed agreements to acquire privately-held North Carolina-based Unitive, Inc., and to obtain a majority interest of approximately 60 percent in Unitive Semiconductor Taiwan Corporation (UST), a joint venture between Unitive and various Taiwanese investors. Unitive, Inc. and UST are among the world's leading providers of services for flip chip and wafer level packaging applications.

FROM THE EDITOR

Mon, 7 Jul 2004
(July 19, 2004) Nashua, N.H.—We have just returned from SEMICON West. Most of the exhibitors were pretty excited about the bustle of people stopping by their booths to see what's new in back-end assembly equipment and materials.

'Silicon Border' on the agenda at SEMICON West

Fri, 7 Jul 2004
(July 9, 2004) San Francisco, Calif.—At SEMICON West 2004, Mexican Secretary of the Economy Fernando Canales Clariond, Baja California Governor Eugenio Elorduy Walther, and developers will discuss their plans to create a 10,000-acre industrial park for the high-tech industry along the shared border between Mexico and the United States.

2004 Advanced Packaging Awards announced

Thu, 7 Jul 2004
(July 19, 2004) Nashua, N.H.—Advanced Packaging magazine has released the names of the winners of its 2004 Advanced Packaging Awards. Electroglas, Inc., ASAT Holdings Limited and Robotic Vision Systems, Inc. are among the companies that received honors for innovations in advanced packaging technology. The awards ceremony took place July 14 at the SEMICON West 2004 exposition in San Jose, California.

Wafer-level packaging...whose job is it anyway?

Tue, 8 Aug 2004
(August 3, 2004) Santa Clara, Calif.—"Where will wafer-level packaging take place?" That is among the topics of the next MicroElectronics Packaging and Test Engineering Council (MEPTEC) 1-day technical symposium coming up on August 19th in Santa Clara, Calif. MEPTEC will bring together experts from various areas of the wafer-level packaging/processing fields to help answer that and other questions related to wafer-level packaging.

KIC to co-sponsor lead-free workshop

Mon, 8 Aug 2004
(August 16, 2004) San Diego, Calif.—KIC, a leader in thermal process development and control software, will co-sponsor a lead-free workshop on October 13-14, 2004, at the Engent facility in Norcross, Georgia. Other co-sponsors include Engent, Henkel Technologies and Speedline Technologies.

AIM forms new semiconductor packaging materials division

Tue, 8 Aug 2004
(August 17, 2004) Cranston, R.I.—AIM announced today the formation of AIM Semiconductor Packaging Materials. This new division is a direct subsidiary of AIM Specialty Materials, which specializes in indium- and gold-alloys for a variety of joining applications.

Speedline announces new allianc