(March 5, 2008) In the semiconductor industry, device characterization or screening occurs through the use of two related tests: burn-in and elevated temperature device characterization, with both tests using temperatures >99°C: the first to accelerate device failure modes that could be related to those in the field, and the second to simulate functional device behavior while characterizing its performance level.
By Scott D. Szymanski, March Plasma Systems
Commercially available plasma treatment systems can be used for a variety of wafer-level packaging (WLP) process steps including removal of photoresist residue after development (i.e. descum); organic, metal, and oxide contamination removal; wafer surface cleaning; and other processes. Through various alterations to the plasma chemistry or chamber configurations, these systems meet demanding WLP processing requirements.
ON Semi believes that its SANYO Semiconductor division's Thai operations in the Rojana Industrial Park have been severely damaged by Thailand's flood. Another facility in Bang Pa In, previously unaffected, is now flooded. ONNN says none of its employees in Thailand have been endangered by flood waters on-site.
Spansion Inc. (NYSE:CODE) will consolidate its 2 semiconductor assembly and test services (SATS) operations, closing its facility in Kuala Lumpur, Malaysia, to reduce costs by about $30 million annually.
Multitest debuted the Quad Tech concept, next-generation vertical contact technology with a barrel-less architecture.
Global Unichip Corp. (GUC; TW:3443) refined its business and technology model to become a full-service, flexible ASIC company. President Jim Lai refers to the model as GUC's branded Flexible ASIC Model, covering SoC integration, implementation methodologies, and integrated manufacturing.
Levi & Korsinsky is bringing a class action lawsuit against OmniVision Technologies Inc. (NASDAQ:OVTI) on behalf of stockholders that allege that OmniVision failed to disclose properly the loss of an exclusive contract with Apple for image sensors, in-house production delays, as well as other counts.
North Dakota State University, Fargo, researchers have developed a packaging technology using Thermo-Mechanical Selective Laser Assisted Die Transfer (tmSLADT) to reduce the size and cost of microelectronics packages.
NEXX Systems shipped a Stratus electrochemical deposition tool to Nantong Fujitsu Microelectronics Co. Ltd. (NFME), based in Jiangsu province, China. NFME will use the Stratus for copper pillar and RDL advanced packaging applications.
At the IMAPS 44th International Symposium on Microelectronics in Long Beach, CA, Voya Markovich, well-known industry PCB and packaging expert, took over the reins as the organization
Steven J. Adamson, marketing specialist with Nordson ASYMTEK, received the Daniel C. Hughes, Jr., Memorial Award, for the greatest contribution to IMAPS and the microelectronics packaging industry.
Cascade Microtech Inc. debuted InfinityQuad, a multi-contact probe head capable of automatically probing aluminum (Al), copper (cu), or gold (Au) pads as small as 30 x 50
Analog Devices Inc. (ADI) introduced a packaging technology for digital isolators that achieves a minimum of 8mm creepage distance required by global industry standards to ensure safe operation in high-voltage medical and industrial applications.
IMAPS 2011, the 44th International Symposium on Microelectronics, will take place in less than one week at the Long Beach Convention Center. Ahead of the show, here are some of the highlights for attendees.
Amkor will acquire Toshiba Electronics Malaysia Sdn. Bhd., Toshiba
Cascade Microtech (NASDAQ:CSCD) completed the sale of its test socket manufacturing business for $550,000 to R&D Interconnect Solutions. Cascade's board of directors also authorized a stock repurchase program under which up to $2,000,000 of its common stock may be repurchased.
By R. Wayne Johnson, Ph.D., Auburn UniversityWhile $4/gal.gasoline prices have dropped, it is inevitable they will rise again. So what does this have to do with advanced packaging? A lot! While we hear discussions of alternate energy, we will continue to use oil for the foreseeable future. Electronics (and advanced packaging) are important for measurements during well drilling and for production management over the life of the well.
GLOBALFOUNDRIES entered into a strategic partnership with Amkor (NASDAQ:AMKR) to develop integrated semiconductor assembly and test processes for advanced silicon nodes. The aim is integrated fab-bump-probe-assembly-test steps that can be commercialized across multiple customers and end-market applications.
Cabot Corp. (NYSE:CBT) will sell its Supermetals business to Global Advanced Metals (GAM), a supplier of tantalum ore to the Supermetals business.
The SMTA will host conference events with Amkor, Research in Motion, and TechLead Corporation on package-on-package (PoP) 3D stacking at SMTA International (SMTAI), October 16-20 in Fort Worth, TX.
SATS provider STATS ChipPAC Ltd. (SGX-ST:STATSChP) honored its top materials and equipment suppliers in 2010, recognizing "intense focus and commitment to performance, quality, cycle time, and cost."
National Instruments (Nasdaq: NATI) added per-pin parametric measurement unit modules and source measure unit modules to its PXI platform for semiconductor characterization and production test.
Semiconductor packaging and test provider STATS ChipPAC Ltd. (SGX-ST: STATSChP) welcomed Pasquale Pistorio as an advisor to its Board of Directors.
Compugraphics International is widening its line of photomasks to include larger-area products up to 16 in2, responding to customer demand for wafer-level packaging and other semiconductor and optical applications.
The annual Known Good Die (KGD) conference, taking place Nov. 10 in Santa Clara, CA, will address semiconductor die testing, assembly, manufacturing, and business challenges, with the tagline "KGD in an Era of Multi-Die Packaging and 3D Integration."
Nemotek Technologie uncrated the Exiguus, with a VGA wafer-level camera integrating wafer-level optics assembled with CMOS image sensors (CIS).
Johnstech International Corporation is rereleasing the configurable ROL 200K (Kelvin) Test Contactor as the ROL 200KR Kelvin-Ready Test Contactor for both pad and leaded style devices.
Tessera Technologies appointed Anthony J. Tether, Ph.D., to its board of directors. Tether is CEO of The Sequoia Group, and has held executive positions at DARPA and Ford Aerospace Corp., among others.
SEMI will hold the first-ever SiP Global Summit, September 7-9, co-located with SEMICON Taiwan. Three forums cover system in package (SiP) test, the "3D IC era," and the requirements of mobile electronics.
Nordson MARCH and Science College of Donghua University, Shanghai, China launched a joint laboratory for plasma research and education. The college and supplier will share equipment, research projects, personnel resources, and additional resources as needed.
Amkor's Ron Huemoeller shares his thoughts about two panels from SEMICON West, on 2.5D silicon interposer packaging technologies and its supply chain, and 3D packaging technology and its ecosystem.
The University of Waterloo, Ontario, through the Applied Research and Commercialization Initiative, is supporting several companies researching and developing new products. One company receiving aid from the school is Microbonds, maker of semiconductor bonding wire.
Multitest launched a 16-site tri-temp pick-and-place handler, the MT9510 x16. The platform can be kitted to test a range of semiconductor packages.
Amkor has extended its Quad Flat No-Lead (QFN) package design kit to be the first such kit available for Agilent Technologies' Advanced Design System (ADS) electronic design automation software.
Industry efforts to transition from gold to copper wire are accelerating as prices for gold continue to spike to near record levels, notes TechSearch International in a new report.
Nomura Principal Finance Co. Ltd., a wholly owned subsidiary of Nomura Holdings Inc., transferred all the shares it owns in Eastern Co. Ltd. to Eastern.
Apple Inc.'s iPad has thus far thwarted competitive tablets in design efficiency, according to an IHS iSuppli Teardown Analysis of eight tablet models from IHS. Major savings come from Apple's control of chips like SDRAM and applications processors.
Great Lakes Engineering will supply DEK's VectorGuard packaging and surface mount assembly stencil system to customers in 32 states and 3 countries.
Agilent and UC Davis established the Davis Millimeter Wave Research Center to develop advanced mm wave and THz systems for radar, sensors, imaging systems, communications and integrated passive devices (IPDs) found in electromagnetic metamaterials and antennae.
Data I/O Corporation (NASDAQ: DAIO) debuted the RoadRunner3 in-line programming system, a just-prior-to-placement programming tool with modules to automate processes and eliminate operator interventions.
SATS provider Unisem purchased a LTX-Credence PAx RF Test System for its Sunnyvale, CA, test development center, joining other recent test/wafer equipment purchases at the site.
Texas Instruments has shipped more than 30 million units of its PowerStack packaging technology, a combination of chip stacking and clip bonding that is designed to improve performance and chip densities in power management devices.
3D semiconductor packaging processes involve various groups, and standards are important in the hand-offs between them, explains Mark Berry, sales director at Metryx. He covers how to use metrology to protect wafer yields in 3D packaging.
Nippon Micrometal Corporation (NMC) licensed their single-layer-palladium (Pd) coated copper (Cu) bonding wire for LSI packaging to Tanaka Denshi Kogyo K.K., bonding wire manufacturer and traditionally a competitor.
Optomec Aerosol Jet product manager Mike O’Reilly will give a presentation titled "Aerosol Jet Printing as an Alternative to Wire Bond and TSV Technology for 3D Interconnect Applications" at the IMAPS Device Packaging Conference on March 9.
IMT introduced its hermetic gold-to-gold (Au-Au) thermo compression bonding for wafer-level packaging (WLP). In development for nearly a year, this bond is being actively used in production.
The new gold/tin (AuSn) process from Stellar Industries is ideally matched to Stellar’s proprietary CPU copper on AlN submounts with its sharp guillotine edge for precise edge alignments.
Multitest received its fifth full purchase order for its InCarrier device transfer system with InStrip test handling system adapted to metal frame-based carriers.
The Unifire 7900IR provides 3D inspection of wafer-scale packaging features as well as registration for wafer-to-wafer bonding applications for use in advanced wafer scale packaging process control.
Tessera Technologies Inc. (NASDAQ:TSRA) announced that on February 17, 2011, it sent Amkor Technology, Inc. an official notice of termination of their license agreement with Tessera. The two companies are currently in arbitration regarding multiple issues.
Jamal Izadian, co-founder & president of RFCONNEXT, makes the case for shaped membrane transmission lines (SMTL) for use in high-speed 3D packaging applications. SMTL supports and improves flip-chip, micro-bumping, wafer thinning, system-in-package (SiP), package-on-package (PoP), and other packaging processes by extending the bandwidth and high-speed limits of these technologies.
inTEST Corporation (NASDAQ: INTT) subsidiaries, Temptronic and Sigma Systems, both in Sharon, MA, will begin operating under the umbrella trade name, inTEST Thermal Solutions Corp.
STATS ChipPAC launched fcCuBE technology, an advanced flip chip packaging technology that features copper (Cu) column bumps, bond-on-lead (BOL) interconnection and enhanced assembly processes. STATS ChipPAC claims the flip chip package is cost-comprable to standard packaging processes, and compatible with shrinking semiconductor device nodes down to 28nm.
InVisage Technologies, image sensor technology start-up, received its series C round of venture funding, led by Intel Capital. The undisclosed amount will be used to bring the company's quantum-dot-based QuantumFilm technology and products into mass production.
Minco Technology Labs, hi-rel semiconductor die processing, packaging and test provider, appointed board member Bill Bradford as president and CEO.
Samsung Electronics began producing embedded multi-chip package (eMCP) memory for use in entry- to mid-level smartphones. The products use low power double-data-rate 2 (LPDDR2) 30nm DRAM and 20nm NAND flash memory.
Increased I/O density, power/performance reqs, and other factors are increasing use of flip chip, 2.5D and 3D technologies, a boon to packaging subcontractors. But they face a challenge from foundries, and must navigate under-utilization of wire bonding capacity.
The SMTA released its call for presenters for SMTA International (SMTAI) 2012, October 14-18 in Orlando, FL. The association, along with Chip Scale Review magazine, also announced the keynote for the International Wafer-level Packaging Conference (IWLPC), held November 5-8, San Jose, CA.
Packaging house Inari Berhad signed an MOU to acquire Amertron Global, which operates in the Philippines and China providing microelectronics and optoelectronics manufacturing services.
STATS ChipPAC held the groundbreaking ceremony for a new factory in Singapore, which will enable STATS ChipPAC to expand its manufacturing capabilities for advanced wafer level technologies.
Tessera Technologies (TSRA) received a letter from Starboard Value and Opportunity Master Fund Ltd, intending to nominate 3 candidates for the TSRA Board of Directors. Tessera issued a response, saying that it has the right Board and management team in place.
With many advanced packaging processes taking place on the semiconductor wafer, the traditional supply chain of front-end fab at the foundry and back-end fab at the packaging and test house is falling apart. The ConFab session,
As packaging has played a larger and larger role in chip performance, form factor, and capabilities, The ConFab has increased its focus on back-end processes. Cue
Displaybank published a 2009-2014 analysis of LED packages, the finished LED components used in various applications. While LED package units will grow steadily through the forecast period, revenues will remain mostly flat from 2010 to 2013.
Mentor Graphics collaborated with Austria Technologie & Systemtechnik (AT&S) to implement AT&S Embedded Component Package (ECP) process in Mentor Graphics
Increased demand for product functionality is driving up IC packaging revenue faster -- a 9.8% compound annual growth rate (CAGR) -- than IC unit growth -- 7.3% CAGR 2010-2016, says New Venture Research (NVR).
Advanced Semiconductor Engineering Incorporated (ASE) opened its Phase 3 manufacturing facility in Weihai, Shangdong province, China, boosting discrete packaging and test capacity.
Mitsubishi Electric Corporation developed a prototype forced-air-cooled three-phase 400V output inverter with all-silicon carbide (SiC) power modules and direct lead bonding that has a power density of 50kVA per liter.
Amkor Technology Inc. (NASDAQ:AMKR) plans to build a state-of-the-art factory and global research and development center in the Incheon Free Economic Zone, which is located in the greater metropolitan area of Seoul, Korea.
Mixed-signal IC maker Silicon Laboratories Inc. (NASDAQ: SLAB) introduced a microcontroller (MCU) die sales program with a minimum order quantity of 1 wafer.
Amkor Technology Inc. (NASDAQ: AMKR), semiconductor assembly and test services provider, announced financial results for 2010, with net sales of $2.94 billion, net income of $232 million, and earnings per diluted share of $0.91. Amkor is currently planning capital additions of approximately $500 million for 2011.
Altera closed the gap on Xilinx considerably in 2010, but Xilinx's competitive 28nm product should enable it to stay at the top of the FPGA market. Start-up Achronix could be the first to reach 22nm because of its Intel connection. The Linley Group's FPGA report, "A Guide to FPGAs," covers competitors within the FPGA space, as well as FPGA adoption in the chip industry.
Hitachi Chemical has granted Henkel a worldwide license for the manufacture and sales of certain dicing die attach film.
Dave Rose, Keithley Instruments, addresses specific cabling techniques for DC, multi-frequency capacitance, and ultra-fast I-V and pulse testing, as well as the importance of proper grounding and shielding, choosing the proper interconnect for a specific measurement, and troubleshooting common interconnect problems.
ElectroIQ caught up with Suresh Ramalingam, director of advanced package design and development at Xilinx, at the January MEPTEC luncheon, where he gave a presentation on the company's stacked silicon interconnect technology. In an interview with Debra Vogler, Ramalingam discusses SSIT in relation to die stacking and TSV.
Under a 3-year, $9.3 million contract with the Air Force Research Lab (AFRL), Camgian Microsystems will develop two ASICs with ultra-low-power characteristics: an RF transceiver ASIC will use radar-on-a-chip technology, while a DSP architecture will integrate aggressive power management.
During the past ten years, Clarkson University has received more than $1.4 million of direct and indirect (through Semiconductor Research Corporation) funding from Intel Corporation.
Agilent Technologies Inc. (NYSE: A) enhanced the memory depth of its Infiniium oscilloscope lineup. All 30 models now ship with the industry's deepest standard memory and offer the deepest memory options, according to the company.
Creative Materials Inc. announced a new series of pressure-sensitive tapes that suit use in the fabrication of solar cells and modules; to replace solder and/or conductive adhesive connections; or as bus bar materials for a wide variety of printed electronics applications, including touch panels, LCDs, electro-chromatic displays, and electro-luminescent displays.
DelfMEMS and KFM Technology signed a common agreement to combine their expertise in RF micro-electro-mechanical systems (MEMS) and thin film packaging (TFP) technology. DelfMEMS will use the collaboration to provide packaged MEMS switches, fixed capacitors, and high-Q inductors on the same chip.
CEA-Leti signed a multiyear agreement with SHINKO ELECTRIC INDUSTRIES CO. LTD. to develop advanced semiconductor packaging technology. They will focus on volume production of silicon interposers.
Tessera Technologies (Nasdaq:TSRA) announced that Bruce McWilliams, PhD, has resigned as a member of Tessera’s board of directors effective immediately, to devote his time and attention to the needs of SuVolta's growing business.
Brush Engineered Materials Inc. (NYSE:BW) will change its name to Materion Corporation (NYSE:MTRN) and unify all of its businesses under the new name effective March 8, 2011.
Dr. Phil Garrou looks ahead to a laundry list of changes coming in the next ITRS Update with respect to assembly and advanced packaging, including 3D integration, interposers, and applications from medical to automotive and embedded applications.
STATS ChipPAC Ltd. (SGX-ST:STATSChP), semiconductor test and advanced packaging service provider, expanded its wafer level package (WLP) offering with new 300mm manufacturing capabilities in Taiwan.
CEA-Leti is expanding its technology offering, ramping up one of Europe’s first 300mm lines dedicated to 3D-integration applications. The new line is dedicated to R&D and prototyping and includes 3D-oriented lithography, deep etching, dielectric deposition, metallization, wet etching, and packaging tools.
JEDEC Solid State Technology Association, standards developer for the microelectronics industry, today announced that its JC-64.8 Subcommittee for Solid State Drives will target the development of standards for SSDs in applications beyond conventional disk drive form factors.
China WLCSP Co. Ltd., provider of wafer level (WLP) miniaturization technologies for the electronics industry, confirmed its commitment to the US market with the opening of a new R&D center in Sunnyvale, CA.
Nautic Partners has partnered with management to acquire Aavid Thermalloy LLC. Aavid designs and manufactures high-performance thermal management products used in a wide range of electronics systems and energy supplies.
CoorsTek Inc., technical ceramics manufacturer, completed its purchase of the advanced ceramics business of Saint-Gobain. CoorsTek adds manufacturing facilities and product lines such as silicon carbide for semiconductors.
Trident Space & Defense, which specializes in semiconductor packaging, data storage solid state drives, high-reliability electronic components, and turnkey full-tracking ground stations, will become part of the TeleCommunication Systems Inc. (TCS) government segment, as part of an acquisition announced in 2010.
SRC and researchers from Stanford University have developed a combination of elements that yields a unique nanostructure material for packaging. This advance should allow longer life for semiconductor devices while costing less than current state-of-the-art materials.
The development effort involves the integration of defect inspection with a debonding tool. Manufacturing efficiencies, along with the ability to handle ultra-thin wafers, necessitates the integration of inspection in de-bonding applications. Rudolph is bringing its inspection technologies to this three-way collaboration to provide this integrated process control solution.
Aries Electronics, an international manufacturer of standard, programmed and custom interconnection products, now offers machined high-frequency center probe test sockets to accommodate IC devices with a lead pitch of 0.30mm.
Victor Moroz discusses the strong but doable effects of stress on TSVs. TSV stress ranges are comparable to the size of the TSV, and analog behaves differently than digital. Synopsys recently presented results (part of a collaboration with imec) at a SEMATECH event.
CEA-Leti and IPDiA have formed a common lab to capitalize on their complementary expertise in miniaturization and 3D integration on silicon. The common lab will develop very high-end passive components that will resist harsh environments, functional sub-mounts for LEDs, and assembly technologies.
The System LSI Division of Samsung Electronics Co. Ltd. has licensed the OptiML Zoom image enhancement solution from Tessera Technologies Inc. (NASDAQ:TSRA).
Amid questions about the impact of the Japan earthquake on electronics and semiconductor production, there's one angle that could directly affect the semiconductor packaging sector: BT resin shortages.
KLA-Tencor Corporation (Nasdaq: KLAC) introduced the ICOS CI-T620, a high-performance component inspector system for tape and reel. The CI-T620 system has dual tapers working sequentially with minimal operator intervention to increase units per hour.
Accretech’s next generation prober, the UF3000EX, offers high-speed wafer handling, a low-noise XY stage, and high accuracy with its OTS (Optical Target Scope) positioning technology.
Molex Incorporated, interconnect supplier, has joined with other researchers to advance the goals of the Danish SAFE (Smart Antenna Front End) project. Scheduled to span four years, the $8.7 million project is being conducted by a consortium comprising Aalborg University, Intel Mobile Communications, WiSpry and Molex.
Accel-RF Corporation installed two advanced semiconductor reliability test systems for customers in Taiwan and Japan. The systems were delivered in Q4 2010 with installation completed in early January 2011.
Multitest announced that a major fabless semiconductor manufacturer has evaluated and approved its Mercury-based wafer-level contactors for subcontractors in Asia.
The collaboration will result in new applications in multi-chip modules in radar, communication, and electronic warfare systems. The new technology platform would enable miniaturization of wireless applications that are faster, lighter and can withstand higher temperatures.
Nemotek Technologie uncrated a two-element wafer-level camera, Exiguus H12-A2. The two-element lense gives Exiguus H12-A2 high resolution and low (<0.5%) distortion.
Electronics System Integration Technology Conference (ESTC) 2012 seeks original papers describing research in all areas of electronic packaging, including LED packaging, flexible electronics, assembly and interconnect technologies, and more.
The 2012 IMAPS Device Packaging Conference will take place March 6-8 in Fountain Hills, AZ, with Amkor's Dr. Robert Darveaux presenting "Escalating Challenges in Developing Complex Solutions for Next Generation Package and Interconnect Technologies."
Amkor (NASDAQ:AMKR) shared that it cut costs through workforce reductions in Q4 2012, and announced a voluntary retirement program in Japan to continue this initiative.
Kyocera America, Inc. doubled its flip chip assembly capacity for microelectronic devices with a $3.5 million Class-10,000 cleanroom, offering lead-free processes in San Diego.
STATS ChipPAC decided not to resume semiconductor assembly operations in its Thailand plant, owing to extensive equipment and facility damages sustained during the disastrous floods in 2011.
The USPTO is looking to increase the diversity of honorees for its annual National Medal of Technology and Innovation (NMTI), honoring "this nation's creative geniuses."
There are a few key attributes in new consumer electronics: a reduced footprint and/or profile, high electrical performance, fine-pitch design, custom features, and a low cost. Multi-row, wafer-level, flip-chip, and multi-chip packaging can meet these needs, say Unisem writers Rico San Antonio and Chris Stai. They compare the value of each packaging type.
Getting thinner appears to be the goal driving the market in both the wafer-level and substrate-level sectors, and innovative tooling and process technology will become paramount in addressing thinned packaging and ramping up to volume reliably, writes Dave Foggie from DEK.
Arthur Chait, president and CEO of EoPlex, describes the company’s high-volume print forming technology -- a lead carrier product called xLC-- and how it enables a cost-effective replacement for conventional quad flat pack no-lead (QFN) leadframes.
A fast-cure, low-shrinkage adhesive for optics and optical assembly, DYMAX OP-67-LS opto-mechanical adhesive cures in seconds for bonding of optical components. The product's low-shrink nature virtually eliminates movement during curing and subsequent thermal cycling.
Are we closer than we think to our needed mass production costs for silicon interposers? Phil Garrou gleans some insights from the year-ending RTI Architectures for Semiconductor Integration and Packaging conference.
Singapore's Institute of Microelectronics (IME) has launched a new multiproject wafer service for 2.5D through-silicon interposers, to provide a cost-effective platform for R&D prototyping and proof-of-concept in the technology.
Tezzaron Semiconductor has licensed patents regarding Ziptronix's direct bonding technologies, "direct bond interconnect" (DBI) and "direct oxide bonding (ZiBond), for use in 3D memory.
Dr. Phil Garrou reports from the 2nd annual Georgia Tech 2.5D Interposer Conference: what's the market projection for silicon and glass interposers, what's preventing high-volume manufacturing, and is there a crossover with flat-panel display glass manufacturing?
Alchimer SA says it is seeking partnerships with various semiconductor equipment and materials companies as it welcomes two top execs: Bruno Morel is the company's CEO since May of this year, and product development director Fr
Deca Technologies has introduced a new chip-scale packaging (CSP) product line for applications where its existing wafer-level CSP option isn't a good fit. Details and analysis to come.
Texas Instruments' MicroSiP module is the first embedded die package in high volume production. Yole D
Altera Corporation will use an exposed-die molded flip chip technology from Amkor on its 28nm Arria V FPGA. Amkor
Amkor Technology Inc. (Nasdaq: AMKR) added Mike Liang as president of Amkor Technology Taiwan. Liang's background includes stints with Phoenix Semiconductor, Ti-Acer, UMC, and others.
Applied Materials Inc. (AMAT) opened the new Centre of Excellence in Advanced Packaging at Singapore
STATS ChipPAC Ltd. (SGX-ST:STATSChP) uncrated its next-generation eWLB package-on-package (PoP) technology, with a package profile height below 1.0mm.
"Together, FCI and NANIUM offer a complete WLP service portfolio covering 150, 200 and 300mm wafer sizes," summarized Armando Tavares, NANIUM president of Executive Board.
Plessey Semiconductors developed the Electric Potential Integrated Circuit (EPIC) sensor, optimized for use as an ECG sensor, at a reportedly lower cost and better resolution than conventional electrodes. It enables ECG monitoring in mobile phone applications.
With the approach of full commercial production of 3DIC products, Dr. Phil Garrou shifts his attention to thermal performance questions and proposed thermal solutions for the future.
The advent of leading-edge semiconductor packaging technologies dictates efficient use of capital, and only the top-tier semiconductor assembly and test services (SATS) companies will have the financial wherewithal to develop required expertise and capacity, says one analyst.
Nanium says it has shipped its 200 millionth embedded wafer-level ball grid array technology (eWLB) component, a 10% year-over-year productivity increase that reflects full conversion to the company's eWLB overmold technology that allows thinner and more robust packages.
Researchers at the Karlsruhe Institute of Technology (KIT) say they have developed a novel optical connection process for semiconductors using "photonic wire bonding" that achieves data transmission rates of several Tbit/sec.
An unidentified "premier global industry research center in Asia" will use Rudolph Technologies' MetaPulse G metrology system in its advanced packaging process development activities.
Ultra Tec Manufacturing has released a new endpoint detection module for its ASAP-1 IPS selected area preparation system, for improving electronic package decapsulation and sample preparation.
Wafer probe card maker FormFactor has agreed to acquire fellow probe card supplier MicroProbe, with a combined entity rivaling top-seller Micronics in the high-growth probe card market.
Microsemi says its new die packaging technology, targeting implantable medical devices such as pacemakers and cardiac defibrillators, can be paired with an ultralow-power radio for wireless health monitoring.
EoPlex Technologies Inc. is promoting the xLC substrate for quad flat pack no lead (QFN) semiconductor packages. The substrate enables QFNs with hundreds of leads and multiple rows at a lower cost than conventional packages.
Following Intel's lead, many companies are moving to adopt copper pillar as the technology for their flip chip applications, as well as leadframe packages. E. Jan Vardaman, president of TechSearch International, says the move to Cu pillar is reminiscent of the transition from the evaporated bump to the plated bump.
New work from Stanford goes beyond simple bump shear testing to allow simulation of stresses exerted on chips during semiconductor packaging. The researchers are able to explore how the stresses affect back-end structures. Alex Hsing, a PhD student in Professor Reinhold Dauskardt's Group at Stanford University, summarizes the group's approach.
Questar Products International released the Q7000 series of fine-pitch, fine-wire (17-75μm), aluminum/gold (Al/Au) automatic wedge and ball bonders to better meet smaller lot size, multiple product variation, frequent set-up change styles of package production.
Sonoscan has demonstrated the single-scan imaging of a sample at 50 different depths, or gates, a technique called PolyGate. It reveals how features, including defects, change from one gate to the next.
Applied Materials Inc. (AMAT) signed an agreement with the Institute of Microelectronics to set up a Center of Excellence in Advanced Packaging in Singapore. The Center will have a full line of wafer level packaging processing equipment and will conduct research in semiconductor hardware, process, and device structures.
Advanced Thermal Solutions, ATS, has released the iQ-200 thermal analysis system for precisely and simultaneously measuring the temperatures of solid materials and the surrounding air, as well as tracking air velocity and air pressure at multiple points to comprehensively profile heat sinks, components, and PCBs.
Zymet Inc. introduced a reworkable edgebond adhesive, UA-2605, that improves thermal cycle performance of CBGAs and plastic BGAs. The adhesive can prevent pad damage during BGA rework, particularly with fine-pitch BGAs.
Tessera Technologies Inc. (Nasdaq:TSRA - News) began two corporate initiatives to expand its technologies in semiconductor microelectronics beyond packaging, and to potentially separate its Imaging & Optics business.
Keithley Instruments Inc., advanced electrical test instruments and systems provider, introduced the Model 2651A High Power System SourceMeter instrument to characterize high-power electronics, like HB-LEDs, power semiconductors, DC-DC converters, batteries, etc.
Freescale Semiconductor's Networking and Multimedia Group (NMG) placed a volume order for Verigy's V93000 scalable test platform to use in testing select QorIQ PowerPC communications microprocessors, based on Power Architecture technology.
MagnaChip Semiconductor now offers cost-competitive and state-of-the-art copper wire bonding technology, which can create a packaging cost savings of about 20% to 30%. MagnaChip worked with the major packaging companies to develop a bonding process that protects wafers under bond pads.
SiliconBlue Technologies unveiled its mobileFPGA platform device roadmap using TSMC's 40nm low power standard CMOS process. The two distinct families target the two areas where smartphones and other handhelds differentiate.
Thin Film Electronics ASA (Thinfilm) and PARC, a Xerox company, entered the next phase of their co-innovation engagement for printed memory devices. This next phase extends the engagement to prototyping the product for manufacturing readiness.
Daniel Duffy, research scientist in Henkel's Advanced Technology Group, notes pros and cons of epoxy and silicone encapsulants for high-brightness LED (HB-LED) manufacturing, and what HB-LED manufacturers need from die attach materials. He also considers quantum dots.
Invensas president Simon McElrea explains the company's new wire bond-based multi-die face-down (xFD) packaging technology, demo'd at this year's Intel Developer Forum, and its advantages in terms of performance and manufacturing cost reductions.
Research and Markets released "Wafer Packaging Fab Database," providing a global overview over 150 companies' 250+ mid-end semiconductor packaging houses.
X-RAY WorX GmbH introduced electronically controlled venting valves for open X-ray tubes. This avoids the manual venting typically performed during X-ray tool maintenance.
The first annual Global Interposer Technology Workshop at Georgia Tech will convene students, academics, researchers, and industry to share information on silicon and glass interposers for semiconductor packaging.
The Burn-in & Test Socket Workshop (BiTS Workshop) is changing its name to The Burn-in & Test Strategies Workshop to reflect the "evolution of packaged ICs."
Honeywell (NYSE:HON) Electronic Materials will more than double refining and casting capacity for high-purity copper and tin at its Spokane, WA, facility, citing increased demand from memory and semiconductor packaging sectors.
IRphotonics added a high-resolution FLIR thermal imaging camera to its application engineering lab. The camera will be used to analyze heat distribution during iCure use.
SEMICON Europa 2011 will take place October 11-13 at Messe Dresden in Dresden, Germany. The event covers new technologies and products for advanced microelectronics manufacturing. This year has more co-located events than ever before.
Rudolph Technologies Inc. (NASDAQ:RTEC) shipped the 1000th NSX Inspection System from its Bloomington, MN manufacturing facility. The NSX inspects wafer bumps, WLP, MEMS, and more.
Invensas Corporation, a Tessera subsidiary, will demonstrate dual-face down implementation of its new multi-die face-down packaging technology at the Intel Developer's Forum. The multi-die package is wire bonded, mounting ICs upside down and staggering them in a shingle-like configuration.
Forget "3D stacking" -- the two companies say a special electronic "glue" applied to the wafer will help stack dozens of chips into a "silicon skyscraper" that will be much faster and more efficient than current chip technology.
Amkor Technology's Board of Directors authorized the repurchase of up to $150 million of AMKR common stock, to enhance stockholder value and support its business model.
Gold wires are used in electronic devices due to the material's flexiblity and conductive quality. At the nanoscale, however, gold wires (<20nm wide) become "brittle-like" under stress, according to a new study at Rice University.
STATS ChipPAC Ltd. completed the expansion of its 300mm wafer bump and wafer-level chipscale packaging (WLCSP) operation in Taiwan.
Fan-out wafer-level packaging (FO-WLP) is gaining momentum as an option for devices with large numbers of I/Os, vs. going finer-pitch to keep using conventional fan-in technology, says TechSearch International in an updated report.
Nanotechnology accelerator SVTC Technologies partnered with SUSS MicroTec on wafer-level packaging for MEMS, and 3D IC bonding technology development.
Microsemi SoC Products Group will use outsourced semiconductor assembly and test (OSAT) provider Amkor Philippines (ATP) for final electrical package test on nearly all its products.
Fujikura Ltd. and FlipChip International LLC (FCI) released ChipletT and ChipsetT embedded die packages for single die or multi-die semiconductor packaging applications.
Backside-illuminated image sensors require more precise wafer processing -- uniform extreme wafer thinning, dopant control, epitaxy growth, trench manipulation, etc. -- but the payoff in image quality is significant. Researchers at imec experimented with different wafer fab technologies to make a record BSI sensor. They also consider new architectures/packaging techniques for this technology.
Deca Technologies, a new company backed by Cypress Semiconductor and SunPower, will combine solar wafer manufacturing methods with semiconductor manufacturing support to create wafer-level chipscale packaging (WLCSP) derivatives.
Nordson Corporation will honor the life of Steven J. Adamson, former Nordson ASYMTEK marketing specialist and electronics industry mentor, by funding a $3,000 annual scholarship in Adamson's name with the IMAPS Educational Foundation.
Multitest's Mercury contactor passed a "thorough BGA test evaluation," landing on the qualified contactors list for all business units of an international IDM.
MOSAID launched the 256Gb HLNAND2 semiconductor memory device, operating at up to 800MB/s per channel for mass storage applications. Winpac will package and distribute HLNAND devices for MOSAID.
Semiconductor Research Corporation is leading an effort to address key roadblocks for wide-scale adoption of the emerging 3D ICs and systems. These new initiatives will address critical reliability and design tool issues and leverage partnership between researchers from universities and the semiconductor industry.
NXP named Tektronix Service Solutions to provide calibration and repair services for all test and measurement instruments at NXP's production and development sites in the Netherlands.
CAD Design Software combined its Electronics Packaging Designer (EPD) and Cadence Design Systems' Allegro IC Package design and analysis environment to create a "Silicon Realization" flow for ICs in leadframe packages.
STATS ChipPAC Ltd. (SGX-ST: STATSChP), semiconductor test and advanced packaging service provider, has shipped over 300 million semiconductor packages with copper wire-bond interconnects. The SATS provider is investing in Cu wire bonding for finer silicon nodes (45/40nm) and low-k/extra low-k.
Hearing aid maker GN ReSound contracted with eSilicon Corporation, independent semiconductor Value Chain Producer, for production of the AD4.0 ASIC. This ASIC is a key component in next-generation hearing instruments from GN ReSound.
Flexpoint was unable to reveal the application in which NASA is using Bend Sensors, though Clark Mower, president of Flexpoint, called the project a "new and expansive area of potential use of our technology."
New Venture Research will release "The Worldwide IC Packaging Market, 2011 Edition" in May 2011. It provides analysis of packaging by I/O count and package type, bare die interconnect, and looks at the major semiconductor assembly and test services (SATS) providers.
Tokyo-based JSR Corporation named the first non-Japanese Officer to its Officers Committee. Eric R. Johnson, the current president of the company's US semiconductor materials operations, JSR Micro, has been named as an Officer.
SPP Process Technology Systems (SPTS) won a multi-system order for its Sigma PVD, Omega Etch and Delta CVD wafer processing systems from a leading outsourced semiconductor assembly and test (OSAT) provider in the Asia-Pacific region.
Sonix Inc. introduced its Molded Flip Chip Imaging (MFCI) enhancement. Sonix MFCI improves image quality and defect detection in molded flip chips and packages with polyimide (PI) layers.
Laird Technologies released the Tpcm 580SP Series phase change material, a high-performance, screen-printable or stencilable thermal interface material with a thermal conductivity of 4.0W/mK that provides an alternative to thermal grease.
T.Onishi, Grand Joint Tech and E.J. Vardaman, TechSearch International share the highlights on low-k dielectrics, 3D packaging, copper pillar, and other exciting work presented at the International Conference on Electronics Packaging (ICEP) in Japan.
Multitest's ECON contactor exceeded 4.5 million insertions at an Asian test house. The contactor performance resulted in a 99% stable test yield.
STATS ChipPAC Ltd. (SGX-ST: STATSChP), semiconductor test and advanced packaging service provider, is expanding its 300mm through silicon via (TSV) offering with the addition of mid-end manufacturing capabilities.
Yole reports on the flip chip market, and finds that this $16 billion industry, with diverse applications, is still growing. New flip chip technologies, such as copper pillars, and technology demands, such as fragile 28nm chips, are driving demand.
Sigurd Microelectronics Corporation (Sigurd) will be the first adopter of Multitest's MT2168 pick-and-place test handler in volume production in Taiwan. The SATS provider will use it to test various QFN packages.
NXP Semiconductors N.V. (NASDAQ: NXPI) says that it has developed the smallest logic leadless plastic packages measuring 0.9 x 1.0 x 0.35mm with 0.3mm pitch. The packages also demonstrate 4x better mechanical adhesion to the PCB than other packages in the same form factor.
About a fortnight since the 8.9 earthquake struck Japan near Sendai, Fujitsu has resumed some operations at its back-end packaging and semiconductor testing sites.
Supertex (NASDAQ: SUPX) will package its HV2601 and HV2701 16-channel, low-charge injection, 200V analog switch ICs in 5.29 x 5.30mm, 42-ball bumped die packages. This packaging represents a 50% space savings over the previous 48-ball fpBGA package.
Torrey Hills Technologies (THT) signed an agreement with Si2 Microsystems Pvt Ltd., India-based microelectronics company and THT furnace customer, for the use of its furnace to test-fire samples sent from THT's potential semiconductor, packaging, and solar cell clients.
IEEE reached the 400,000 member mark for the first time in its history. By the end of 2010, total IEEE membership had surpassed 400,000, making it the seventh consecutive year the association had experienced membership growth.
As it developed an improved FPGA technology, the NuPGA team discovered a path for practical monolithic 3D ICs. MonolithIC 3D changed its strategy to focus on monolithic 3D IC technology as a pure IP innovator organization.
ALLVIA, through-silicon via (TSV) foundry, will present its latest analysis on silicon interposers and embedded capacitors during the IMAPS Conference on Device Packaging in Scottsdale, AZ, March 9. Dr. Sergey Savastiouk, CEO at ALLVIA, will present "Silicon Interposers Enable High Performance Capacitors."
NVIDIA Corporation (NASDAQ: NVDA) has licensed Inter-Chip Connectivity (ICC) technology from SMSC (NASDAQ: SMSC), a leading semiconductor company creating valued connectivity ecosystems.
Arteris Inc., network-on-chip (NoC) interconnect IP company, will incorporate its FlexNoC NoC interconnect IP into an SoC die on silicon interposer test chip with TSMC.
The Institute of Microelectronics, a research institute of Singapore's A*STAR, plans to commercialize key innovations in silicon photonic chips designed to support high-speed, high-bandwidth optical communications.
OSRAM Opto Semiconductors introduced the Oslon Square LED for lighting applications, packaged enclosed in a reflective layer to boost light output.
SATS provider STATS ChipPAC Ltd. (SGX-ST:STATSChP) was named "Supplier of the Year" by Cirrus Logic Inc. (NASDAQ:CRUS), analog and mixed-signal processing components maker.
Hynix Semiconductor Inc. exercised the renewal option in its March 31, 2005 license agreement with Tessera Technologies Inc. (NASDAQ:TSRA) to extend the term of that license to May 22, 2017.
ChipMOS subsidiary ThaiLin Semiconductor Corp. will take on dedicated semiconductor testing capacity for a new long-term service agreement with its client Asahi Kasei Microdevices Corporation (AKM).
Fairchild Semiconductor and Infineon Technologies formed a packaging partnership for their power MOSFETs in the MLP 3x3 (Power33 or S3O8) and PowerStage 3x3 packages.
A seminar held at last month's Semicon China reiterated points made earlier in the year by an industry group that there are still questions about using copper bonding wire vs. gold in semiconductor packaging applications.
Vage Oganesian of Tessera and Vern Solberg, Tessera consultant, discuss the advanced packaging options available with 3D contact features on substrate interposers for complex, high-pin-count flip chip applications.
The readiness of suppliers to offer 2.5D packaging technologies was in full debate at the RTI 3D ASIP event this month, with presentations and rumors questioning how soon customers will need 2.5D/3D, and whether some offerings are worth the investment.
Small, mobile, Internet-connected devices are bucking the slow economy and use advanced packaging technologies to pack an enormous amount of functionality into a very small form factor, notes New Venture Research, which provides forecasts for each advanced packaging device type.
Amkor Technology Inc. (Nasdaq:AMKR), semiconductor assembly and test services (SATS) provider, has shipped more than 100 million units of its Through Mold Via (TMV) package-on-package (PoP) products.
Yole identifies the fan-in wafer-level chipscale packaging (WLCSP) market for strong growth, and a diverse base of chip technologies. Fan-in WLCSP reached 2.3 million 300mm-equivalent wafers shipped in 2011, or about $1.7 billion in revenue.
Powertech Technology Inc. (PTI) has approved a tender offer of NT$25.28 per share for the common shares of Greatek with a minimum acquisition target of 30% of outstanding shares.
IPC and JEDEC created
Singapore's Institute of Microelectronics (IME), a research institute of the Agency for Science, Technology and Research (A*STAR) launched the 11th cycle of its 15-year packaging R&D with 23 companies and 4 main projects.
LORD Corporation launched the ME-555 underfill encapsulant for semiconductor packaging and assembly. LORD ME-555 is a high-purity, semiconductor-grade epoxy underfill for encapsulating flip chips.
Tektronix Component Solutions purchased 5 Teradyne J750EX semiconductor test systems to screen a wider variety of complex ASICs, increase test capacity, and generate test programs faster.
JaroThermal's Honeycomb heatsink directs heat towards the outside of the device, while producing a steady flow of cool air inside the heatsink. Honeycomb heatsinks can be used with either plastic or metal/ceramic BGA packages.
NXP Semiconductors N.V. (NASDAQ: NXPI) launched overmolded plastic (OMP) RF power devices with 2.5-200W peak power. The plastic packages are a lower-cost option alongside NXP's ceramic package RF devices.
ternational Rectifier, (IR, NYSE:IRF), power management technology provider, introduced a PQFN 2 x 2mm with <1mm profile package featuring its latest HEXFET MOSFET silicon. The new package is ultra-compact, high density and efficient for lower-power applications.
The AccumaxDirect premier vertical probe card from Wentworth Laboratories withstands "severe test parameters" in high-volume flip chip/C4 test. It was just approved for use with Verigy testers.
IEEE's Field Award for microelectronics packaging contributions goes to GA Tech's Rao Tummala, a longtime IBM research who pioneered packaging integration research and globalization of electronic packaging.
Today at The ConFab, John Chen (Nvidia), Jeong-ki Min (Samsung Electronics), and Abraham Yee (Nvidia) gathered foundry, OSAT, and chip maker leaders to discuss what happens beyond Moore's Law. The following are key points from "Collaboration to Strengthen the IC Supply Chain."
RJR Polymers debuted liquid crystal polymer (LCP) semiconductor packaging technology for RF and microwave system designers that is competitive with ceramic ACPs, improving thermal management and offering design flexibility based on the company’s epoxy range.
STATS ChipPAC says integrating through-silicon vias with passive devices and its eWLB technology addresses complex design issues, shrinking lithography nodes, and increased performance demands for mobile and consumer applications.
SEMICON West is a major conference for semiconductor manufacturing professionals. Semiconductor packaging has become a major focus in recent years, and this year, BEOL attendees have ATE Vision 2020, 3D IC standards meetings, a keynote, and multiple sessions dedicated to packaging technologies. Here's your guide to attending SEMICON West on a packaging track.
Semiconductor die and packaging specialist Chip Supply Inc. is changing its name to Micross Components, which reflects the acquisition of Chip Supply last November by Micross Components. Micross provides specialist products and services for high-reliability and state-of-the-art electronics for high-reliability, industrial, and commercial applications.
imec's 3D integration industrial affiliation program (IIAP) partnered with Atrenta Inc., SoC realization products provider to semiconductor and electronic systems industries, to developed an advanced planning and partitioning design flow for heterogeneous 3D stacked ICs.
Carsem will grow its Suzhou, China factory by an additional 430,000 square feet, increasing their Suzhou micro leadframe package (MLP) capacity to over 20 million per day, with a focus on copper wire bonding.
Agilent Technologies Inc. (NYSE:A) released the B2900A Series line of compact benchtop source/measure units (SMU) for semiconductor, component, and materials testing. The company claims that these SMUs offer capabilities competitive with semiconductor device analyzers.
PoP provides a cost/performance solution that solves business and logistics issues associated with stacking devices directly. 3D TSV, with its associated uncertainties, cannot yet meet PoP's benefits, says TechSearch International (TSI).
Amkor Technology (NASDAQ:AMKR) completed its offering of $400 million aggregate principal amount of its 6.625% Senior Notes due 2021. The proceeds from the offering will be used to fund the company's tender offer for the approximately $264.3 million aggregate principal amount of its outstanding 9.25% Senior Notes due 2016, for general corporate purposes.
The semiconductor industry is moving to 3D device structures, says Raj Jammy, SEMATECH, at The ConFab 2011, discussing TSV and system-in-package (SiP) opportunities and challenges. He also summarizes logic and memory roadmaps.
Ramtron (NASDAQ: RMTR) named Taiwan-based King Yuan Electronics Co., LTD (KYEC) to provide semiconductor assembly and test services (SATS) for its entire line of F-RAM products.
Yole Développement released "Equipment & Materials for 3DIC and Wafer-Level-Packaging," a database and complete report analyzing in detail the equipment and materials tool-box for wafer-level packaging (WLP). This semiconductor packaging technology falls into the "mid-end," where frontend semiconductor wafer fabs and backend packaging facilities both operate.
The ConFab gathers semiconductor industry leaders to discuss the biggest trends in the chip manufacturing sector. One of these major trends is 3D packaging, and Session 2 on Monday (May 16) will combine packaging house, fabless, and foundry approaches to the new supply chain, with speakers from Amkor, GLOBALFOUNDRIES, STATS ChipPAC, and Qualcomm.
Rudolph Technologies (NASDAQ: RTEC) released the Wafer Scanner 3880 to inspect micro and standard bumps, through silicon via (TSV) post-via-fill copper protrusions (nails) and re-distribution layers (RDL) used in 3D IC packaging.
Tessera Technologies, Inc. (NASDAQ: TSRA) Board of Directors appointed Robert A. Young, Ph.D., as president and CEO, taking over for Henry R. Nothhaft, who resigned to pursue his advocacy of smart innovation policies in Washington DC.
CoolChip Technologies won the MIT Clean Energy Prize for their technology that reduces data center cooling needs with air-based CPU cooling.
RFaxis released its patent-pending On-Die Coexistence Filter technology, designed to replace "bulky and expensive" stand-alone coexistence filters for cellular, mobile, and other devices.
Multitest, a designer and manufacturer of final test handlers, contactors and load boards, now provides extended temperature control with its extended temperature calibration (XTX) on the MT9510 test handler.
Cascade Microtech (CSCD) launched a WLCSP probe card series that retains pin position, scales from x1 to x8 on a per-die basis, and can be configured for individual die testing. The Viper series will be used for high-volume test to qualify known good die (KGD).
The U.S. Court of Appeals for the Federal Circuit issued a favorable ruling in Amkor's appeal in its patent infringement case against Carsem and affliates before the U.S. ITC, Amkor reports.
Tessera received an initial payment of approximately $20 million from semiconductor packaging company Amkor, related to the interim award issued by the International Court of Arbitration of the International Chamber of Commerce (ICC).
Deca Technologies, wafer-level packaging (WLP) services to the semiconductor industry, added Iain Meikle as VP of operations and managing director in the Philippines.
Tessera appointed Rick Neely, Jr. as EVP and CFO, responsible for the company
Heavy monsoons moving through the Philippines are causing floods in and around Manila, the capital. The Philippines is a small but growing area for microelectronics manufacturing and packaging facilities.
Tektronix Component Solutions, a custom microelectronics services provider, tapped supply chain aggregator MOSIS to help its customers develop complete, high-performance ASICs with lower early-stage ASIC development costs.
Unisem named Lee Hoong Leong as group COO, replacing Ang Chye Hock, who has retired. Lee brings experience from UTAC, STATS ChipPAC, TI, and National Semiconductor.
FlipChip International (FCI), wafer-level packaging and flip chip bumping provider, named Weng Kay Lui as Asian sales director, overseeing sales for, among other areas, FCI's recently expanded FlipChip Millennium (Shanghai).
STATS ChipPAC appointed Gary Tanner as a member to its Board of Directors. Tanner brings experience from Zarlink Semiconductor, Intel, Texas Instruments, and other semiconductor companies.
At SEMICON West, the working groups of the International Technology Roadmap for Semiconductors (ITRS) outlined 2012 updates to the roadmap. Check out the back-end process info here.
Research and Markets released "Embedded Wafer-Level-Packages: Fan-out WLP/Chip Embedding in Substrate - 2010 Report," which covers embedded IC packaging markets, technology innovations, the manufacturing processes for fan-out and embedded wafer-level packaging, cost targets, and more.
In this video interview, Philip Garrou, microelectronics consultant and Advanced Packaging blogger, offers information on his blog, Insights from the leading edge, and summarizes reasonable roadmaps for 3D technology and TSV in particular. 2012 mainstream adoption seems too aggressive to Garrou.
In this video, Matt Nowak, Qualcomm, talks about his keynote at ASMC on through silicon technologies for stacking die in advanced packaging applications.
Package on package (PoP) stacking makes use of the vertical space available on electronics printed circuit boards (PCBs). It increases density, fitting more silicon into the same footprint. However, package stacking can be difficult, as fine pitches require placement accuracy, and taller stacks generally face reliability issues, especially if the stack is reflowed improperly. So where should PoP stacking take place?
Teledyne completed the acquisition of Intelek plc. Teledyne was the beneficial owner of, or had received valid acceptances in respect of approximately 93% of Intelek's ordinary shares. The aggregate value for the transaction will be approximately £35 million.
Wrap-up of what we heard and saw at SEMICON West 2010. Lesson 3: Everything about 3D & packaging was hot, with suppliers jostling to get into this next high-growth market. But are they really prepared for what awaits them?
STATS ChipPAC drew down US$150.0 million under the Credit Facility, and used the proceeds from this drawdown to redeem all US$150.0 million in outstanding principal amount of its 7.5% Senior Notes due 2010 at their maturity on July 19, 2010.
Dr. Phil Garrou looks at 3D IC technology discussions at IEDM 2010, including details of TSMC's integration of 3D into its advanced CMOS foundry processes, and a close examination of 3D-induced stresses.
Cohu Inc. (NASDAQ:COHU) appointed Luis A. Müller president of its newly formed Semiconductor Equipment Group, which encompasses Cohu subsidiaries Delta Design and Rasco GmbH.
RoodMicrotec N.V. has successfully secured mezzanine capital of € 1.994 million without repayment obligation, providing a long-term strengthening of the company’s equity position.
O2 Investment Partners, LLC, announced it has acquired all outstanding shares of Silbond Corporation, a specialty chemical manufacturing business based in Weston in southeastern Michigan.
Terepac Corporation has been accepted into the Plug and Play Tech Center in Sunnyvale, California, an incubator in the heart of Silicon Valley. Terepac’s footprint in Silicon Valley is the company’s first presence in the United States.
Micross Components, Inc. and SemiSouth Laboratories, Inc. announced a collaborative effort to expand SemiSouth's line of Silicon Carbide (SiC) Power JFETs and Schottky Diodes. SemiSouth will provide select JFET and diode die to Micross for packaging and test in metal hermetic packages
Nanometrics Incorporated (Nasdaq: NANO) announced that a leading semiconductor foundry has ordered a UniFire 7900 metrology system for advanced 3D wafer-scale packaging process control.
The Centre Intégré de Microélectronique Provence Alpes Côte d'Azur (CIMPACA) selected DCG Systems products for its characterization and failure analysis platform: the ELITE lock-in thermography system and the Meridian WaferScan emission microscopy wafer prober with LVx option.
FormFactor Inc. (NASDAQ: FORM) announced that Executive Chairman Carl Everett was elected to serve as non-executive Chairman of the Board of Directors. Current lead independent director Jim Prestridge will remain on the Board. FORM also announced the resignations of Board members Homa Bahrami, Chenming Hu and Harvey Wagner.
Diodes Incorporated (Nasdaq: DIOD) released its first device in its unique PowerDI5060 package, the DMP3010LPS 30V rated p-channel enhancement mode MOSFET.
The MiQro Innovation Collaborative Centre (MICC; Bromont, QC, Canada) will receive a $14.1 million grant as part of the Canadian government's Centres of Excellence for Commercialization and Research (CECR) program. The grant will be used for 200mm MEMS and WLP research.
Vishay Intertechnology Inc. (NYSE: VSH) has entered into a new five-year $450 million credit facility. The senior secured facility, which matures on December 1, 2015, replaces VSH's prior $250 million revolving credit facility, which was scheduled to mature on April 20, 2012.
The consideration for the acquisition is approximately $38 million, comprising of approximately $17 million in cash and 1.8 million AOS's common shares. Prior to this acquisition, AOS held 43% equity stake in APM.
Integrated Microelectronics Inc. (IMI), a leading electronics manufacturing service (EMS) provider to OEMs, announced an agreement to acquire 67% of PSi Technologies Inc. (PSi), an independent semiconductor assembly and test services (SATS) provider.
Rogers Corporation has developed a match for the RO4360 laminate: RO4460 prepreg. Both materials feature dielectric constant (Dk) of 6.15 ±0.15 and low dielectric loss of 0.003 at 2.5GHz. Together, they form an ideal system for fabricating compact, cost-sensitive multilayer high-frequency (HF) circuits in limited space.
Shin-Etsu Silicones of America Inc., U.S. subsidiary of Shin-Etsu Chemical Co. Ltd., Japan, launched the TC-CA Series, comprised of Shin-Etsu’s advanced polymer and thermally conductive filler composite material technologies. The low-hardness silicone soft pad series of products have both high thermal conductivity and excellent electrical insulation properties.
Henkel’s Hysol FP5201 NCP offers the underfill protection required for Cu Pillar technology, effectively mitigating the stress between the substrate and the die.
In this video interview, Craig Mitchell, Tessera, comments on 3D packaging and interconnect. The chip industry is using packaging technologies to address miniaturization and density. Materials are posing a challenge.
In this video interview, Dave Stepniak, Texas Instruments, talks about a wafer-level packaging (WLP) trends paper he presented at SEMICON West. He summarizes the paper for senior technical editor Debra Vogler.
WLP has always faced cost challenges on the mass-market sectors, like consumer devices. WLP can reduce power consumption and package size. Novellus introduced several products at SEMICON West to increase deposition and removal productivity and advance the technology.
This report from Research and Markets covers new and established technologies for embedded package integration. Benefits of embedded package integration include miniaturization, improvement of electrical and thermal performance, cost reduction and simplification of logistic for OEMs.
Imbedded component/die technology is a method of imbedding active and passives into cavities within a multi-layer PCB to decrease the surface area required to implement the circuit design and increase the robustness of the overall assembly. Casey H. Cooper, STI, discusses the design methodology, packaging processes, and test data gathered during imbedded die/component packaging implementation in a mixed-signal prototype. The prototype was subjected to reliability testing and demonstrated in a test flight.
Gartner VP of semiconductor manufacturing research, Jim Walker, notes that, for the first time, 2 SATS companies joined the top 20 capital spenders in 2010. He also predicts solid growth for advanced packaging tooling with memory ATE and copper wire bonders being the top performers. Walker says the conversion to copper wire from gold is a wise move.
The 5th annual IeMRC Conference, September 21 in Loughborough, UK, will include 4 sessions: Advanced packaging, Materials processing and assembly, Printed electronics, and EPSRC.
KGD (Known Good Die) Packaging and Test Workshop 2010 will focus on semiconductor die products test, assembly, manufacturing, and business issues in the microelectronics industry. Bill Bottoms will keynote, covering deep submicron and 3D integration.
Fujipoly released Sarcon 100GR-FL, a low resistance, durable thermal interface gap filler pad. The gel-like material is manufactured with an integrated nylon mesh layer that prevents distortion and stretching during die-cut operations.
Laird Technologies released the Tflex XS400 Series thermal gap filler, a compliant elastomer gap filler for moderate thermal performance with a thermal conductivity of 2.0W/mK. This soft interface pad conforms with minimal pressure, resulting in minimal thermal resistance even at low pressure with little or no stress on mating parts.
A pre-competitive iNEMI R&D project plan, currently under development, will identify approaches capable of meeting wiring density needs for future generations of organic semiconductor packaging substrates. Meeting these future needs will require radical improvements and innovations in all aspects of organic packaging substrate technology.
Picotest released a new family of Signal Injectors, or adapters, to improve voltage regulator, LDO, and power supply testing accuracy. Increased bandwidth and higher resolution measurements are enabled for PSRR, stability, crosstalk, reverse transfer, input impedance, Bode plots, and crosstalk tests along with non-invasive ICT for load transients, stability and output impedance.
Nordson DAGE, a subsidiary of Nordson Corporation (NASDAQ: NDSN) and provider of bond testing technology, introduced Paragon intelligent bond testing software for semiconductor packaging.
Users of WIN's GaAs foundry services can engage in wafer-level and package test in Silicon Valley, CA, and Grenoble, France.
Research in China put out this new report chronicling the advanced semiconductor packaging industry happenings and key companies from 2009 to 2010. The study mainly focuses on CSP and BGA packaging. Technology adoption and costs are analyzed, from eWLB to TSV. Packaging tech usage examples are included here, along with assessments of tech adoption and industry player rankings.
RJR Polymers debuted a new-generation LCP quad flat-pack no-lead (QFN), air-cavity package that will support finer lead pitches, thinner leadframes and shorter wire bond lengths in a near hermetic, ROHS-compliant solution.
Tessera Technologies Inc. (Nasdaq:TSRA) opened a new office in Seoul to support Tessera’s regional activities with OEMs and industry partners in the growing cell phone market.
Dow Electronic Materials has broken ground for a new metalorganic precursor manufacturing plant in Cheonan, Korea. Dow is expanding TrimethylGallium (TMG) production capacity to meet the surging global demand for the material in the LED and related electronics markets.
Bare die in yarn, comfortable electronics, stretchable interposers, washable photovoltaic clothes, and other elements will be on the table for the PASTA project to bring smart textiles from the lab to industrial manufacturability. Imec leads the program.
Jae-Woong Nah, researcher at IBM's Thomas J. Watson Research Center, briefed ElectroIQ on his IMAPS conference paper: "Mask and mask-less injection molded solder (IMS) technology for fine-pitch substrate bumping." IMS is a variation of C4NP for solder deposition on fine-pitch laminates. Nah explains how the researchers injected 100% pure molten solder instead of solder paste with a reusable film mask for forming high-volume solder on fine-pitch substrates.
Kulicke & Soffa Industries Inc. (Nasdaq: KLIC) introduced the IConnPS ProCu wire bonder optimized for copper wire bonding. The K&S IConnPS ProCu offers a significant and new level of capability for packaging lines transitioning from gold to copper wire bonding.
NovaCentrix announced that Metalon ICI-020, a new copper-based screen ink, will be featured at Printed Electronics USA 2010 in Santa Clara, CA, November 30-December 2, 2010. Pre-printed samples of Metalon ICI-020 screen ink on card stock will be distributed with the registration packs by IDTechEx staff, and attendees may bring their samples to the NovaCentrix exhibit area to cure the ink with NovaCentrix’s PulseForge process tool.
EI added LCP Laminates to its family of microelectronics packaging product offerings. Custom-designed LCP Laminates are suitable for semiconductor packages as LCP coreless designs for up to 6 layers as well as in combination with other rigid materials as hybrid circuits. Development and testing of Z-interconnect cross-sections for >8 layer offerings are also underway.
The phoenix nanotom m, from GE´s Inspection Technologies business, has been developed for high resolution and high precision X-ray computed tomography (CT) in non-destructive 3D analysis and 3D metrology.
LTX-Credence (LTXC) introduced the ASLx, a new test system extending the capabilities of the ASL low-cost analog and mixed-signal test platform. ASLx provides 4x the analog and digital pin count and 5x the power capability of the ASL1000.
Alan Huffman, research engineer and program manager at RTI International, presented a paper at IMAPS 2010 titled "On the origins, status, and future of flip-chip and wafer-level packaging." In a podcast interview with Debra Vogler, senior technical editor, Huffman discusses the advantages and disadvantages of flip-chip and wafer-level packaging (WLP), along with potential solutions.
The IDTechEx report, "Active RFID and Sensor Networks 2011-2021," comprehensively analyzes the technologies, players and markets with detailed 10-year forecasts, including tag numbers, unit prices and interrogator numbers and prices.
Tutorials at the October event will cover 3D packaging, future interconnects, WLP, flip chip, and more.
The senior notes consist of $600.0 million of 7.5% Senior Notes due 2015. The Private Placement is expected to close on Thursday, August 12, 2010.
Semiconductor packaging and test provider Unisem (M) Berhad announced results for the second quarter, ended 30 June 2010 (2Q10).
Assembléon’s recently released Twin Placement Robot (TPR) will reportedly reduce costs for semiconductor backend manufacturing. The TPR fits on Assembléon’s A-Series pick & place equipment for packaging and IC placement. Plans are in the works for the TPR to do semiconductor manufacturing tasks as well.
Continental Corporation applied economic conveyor and handling modules from IPTE’s EasyLine product portfolio to link its gold and aluminum wire bonding, mounting, and AOI areas.
Japan Marketing Survey Co. Ltd. (JMS) will publish "Outlook of thermal interface material market 2010) this week, with data on the semiconductor package thermal management market size by application, thermal interface material types' market shares, and more.
PoP packages present some unique rework challenges, such as how to rework an underfilled package; also, these packages are prone to warpage. Inspecting the area array devices can be a challenge. Bob Wettermann, BEST Inc., discusses rework solutions.
Endicott Interconnect Technologies Inc. (EI) entered into a strategic partnership agreement with Harris Corporation to jointly develop innovative microelectronic solutions and collaborative services for new products serving key markets and customers.
Indium Corporation’s global product manager, Andy C. Mackie, Ph. D., MSc, is presenting at the International Wafer-Level Packaging Conference (IWLPC) October 11-14, 2010 in Santa Clara, CA.
The advanced packaging and test track of SEMICON Europa will deal with the industry shift away from high-lead solders, digital test and testing integrated analog/mixed-signal packages, package design in the electronics design workflow, and LEDs, among other topics.
3D Semiconductor Integration, Next Generation Materials, Photovoltaics, Advanced Assembly & Packaging to be Highlighted at IMAPS 2010 International Microelectronics Conference.
Under the agreement, Fujitsu is licensed to Tessera's semiconductor packaging technology covering a broad range of chipscale and multi-chip package types.
New requirements are coming on-line for manufacturers of products containing tin (Sn), tantalum (Ta), gold (Au), tungsten (W), or any other “conflict metals.” If the electronics industry thinks that the SEC regulations will only impact publicly traded companies, they need to think again.
Integra Technologies, IC test and evaluation services provider, was selected by Proteus Biomedical for development and production test of their new integrated circuit (IC) designs for future medical electronics products.
An in-house tool allows KaiSemi to perform automated FPGA-to-ASIC conversion, creating fully compatible replacement chips.
STATS ChipPAC Ltd. opened a new 300mm embedded Wafer-Level Ball Grid Array (eWLB) manufacturing facility, switching over from 200mm technology. The official inauguration was held at STATS ChipPAC's Yishun facility in Singapore with more than 150 local dignitaries, customer representatives, business partners and management participating.
Freescale will license its redistributed chip packaging technology to Nepes, Korean semiconductor parts and materials specialist. Nepes and Freescale will also collaborate on RCP development.
VectorGuard 3D stencils are designed for specialist applications requiring multiple level printing. Facilitating printing on different levels with upward or downward steps, VectorGuard 3D enables a uniform stencil thickness.
MicroProbe, wafer test technology supplier, is extending its direct-dock offering to support Advantest's T2000 SoC test platform. The T2000 platform-compatible option enables test coverage at wafer sort. More than 100 direct-dock probe cards are already in the field.
The test community is embracing 3D ICs, as evidenced by presentations at the first IEEE International Workshop on Testing 3D stacked ICs that addressed a range of test challenges and solutions, reports Dr. Phil Garrou.
TechSearch International’s new study, "2010 Flip Chip and WLP: Market Projections and New Developments," projects a CAGR of more than 15% for flip chip units. In unit volumes, WLPs are expected to see a 12.48% CAGR from 2009 to 2014. The report profiles drivers for the demand for gold and solder bumping, as well as WLP.
In this podcast interview, Smith discusses the three generations in the transition to 3D packaging and how the OSATs shape the development roadmap. Smith says that we need complete supply chain collaboration: EDA tool suppliers, equipment/materials suppliers, logic, memory, fabless, IDMs, and the SATs, to develop and deploy the technologies.
Package-on-package, implemented with flip chip package assembly, is meeting requirements for next-gen mobile devices. Challenges remain: fine pitch underfill, brittleness of ultra low-k (ULK) dielectrics, and shorting between adjacent bumps. Craig Mitchell, Tessera, examines the lucrative 3D packaging step and how to face these challenges.
Advanced Packaging asked our readers where -- at the foundry, in a dedicated semiconductor assembly and test services (SATS) house, or on the SMT line -- package-on-package (POP) assembly should take place.
Rudolph Technologies Inc. (RTEC) is partnering with a major outsourced semiconductor assembly and test (OSAT) services manufacturer to provide its inspection and metrology capability in the development of stacked packaging processes. The process uses silicon interposer technology, sometimes referred to as 2.5D IC, as an intermediate step toward full blown 3D ICs.
Japan's Fujitsu Semiconductor Ltd. will transfer its flip chip mounting technology to a Chinese group affiliate for system chip assembly.
Mattson Technology Inc. (NASDAQ: MTSN) received a repeat order for the Alpine etch system from a leading semiconductor manufacturer. The system will be used in the customer's leading-edge 300mm packaging facility in Asia for advanced wafer-level packaging processes.
Senior technical editor Debra Vogler asked Tarun Verma, senior director, packaging engineering at Altera, to comment on the MEPTEC Semiconductor Packaging Roadmaps conference, which took place recently in Santa Clara, CA.
Japan Marketing Survey Co. Ltd. (JMS) published the report "IC Packaging & Substrate Report 2010." It covers production trends of major semiconductor package assemblers and substrate makers and the package market size through 2014, based on package type and electronics volume.
Tessera Technologies Inc. (Nasdaq:TSRA) semiconductor packaging subsidiary, Tessera Inc., signed a technology licensing agreement with Nanium S.A. Nanium, formerly known as Qimonda Portugal, previously was the largest semiconductor packaging assembly and test operation within Qimonda. Nanium has now reorganized as an independent company and will focus on providing assembly and test services for the DRAM memory market and other semiconductor products. Products manufactured by Nanium will be incorporated into computers, servers and various electronic devices such as MP3 players, mobile phones, cameras, and game consoles. The initial term of the license agreement runs through the end of 2017.
System Plus Consulting released its new reverse costing analysis of the enhanced Wafer Level BGA (eWLB) packaging used in the X-GOLD 213 circuit from Infineon. eWLB is a ball grid array (BGA) package based on the emerging fan-out wafer-level package (FO-WLP) concept. All the packaging operations are done at the wafer level, and a fan-out area is provided to extend the package size beyond the IC surface area to allow for higher ball counts. The ball pitch is 0.5mm and only one redistribution layer is used for this 217 balls, 8 × 8mm package.
ICAP Ocean Tomo, the intellectual property brokerage division of ICAP Plc (IAP.L), is offering for sale a patent portfolio relating to wafer-level semiconductor packaging owned by Hymite A/S. The 77 issued U.S. and foreign patents and patent applications cover new packaging technologies for optical communications components, LED emitters, and semiconductor fabrication.
The Burn-in & Test Socket (BiTS) Workshop will take place March 7–10, 2010 at the Hilton Phoenix East/Mesa Hotel in Mesa, AZ. More than 30 papers and posters will be presented; participants include end users and suppliers of sockets, boards, burn-in systems, handlers, and packages; and other related equipment, materials, and services. The TechTalk session on PCB design, fabrication and assembly is booked full, as is the tutorial on RF socket characterization by Gert Hohenwarter, Ph.D. of Gatewave Northern Inc. Here are some of the show highlights.
On behalf of the World Gold Council (WGC), SEMI conducted a survey titled “Semiconductor Industry Opinions Concerning the Selection of Bonding Wire Material.” The survey was intended to gauge the semiconductor industry’s use of copper bonding wire versus gold for packaging applications. The WGC is a commercially driven organization focused on creating demand for gold. While 41% of semiconductor companies surveyed use copper bonding wire, none use it in the majority of their products. However, the majority of respondents will consider copper bonding wire in their new products.
In this video interview, Sesha Varadarajan, Novellus, says that capacitance issues must be overcome, and the PVD step must provide good enough coverage to properly apply copper. CTE mismatch can also cause issues.
Yole asks if next-generation package substrates are myth, niche, or high-volume necessity? Several companies are investigating silicon interposers and there is great interest in the topic, but there is no clear consensus on apps and timing for adoption, says TSI in its forecast for Si interposers. Both analyst forecasts are summarized.
In this video interview from SEMICON West 2010, Jan Vardaman, president/founder of TechSearch International, discusses 3D technologies in the real engineering world. Especially for 300mm, work is being done on processes and yield. She points to 2012 for widespread adoption of TSV.
Peter Ramm, Fraunhofer EMFT, will be the Opening Speaker at the 7th Annual International Wafer-Level Packaging Conference (IWLPC). Ramm will present "The European 3D Technology Platform for Heterogeneous Systems" at the Kick-Off Reception.
Carsem is aggressively expanding its MLP/QFN package manufacturing capacity in Ipoh, Malaysia and Suzhou, China factory locations. This capacity expansion in assembly is matched with an equal proportion of test capacity expansion.
Murata purchased 533,000 shares of RF Monolithics Inc. (RFMI) common stock at a small premium over RFM’s recent 30 day volume weighted average price, in a private transaction. RFM and Murata Manufacturing Co. Ltd. have entered into a collaboration agreement.
The series of workshops focuses on digital signal processing (DSP) system design using Xilinx FPGAs with high-speed data converters. These workshops are being offered to design engineers in North America.
Shipments of “combo” chipsets for mobile devices that gather a variety of connectivity types in one small package are expected to approach 280 million worldwide by the end of 2010. Integrating different radio technologies such as FM, Bluetooth, Wi-Fi and GPS on a single chip may sometimes involve performance compromises, but saves money, space and power.
Sensonor Technologies is developing SAR500, a novel high-precision, low-noise, high-stability, calibrated and compensated digital oscillatory gyroscope with SPI interface housed in a custom-made ceramic package.
SiliconBlue Technologies, provider of custom mobile devices for consumer handset applications, debuted two device packages for its iCE65 mobileFPGA family. The iCE65L01 FPGA device with 1,280 logic cells is now offered in a 5x5 mm, 81-ball BGA package with 63 user I/O pins, and the iCE65P04 device with 3,520 logic cells is now offered in a 6x6 mm, 121-ball BGA package with 95 user I/O pins.
At the ITRS 2012 update, back-end technologies session, at SEMICON West, roadmapping for More than Moore was addressed as both a philosophical and technical matter.
ULIS invested EUR20 million in a new state-of-the-art facility to meet increasing market demands for IR technology, with a move to 200mm wafers and pixel/wafer-level packaging techniques.
Ultratech formed 'exclusive supplier' and 'preferred tool vendor' agreements with several top-tier advanced packaging companies around the world.
STATS ChipPAC brought its fcCuBE advanced flip chip semiconductor packaging technology with copper column bumps, bond-on-lead interconnection, and enhanced assembly processes into high-volume manufacturing for multiple customers.
Tessera received notice from Powertech Technology Inc. (PTI) that it will terminate its license agreement with the semiconductor packaging and optics technology company. Tessera also completed phase 1 of its acquisition of camera module technologies from Flextronics.
UNISEM relaunched its business model with the name
Ultratech acquired IBM patents on semiconductor packaging technologies, including C4 bumping, ball grid array (BGA) methods, lead-free solders, and 3D packaging.
Attendance was high at this year's Electronic Component Technology Conference (ECTC) in San Diego. Sandra Winkler is senior industry analyst at New Venture Research and IEEE/CPMT Luncheon Program Chair, shares the key trends in ECTC's sessions, like WLP, 2.5D, LED packaging, and more.
The LL leaded laminate copper-moly-copper base packages dissipates heat from high-power compound semiconductor devices, such as gallium nitride, gallium arsenide, and silicon carbide chips.
Terepac Corp. will produce high volumes of its proprietary micro circuits for Rockwell Automation, supporting the "Internet of Things" with RFID tags. Rockwell Automation will support the infrastructure that Terepac uses, enabling it to miniaturize significantly more circuits than its current capability.
The Full Service Foundry business unit of ams extended its dedicated test solutions for foundry customers, offering known good die (KGD), with customers' complex analog/mixed-signal ICs 100% electrically tested according to their own test specification.
Day 3 of the 15th IITC (International Interconnect Technology Conference) opened in San Jose, CA under clear sunny skies and a pleasant breeze. The herd thinned a bit, down to ~150 hearty souls from the original 230 the prior two days.
OSAT Inari Berhad was listed on the Bursa Malaysia, Stock Code: 0166, in an IPO that will partly be used to fund a new packaging and test facility.
Henkel worked with STMicroelectronics (STM) to qualify Henkel's Ablestik C100 conductive die attach film materials for scalable, adaptable leadframe packaging.
Jan Vardaman, president and founder of TechSearch International, summarizes highlights from her SEMICON West presentation on TSVs, speaking to RDL development, LED packaging, and TSV-alternative PoP.
The FC300R performs chip-to-substrate bonding, chip-to-wafer assembly, and chip-to-chip stacking for flip chip, through silicon via (TSV), and other advanced packaging processes, with a robotic handling system for fragile and diverse substrates/wafers.
WACKER began operating several silicone-polymer production lines at its Burghausen, Germany, site, expanding production of high-purity specialty silicones, encapsulation and coating compounds, as well as UV-activated silicones.
Creative Materials now manufactures electrically conductive and electrically insulating adhesives for quartz oscillator circuits, used for bonding leads and lids. The low-stress adhesives feature good thermal stability with low out-gassing.
Advanced Semiconductor Engineering Inc. (ASE, TAIEX:2311) predicts that the global IC sector will face inventory adjustments in the near term. ASE will maintain its capital expenditure plan through the correction period.
NEXX Systems installed 2 300mm Stratus deposition at a Korean IDM for high-volume wafer-level packaging processes.
The compact package suits mission-critical applications requiring up to 4GByte memory densities in smaller, faster packages with extended-temperature ranges.
Endicott Interconnect Technologies released an update on its defense electronics development and production and sustainment contracts, which totalled $101 million.
SEMICON West preview: This year's SEMICON West Advanced Packaging Program is taking a broad approach, encouraging participation from across the supply chain to help keep pace with a rapidly expanding electronics market -- and in markets beyond, from automotive to aerospace and medical.
Carsem received Microsemi Corporation's Best Supplier of The Year Award, for assembly and test services that were provided by the Carsem factory located in Suzhou, China.
The JEDEC Solid State Technology Association published a significant revision to JESD9B, Inspection Criteria for Microelectronic Packages and Covers.
Technic Inc. debuted Pallaspeed Pd/Ni NFA, a production-proven sulfate palladium nickel process that produces low-stress ductile deposits over a wide current density range, for structures like semiconductor package leadframes.
NXP SOD882D enables easy visual inspection of solder pads. SOD882D is an ultra small and flat package built for space constrained and robust devices. The new package pad designs were developed out of NXP's discrete leadless packaging technologies.
New Venture Research, a technology market research company, released "Advanced IC Packaging Technologies and Markets, 2010 Edition," a strategic report on the latest technologies in IC packaging, with forecasts of key markets.
Vishay Intertechnology Inc. (NYSE: VSH) released two devices in its first family of power MOSFETs built on an enhanced process flow with strict manufacturing process controls for implantable medical applications.
DEK has teamed up with Irisys, infrared products supplier, to develop a robust fine-pitch isotropic conductive adhesive (ICA) interconnection process designed to drive Irisys’ latest generation of advanced infrared sensor products. The project led to the development of an optimized process for the assembly of pyroelectric thermal sensing arrays.
4G chipmaker Sequans unveiled its latest Mobile WiMAX solution, the SQN1280, an all-in-one WiMAX system-in-package (SIP) for makers of handsets, tablets, USB sticks, portable hotspots, M2M modules, and a variety of consumer electronics devices.
The AYALA group’s electronics unit, listed Integrated Microelectronics Inc. (IMI), has completed its $30-million acquisition of PSi Technologies Inc.
austriamicrosystems Full Service Foundry introduced "More Than Silicon," a comprehensive service and technology package that goes beyond standard foundry services. Foundry customers receive access to leading-edge technology add-ons, advanced packaging services, and dedicated support engineers to enable first-time-right designs.
DEK has launched ProActiv process technology to enable electronics manufacturers to print pastes with high-density heterogeneous PCBs and ultra fine pitch assemblies such as advanced package assembly.
Buoyed by improved demand and a brightening macroeconomic environment, NOR flash memory market revenue is projected to return to growth in 2010, according to iSuppli Corp. The climb will be modest: from $4.6 billion in 2009 to $4.8 billion in 2010.
In a deal that will generate economical new process options for the 3D integration market, Alchimer S.A., a provider of nanometric deposition technology for semiconductor interconnects and through-silicon vias (TSV), and KPM Tech Co. Ltd., a manufacturer of plating materials and systems, announced a multi-level collaboration that gives KPM Tech exclusive rights to produce chemicals in Korea for Alchimer’s technology. The agreement also includes the manufacture of various configurations of wet processing tools to support the Alchimer TSV platform.
Silicon circuit board (SiCB) technology allows bare-die FPGAs, CPUs, and memory to be placed together on a single silicon substrate. Embedded computing modules using SiCB offer better performance than FR-4 material -- notably 22% reduced power consumption in a typical system, reports David Blaker from siXis Inc.
The IMAPS-UK MicroTech-2010 and IEEE-CPMT Advanced Packaging Materials (APM), Feb. 28 to March 2 at Cambridge University, will be the major Spring 2010 event on electronics packaging, interconnection and integration conference in Europe.
Tom Adams from Sonoscan describes advances with "chip-in-polymer technology, developed at Germany's Fraunhofer IZM, which achieves 3D packaging advantages through better shock/vibration protection and shorter interconnect distances.
Execs from Applied Materials and Semitool discuss the motivations behind AMAT's $364M acquisition, to solidify and widen a presence in two key growth segments: advanced packaging and copper interconnects for memory.
Presentations at this year's International Symposium on Microelectronics (IMAPS, San Jose, Nov. 1-5) included discussion of TSV/3D integration challenges and temporary bonding steps qualified for different process flows, and a wafer-level packaging (WLP) encapsulation process and stacked multi-chip package (MCP) for a MEMS variable capacitor and control IC chip.
Taiwanese subcon ASE has ordered "multiple" tools for backend inspection from Rudolph Technologies, illustrating a trend to incorporate real-time process control into advanced backend fabrication processes.
Embedded computing modules employing "silicon circuit board" technology as an alternative to expensive ASIC developments offer advantages in performance and power for integrating memory and logic -- and are a practical alternative to 3D integration due to thermal and supply chain issues, explains siXis' David Blaker.
Andrew Smith, Ventmark Technology Solutions, presents a 3D die stacking technology to address package miniaturization. Using bare die and vertical interconnect structures, this stacking technology permits the design of ultra-thin, near-CSP solutions without TSVs. Designers lacking custom ICs should look to new chip stacking technology.
The International Conference "3-D ARCHITECTURES FOR SEMICONDUCTOR INTEGRATION AND PACKAGING" will take place December 8-10, 2010 at the Hyatt Regency San Francisco Airport Hotel. Check out the planned keynotes and topics of the conference.
SST/AP gets an update on Texas Instruments' progress ramping its new assembly/test facility in the Philippines -- which had been ramped far ahead of schedule in response to "unprecedented" demand.
SET unveiled a patented system enabling a thorough removal of oxides before or during the semiconductor packaging bonding sequence. Addressing the challenges of the oxidation of metal surfaces in device bonding, this machine system encompasses a substrate chuck and a bond head with a non-contact localized confinement chamber that operates safely with reducing gases such as forming gas or formic acid vapor.
SABIC Innovative Plastics launched three new sustainable additions to its Valox* ENH resin series that deliver advanced flame retardance (FR) with desirable mechanical and electrical performance. These innovative materials help customers comply with global environmental regulations.
EoPlex Inc. debuted a high-performance, clean-tech lead carrier for semiconductor packaging. EoPlex xLC is reportedly a cost-effective replacement for the leadframes currently used in quad flat pack no-lead (QFN) packages.
X-RAY WorX presented its new concepts for the cooling of high resolution microfocus X-ray tubes. The company offers a new, modular cooling concept with an optimized internal cooling of the target inside the tube head.
Cascade Microtech Inc. (NASDAQ: CSCD) announced new programs to drive down ownership costs and provide customers with increased access to experts in probe technology. The new programs involve direct sales channels and a repair program, among other efforts.
Global Industry Analysts released a report analyzes the global market for IC sockets in US$ Million by dual in-line memory module sockets, production sockets, test/burn-in sockets, and others. Regional IC sockets markets are analyzed as a consolidated whole with no granular level breakup offered by product group/segment. Annual estimates and forecasts are provided for the period 2006 through 2015.
At the Electronic Components & Technology Conference (ECTC) this month in Las Vegas the CPMT (Components, Packaging and Manufacturing Technology) Society of IEEE bought out their long time partners ECA (formerly EIA). Other news: STATSChipPAC expanded its presence in eWLB, copper-copper bonding in 3D was reviewed, and Doublecheck Semiconductors, working with Disco and the Fraunhoffer IZM claims to have developed technology that enables standard silicon wafers to be thinned down to less than 100µm.
In a SiP chip stack, space constraints can lead to large parasitic inductances in the packaging. Planarity, processing, high-temperature exposure, and other factors also present challenges. A new anisotropic conductive adhesive technology could enable low-cost flexible packaging via a multi-layer particle structure. S. Manian Ramkumar, Ph.D., RIT, reviews the adhesives benefits to various levels of electronics interconnect.
Aries Electronics, manufacturer of interconnection products, now offers a CSP test socket with a window that optically exposes 100% of the top of the device under test (DUT) for failure analysis (FA) testing for emission microscopy (EMMI) or optical sensor applications.
The CREAM Project addresses the thematic “Aeronautics and Air Transport (AAT)” through the objective of developing an “Innovative Technological platform for Compact & Reliable Electronic integrated in Actuator and Motor” destined for several applications of the All Electric Aircraft such as fuel pumps, landing gear or brake actuators, flight control actuators, etc.
Imec and PVA Tepla say they have achieved void detection in through-silicon vias at wafer level, after TSV copper plating, thanks to a nondestructive high-frequency scanning acoustic microscopy (SAM) technique.
Novati Technologies Inc. has licensed Ziptronix's direct bonding technologies, "direct bond interconnect" (DBI) and "direct oxide bonding (ZiBond), to offer 3D stacking services and test to customers.
Semiconductor packaging and test services provider Carsem will assemble and test LED packages, partnering with a key customer and applying semiconductor packaging technologies for better LEDs.
GaN Systems and Arkansas Power Electronics International will co-develop a high-temperature, high-performance package optimized for gallium nitride (GaN) transistors and diodes.
NXP Semiconductors released the new SOT1226 "Diamond" package using a
EoPlex Limited, a subsidiary of ASTI Holdings Limited, Singapore, will open a new factory for its xLC semiconductor package technology in Q2 2012, in Malaysia.
Semiconductor packaging service provider STATS ChipPAC Ltd. (SGX-ST:STATSChP) appointed Pasquale Pistorio as a member of the Board of Directors, effective immediately.
Silex Microsystems brought its Met-Via full-wafer-thickness TSV technology into Chip Architectures by Joint Associated Labs for European Diagnostics, where it is being used to create cost-effective molded chip-level packaging with through metal vias.
ChipMOS TECHNOLOGIES INC. (ChipMOS Taiwan), purchased a 393,173sq.ft. building adjacent to its existing facility in Southern Taiwan Science Park.
WLCSP start-up Deca Technologies might take over SunPower Corp.'s Fab 1, when the solar photovoltaics supplier consolidates its Philippine manufacturing operations to Fab 2 this quarter.
Georgia Tech's Packaging Research Center proposes a new consortium on 3D semiconductor packaging called 3D ThinPack for ultra-miniaturized 3D heterogeneous, RF, digital and power modules in partnership with global companies.
Invensas Corporation, a wholly owned subsidiary of Tessera, unveiled a DIMM-IN-A-PACKAGE multi-die face-down (xFD) packaging architecture for memory semiconductors in low-profile devices.
Endicott Interconnect Technologies has appointed David W. Van Rossum to the position of Chief Financial Officer, effective immediately.
ON Semiconductor (Nasdaq: ONNN) will develop a next-generation star tracker CMOS image sensor with the European Space Agency. The sensor will be used in star trackers, sun sensors and other scientific applications.
Terepac Corporation, developer of tiny digital electronics, has launched the TereTag miniaturized circuit design that is embedded in items to enable the "Internet of Things."
Cypress Semiconductor transferred 7 back-end semiconductor package assembly lines from its Philippines facility to Chinese packaging subcontractor Jiangsu Changjiang Electronics Technology Co.
Texas Instruments Incorporated (TI, TXN) now offers bare die in quantities as low as 10 pieces for initial prototyping, and larger quantities (full waffle trays) for production volumes.
Research organization imec introduces important changes to its ultrathin chip packaging (UTCP) technology, increasing yields 15-20%.
The Global Semiconductor Alliance (GSA) released its GSA Q1 Wafer Fabrication & Back-End Pricing Reports, tracking fab utilization rates, wafer and mask costs, and package pricing.
The 2011 International Technology Roadmap for Semiconductors (ITRS) has been publicly released. Several areas of advancement are highlighted in the 2011 ITRS: DRAM and Flash memory, and MEMS.
Yole Developpement released "European Microelectronic Fabs Database & Report 2012," a database and report on the European microelectronics and microsystem manufacturing fabs, pilot lines, and major R&D organizations.
For the first time, Apple Inc. has publicly published a list of over 150 companies that the electronics giant says represent 97% of its procurement expenditures for materials, manufacturing, and assembly of products worldwide.
While Apple's release of the iPhone 4S in Q4 2011 "unleashed tremendous pent-up demand" from consumers, Samsung used its broad range of smartphones to take the top spot, reports IHS.
Toshiba Corporation (TOKYO: 6502) will rebuild its semiconductor manufacturing operations in Thailand by relocating Toshiba Semiconductor Thailand Co., Ltd. (TST) to a new manufacturing facility.
The 23rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2012) will be held May 15-17 in Saratoga Springs, New York. The conference will feature presentations of more than 85 peer-reviewed manuscripts covering critical process technologies and fab productivity. This year’s event features a panel discussion on “Competing for R&D Dollars,” moderated by Solid State Technology Editor-in-Chief Pete Singer.
Blogger Mike Fury reports from the MRS Spring 2012 meeting in San Francisco. Highlights from the third day: leakage and TDDB in low- κ dielectrics, flexible energy storage and conversion, Mn capping layers and diffusion barriers, hard masks for Cu interconnects, nanogenerators, Cu in RF, flexible temperature sensors, NEMS and MEMS in HDD, ZnO nanostructures, and various aspects of CMP.
Solid State Technology is proud to announce that David McCann will speak at The ConFab 2012. David, the Senior Director for Packaging R&D at GLOBALFOUNDRIES in Malta, New York, will speak on the evolution toward silicon-based interconnect and packaging, which is having profound impact on how we think about technology development and the supply chain.
CMOS image sensors (CIS) are breaking sales records again, after several years without upward momentum, reports IC Insights. New portable systems and embedded imaging are lifting CIS to $6.3 billion in 2012 and new record sales each year through 2016.
coolingZONE LED, May 29-31 in Berlin, is soliciting technical presentations on LED energy consumption, LED packaging, heat and air-flow simulations of LED products, and related topics.
SEMI is seeking papers for technical sessions and presentations at the upcoming SEMICON Europa 2012, October 9-11 in Dresden, Germany. Technical presentation abstracts are due April 30.
Taiwan raised investment ceilings for Chinese investors in LCDs, semiconductors, IC assembly and test, microelectronics production equipment, and metal tool manufacturing.
IBM scientists developed a prototype optical chipset, Holey Optochip, that can transfer 1Tbit per second as a parallel optical transceiver, using optical vias through a standard 90nm CMOS chip.
SEMI has extended the deadline to submit proposed papers to next spring's China Semiconductor Technology International Conference 2013, and added a new symposium on circuit design, system integration, and application.
Semiconductor equipment demand is persistently sluggish as the industry takes a break from a "multiyear expansion period" to digest recent investments and wrestle with a broader economic slowdown, acknowledges SEMI in its updated year-end forecast. But make no mistake: leading-edge technology investments are still happening, and growth will return in the typical cyclical pattern.
STATS ChipPAC Ltd. plans to expand its semiconductor assembly and test operation in South Korea.
We've scanned the entire conference program for next week's 58th annual IEEE International Electron Devices Meeting (IEDM), to present a quick sampling of some of the more intriguing papers.
Rudolph Technologies, Inc. (Nasdaq: RTEC) has entered the back-end advanced packaging lithography market, with the acquisition of Azores Corp., and the introduction of a new 2X reduction stepper called the JetStep.
The ConFab, Solid State Technology’s invitation-only event for the semiconductor industry, took place in June, with presenters from top companies and analyst firms. If you couldn’t be there, check out all the coverage from the event -- reports, presentations, video interviews and more.
EMCORE, compound semiconductor-based components and subsystems supplier, will replace multiple legacy manufacturing systems in its compound semiconductor fab and back-end packaging operations with the Camstar Enterprise Platform.
CEA-Leti presented research updates alongside SEMICON West this week. After the talks on device architecture, 3D and 2.5 packaging interconnects, large-scale computing and power consumption, and more, CEA-Leti’s researchers joined Solid State Technology to talk about their fields of interest.
OSRAM AG will build a new LED assembly plant in Wuxi, Jiangsu, China, packaging LED chips fabbed at its Regensburg, Germany and Penang, Malaysia wafer processing facilities.
A main focus of this year’s Electronic Components and Technology Conference (ECTC), held this week in San Diego, is 3D integration and through silicon vias (TSVs).
The 15th IITC (International Interconnect Technology Conference) opened Monday, June 4 at the Doubletree Hotel in San Jose, CA. Recurring themes this year were variations on 3D and TSV, novel systems and packaging, and back end memory. Mike Fury reports.
Luc Van den hove, president and CEO, imec, spoke with Solid State Technology, covering imec’s major announcements and research presentations to take place during SEMICON West 2012.
Daewon Innost achieved what it says is the LED industry’s best thermal dissipation performance on its Glaxum LED Array family, based on the proprietary Nano-Pore Silicon Substrate (NPSS) technology.
Singapore’s A*STAR’s Institute of Microelectronics (IME), and Hitachi Chemical Co., will be collaborating on a joint research program to develop high performance material technologies for thin wafer processing for 3D IC packaging.
The field of power electronics, the application of electronics for the control and conversion of electric power, is underpinned by basic electrical principles that were established in the distant past by the pioneers of electrical science. But today, the need to supply, modify and control the voltage, current or frequency of electric power arises in a vast number of applications and products spanning a huge range in terms of power handling capability.
Devan Iyer, director of Semiconductor Packaging in Texas Instrument’s Manufacturing Group, has joined the advisory board of The ConFab.
Four of the leading micro- and nanoelectronics regions in Europe are joining forces to form a cluster alliance called “Silicon Europe.”
STATS ChipPAC says it has expanded its through-silicon via (TSV) capabilities with a 300mm mid-end manufacturing operation targeting mid-end-of-line semiconductor manufacturing, including microbump technology down to 40μm, temporary bond/de-bonding, backside via reveal, isolation, and metallization.
Hesse & Knipps, Inc., the Americas subsidiary of Hesse & Knipps Semiconductor Equipment GmbH, added the HBK08 Loop Former Bondhead to its BONDJET BJ935 and BONDJET BJ939 fully automatic heavy wire bonders.
At the upcoming International Electron Device Meeting, Macronix researchers will describe how they built flash memories that could heal themselves by means of tiny onboard heaters that provide thermal annealing just at the spots where it is needed.
The 58th annual IEDM will take place December 10-12, 2012 at the San Francisco Hilton Union Square, preceded by a full day of Short Courses on Sunday, Dec. 9 and by a program of 90-minute afternoon tutorial sessions on Saturday, Dec. 8.
The first working 3D NAND flash memory at sub-40nm feature sizes will be described by Macronix researchers at this year’s International Electron Devices Meeting (IEDM).
At this year’s IEDM, a team led by Korea’s Gwangju Institute of Science and Technology will detail a high-speed pattern-recognition system comprising CMOS “neurons” and an array of resistive-RAM (RRAM)-based “synapses,” which demonstrated STDP, a brain-like function.
Deca Technologies, an electronic interconnect solutions provider to the semiconductor industry, today announced it has named semiconductor industry veteran Chris Seams its new CEO.
In a keynote at the IEEE International Interconnect Technology Conference (IITC), Douglas Yu from TSMC talked about Moore’s Law scaling becoming increasingly difficult.
Advanced packaging technology is undergoing dramatic changes as the smart phones and new sensor technologies demand continued improvements in form and function.
Fab equipment spending will grow two percent year-over-year (US$ 32.5 billion) for 2013 and about 23 to 27 percent in 2014 ($41 billion) according to the May edition of the SEMI World Fab Forecast.
Signetics Corporation today announced that it has again approved capex plans that will further expand their capacity for flip chip package assembly at their factory in Paju, South Korea.
Mentor Graphics Corp. today announced significant achievements in its continued collaboration with TSMC on 20nm physical verification kit optimizations.
The semiconductor industry’s march toward broader 3D IC integration marked an important milestone this week at ECTC 2013, with the report of an advanced new temporary bonding solution for 3D TSV semiconductor packaging.
OMRON Corporation today announced that they have finished development work on the world's first infrared sensor manufactured with wafer-level vacuum packaging technology to create a 16x16 element MEMS non-contact infrared thermal sensor capable of highly precise 90-degree area detection.
Mentor Graphics Corp. and Tezzaron Semiconductor Corp. today announced they are collaborating to integrate the Mentor Calibre 3DSTACK product into Tezzaron’s 3D-IC offerings.
Yole Développement announced its 2.5D, 3DIC and TSV Interconnect Patent Investigation report. For this analysis of 3D packaging technology patents, more than 1800 patent families have been screened.
MOSIS, a provider of low-cost prototyping and small volume production services for custom ICs, has teamed up with imec, Ireland's Tyndall National Institute and ePIXfab, the European Silicon Photonics support center providing low-cost prototyping services for photonic ICs.
Endicott Interconnect Technologies, Inc. (EI) announced that its System-In-Package (SiP) technology performed successfully in a military test of a small hit-to-kill interceptor designed to defeat rocket, artillery and mortar attacks.
The worldwide semiconductor assembly and test services (SATS) market totaled $24.5 billion in 2012, a 2.1 percent increase from 2011, according to final results from Gartner, Inc.
Amkor Technology, Inc. today announced that Stephen D. Kelley has been appointed to serve as president and chief executive officer and as a director of the company, effective May 8, 2013.
LFoundry to manufacture wafers for Aptina following LFoundry’s purchase of Micron’s Avezzano, Italy semiconductor fabrication facility.
Increased spending in NAND and flash by Micron, LEDs by Philips and Osram, and continued investments by GLOBALFOUNDRIES will create new opportunities for equipment and materials suppliers in Southeast Asia.
Sales in March 2013 were up slightly compared to February 2013 and March 2012.
Silex Microsystems, the world’s largest pure-play MEMS foundry, today announced that it has joined an international European Union-funded program aimed at developing a new MEMS manufacturing platform based on advanced inkjet-based printing technologies.
North America-based manufacturers of semiconductor equipment posted $1.14 billion in orders worldwide in March 2013 (three-month average basis) and a book-to-bill ratio of 1.14, according to the March Book-to-Bill Report published today by SEMI.
Over the last few years, glass has gained considerable interest from the semiconductor industry due to its very attractive electrical, physical and chemical properties, as well as its prospects for a relevant and cost-efficient solution. The application scope of glass substrates in the semiconductor field is broad and highly diversified.
At this week’s International Solid State Circuits Conference (ISSCC 2013), imec and Holst Centre presented an ultra-low power processor that operates reliably at near-threshold voltages.
CEA-Leti today announced that it will coordinate a four-year project aimed at building a European-based supply chain in silicon photonics and speeding industrialization of the technology.
STMicroelectronics announced today another milestone in its testing of its 28nm FD-SOI Technology Platform.
80 percent of the devices used for portable and mobile applications are currently manufactured on 200mm or smaller wafers. How this plays out going forward could change who the dominant players will be.
Advanced packaging requirements are driving the evolution of back end manufacturing to become more similar to the front end.
The development of innovative technologies that solve the critical issues for the transition and adoption of 450-mm manufacturing will be the defining factor for whether a company merely survives or thrives.
Worldwide silicon wafer revenues declined by 12 percent in 2012 compared to 2011, according to the SEMI Silicon Manufacturers Group (SMG) in its year-end analysis of the silicon wafer industry.
Although many are small companies manufacturing low-pin count devices, all of the world’s “Top 10” OSAT, Outsourced Semiconductor Assembly and Test, players have one or more assembly and testing facilities in China.
In the first of two installments, we examine the global issues facing the semiconductor industry, as released by Linx Consulting in The Econometric Semiconductor Forecast.
A new econometric semiconductor industry forecast predicts semiconductor wafer area production to grow slightly less than 6% in 2013, according to Linx Consulting.
SEMATECH announced today that Araca Inc., a leading provider of products and services for chemical mechanical planarization research and development, and the International SEMATECH Manufacturing Initiative (ISMI) are partnering to deliver CMP processing and productivity solutions to help chip manufacturers increase yields, reduce equipment downtime and lower consumables costs.
Dow Corning and IBM scientists unveiled a major step in photonics yesterday at the Photonics West conference, using a new type of polymer material to transmit light instead of electrical signals within supercomputers and data centers.
Spending on research and development by semiconductor companies grew 7% in 2012 to a record-high $53.0 billion, even though the semiconductor market declined 1% to $317.6 billion.
IPC recently released the C revision of IPC-7095, Design and Assembly Process Implementation for BGAs.
STATS ChipPAC and UMC announced the world's first demonstration of TSV-enabled 3D IC chip stacking technology developed under an open ecosystem collaboration.
Renesas and J-Devices signed a memorandum of understanding regarding the transfer of the semiconductor back-end production business of three facilities operated by Renesas’ wholly owned manufacturing subsidiaries
GlobalFoundries says it plans to build a $2 billion "Technology Development Center" R&D facility at its Fab 8 campus in Saratoga County, NY, for semiconductor technology development and manufacturing: EUV lithography photomasks to new interconnect and packaging technologies enabling 3D chip stacking, "and everything in between."
Samsung tops list; IC foundries expected to show biggest capacity gains through 2017.
In February, Infineon received the first customer go-aheads for products of the CoolMOS family produced by the 300-millimeter line at their site in Villach, Austria.
New marketing and technical support center opened in Reading, UK.
Fab equipment spending for Front End facilities is expected to be flat in 2013, remaining around $31.7 billion, increasing to $39.3 billion in 2014 — a 24% increase.
EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today announced that it is developing equipment and process technology to enable covalent bonds at room temperature.
Peregrine Semiconductor Corporation, a fabless provider of high-performance radio frequency integrated circuits (RFICs), yesterday announced plans to collaborate with Murata Manufacturing Company on a multisource arrangement for RF switches and other components based on Peregrine’s proprietary UltraCMOS technology
Flip-Chip is big on value: in 2012, it was a $20B market, making it the biggest market in the middle-end area, and Yole Développement expects it to continue growing at a 9% clip, ultimately reaching $35 billion by 2018.
Foundry to use wafers for 3D IC and advanced packaging volume production applications.
Signetics Corporation today introduced their new MapBGA package to the industry. This alternative to standard PBGA packaging has improved reliability and design flexibility due to its unique assembly process.
This week, India’s Finance Minister P Chidambaram offered incentives to chip makers to set up headquarters in India, in an effort to encourage local electronics manufacturing. However, the response from the industry has been less than positive. Many believe that is it is a good start, but far from sufficient.
Tokyo-based Asahi Glass Co., Ltd. and nMode Solutions Inc. of Tucson, Arizona, have invested $2.1 million to co-found a subsidiary business, Triton Micro Technologies , to develop via-fill technology for interposers, enabling next-generation semiconductor packaging solutions using ultra-thin glass.
Wafers with a diameter of 450mm enable the micro-chip industry an increase in yield of up to 80%. This leads to an enormous increase in productivity. In order to control the product quality, these wafers receive a specific marking from the manufacturer.
The Temescal Division of Ferrotec Corporation today announced the Temescal UEFC-5700, a ultra-high efficiency electron beam metallization system for lift-off compound semiconductor applications.
In 2012, global PCB industry saw a jump in terms of output value, benefitting in a large part from the rapid growth in the shipment of Apple and Samsung. However, there is no such possibility of a huge jump in 2013, as the report states the expected growth rate will slow down to 2.7%.
OneChip Photonics this week revealed strategic, outsourcing plans to expand into new markets, with announcements of newly-established relationships with semiconductor foundry GCS and wafer supplier IQE. Both announcements related to OneChip’s bigger, strategic plan to expand its services into the high-volume DCI market.
GLOBALFOUNDRIES today announced the accomplishment of a key milestone in its strategy to enable 3D stacking of chips for next-generation mobile and consumer applications.
Applied Materials (AMAT) speaks about its new conductor etch system -- the Centris AdvantEdge Mesa Etch -- released at SEMICON Japan this week. The company sees the gap in the lithography roadmap is an etch opportunity. Thorsten Lill, VP Etch Business Group, at Applied, told ElectroIQ that new steps in advanced transistors, double-patterning, and advanced packaging are driving growth in the conductor etch market (~$1.6B market in 2010).
Fabless giant Qualcomm has made two deals to reserve leading-edge semiconductor manufacturing capacity: one with longtime partner TSMC, and the other with upstart GlobalFoundries.
Jeff Schake, et al, DEK Printing Machines, discuss the flatness characteristics of available wafer pallets, and use them in an experiment with thinned wafers in automated printing. With thin wafers, and the requirement for low coating thickness, the wafer-support tooling surface metrology should have an appreciable impact on coating thickness control.
In these three video interviews from SEMICON West 2010, Leti research directors speak with senior technical editor Debra Vogler. Yannick Le Tiec discusses cleaning; Michel Brillouet speaks on 3D packaging work, and Didier Louis updates us on advanced lithography.
The semiconductor industry is at its most profitable point now than any other time in the past decade thanks to industrywide efforts to aggressively manage costs and capacity -- but wild optimism about surging growth forgets the truth that this recovery only resets to levels from three years ago, according to iSuppli.
The IC community has been searching for a manufacturable low-k dielectric which could scale to below K = 2.0, says Dr. Phil Garrou. Microindent photos of uLK 124, released by SBA Materials show a clean ductile indent. SBA reports that their uLK materials can be integrated into existing fab lines using equipment and process flows already in place.
LEDs, SiGe semiconductors, and WLP bumps each present their own challenges to metrology systems, says Alon Kapel, Jordan Valley Semiconductor.
In an exclusive series of blogs, imec reports from its International Technology Forum (ITF) last week in Brussels. Els Parton, science editor, imec, shares Jy Bhardwaj's (Philips Lumileds) points about LEDs costs improvements.
Tien Wu, ASE; Rama K. Shukla, Intel; and Luc Van den hove, imec, are the honored presenters for SEMICON West 2011.
Diodes Incorporated (Nasdaq:DIOD) began packaging MOSFETs in the miniature DFN1212-3 package for cooler operation than the equivalent-footprint SOT723 package.
The Design Automation Conference (DAC) is soliciting semiconductor industry experts for participation in invited sessions, panels, and other events at the 49th DAC, June 3-7, 2012 in San Francisco, CA.
The final day of SEMI's Strategic Materials Conference (SMC) dug deeper into rare earth elements supplies, deposition precursors, projections for semiconductor packaging materials and fab equipment, and a geopolitical perspective on relevant markets, reports Techcet's Michael A. Fury.
Zvi Or-Bach, MonolithIC 3D, describes the TSV-beating monolithic IC fab process, and argues for scaling "up" rather than down. Or-Bach compares the costs of further semiconductor scaling to advanced packaging.
Twenty-eight companies get the nod from Intel's latest supplier awards, including four "Achievement" award winners.
Ivo Bolsens, Xilinx, compares crossover cars -- sports car performance with station wagon utility -- to semiconductor ASICs (high-performance) and FPGAs (flexible, easy to use, less NRE). The semiconductor industry needs a programmable platform that has ASICs' capabilities.
Michael A. Fury of Techcet blogs about the papers he saw at IEDM 2010. The final afternoon continued with 4 parallel sessions and the halls and conference rooms were as crowded as they had been all week. I was compelled to spend nearly all of my time in the novel process technologies session.
Integrated Silicon Solution Inc. (Nasdaq: ISSI) completed the spin-off of its subsidiary, Giantec Semiconductor Inc., which focuses on the ASSP business that includes EEPROM and SmartCard products.
Sales of semiconductor materials rose 25% in 2010 to a new record $43.55B thanks to surging device shipments, according to final tallies from SEMI.
This article, the first in a series of three on 3D packaging technology, summarizes information presented during a November 2007 webcast produced by Advanced Packaging magazine. Participants were Jean-Christophe "J.C." Eloy, founder and GM of Yole D
The demand for smaller sizes and lighter weights in consumer electronic devices is feeding the demand for continued package miniaturization. With expanded systems integrated onto ultra-thin wafers, these exotic final assemblies are extremely delicate. Creating complex nano-devices that function is not enough. They must keep working, and to do that, they need protection.
Flip chip technology was introduced in the early 1960s and used in the computer manufacturing process. Development for automotive applications followed in the 1970s. Since then, the importance of the flip chip technology has increased due to size, performance, flexibility, and cost compared to other packaging methods.
Semiconductor assembly and test service (SATS) houses, packaging foundries, and integrated device manufacturers (IDMs) are increasingly turning to wafer-level packaging (WLP) to address the demand for miniaturization, lower cost, enhanced functionality, and higher reliability in today's personal digital devices.
"Substrates: The Foundation of Semiconductor Packaging," MEPTEC's final technical symposium of 2007, identified cost and co-design as pivotal issues for the most critical component of semiconductor packaging.