(March 5, 2008) In the semiconductor industry, device characterization or screening occurs through the use of two related tests: burn-in and elevated temperature device characterization, with both tests using temperatures >99°C: the first to accelerate device failure modes that could be related to those in the field, and the second to simulate functional device behavior while characterizing its performance level.
(March 5, 2008) This article is the third in a series on 3D packaging technology, and summarizes information presented during a January 2008 webcast hosted by Advanced Packaging magazine. Participants were: Fred Roozeboom, Research Fellow, NXP Semiconductors and professor at TU Eindhoven; Kai Zoschke, Research Engineer for Fraunhofer IZM; and Thorsten Matthias, Director of Technology North America, EV Group.
By Scott D. Szymanski, March Plasma Systems
Commercially available plasma treatment systems can be used for a variety of wafer-level packaging (WLP) process steps including removal of photoresist residue after development (i.e. descum); organic, metal, and oxide contamination removal; wafer surface cleaning; and other processes. Through various alterations to the plasma chemistry or chamber configurations, these systems meet demanding WLP processing requirements.
Invensas has "acquired" dozens of 3D IC packaging patents from Allvia, and the two have agreed to further collaboration in the area.
2.5D, 3D and Beyond - Bringing 3D Integration to the Packaging Mainstream will take place November 9 in Santa Clara, CA. The MEPTEC conference follows the trend of 3D and 2.5D packaging moving from roadmap to factory production.
ON Semi believes that its SANYO Semiconductor division's Thai operations in the Rojana Industrial Park have been severely damaged by Thailand's flood. Another facility in Bang Pa In, previously unaffected, is now flooded. ONNN says none of its employees in Thailand have been endangered by flood waters on-site.
Spansion Inc. (NYSE:CODE) will consolidate its 2 semiconductor assembly and test services (SATS) operations, closing its facility in Kuala Lumpur, Malaysia, to reduce costs by about $30 million annually.
Multitest debuted the Quad Tech concept, next-generation vertical contact technology with a barrel-less architecture.
Global Unichip Corp. (GUC; TW:3443) refined its business and technology model to become a full-service, flexible ASIC company. President Jim Lai refers to the model as GUC's branded Flexible ASIC Model, covering SoC integration, implementation methodologies, and integrated manufacturing.
ACM Research Shanghai, Ltd., introduced the integrated Ultra iSFP stress-free polishing (SFP) semiconductor manufacturing tool for 65-45nm copper (Cu) interconnects, improving through silicon vias (TSV) with better heat dissipation.
Levi & Korsinsky is bringing a class action lawsuit against OmniVision Technologies Inc. (NASDAQ:OVTI) on behalf of stockholders that allege that OmniVision failed to disclose properly the loss of an exclusive contract with Apple for image sensors, in-house production delays, as well as other counts.
EV Group (EVG) launched a suite of temporary bonding and debonding equipment modules that support ZoneBOND technology.
North Dakota State University, Fargo, researchers have developed a packaging technology using Thermo-Mechanical Selective Laser Assisted Die Transfer (tmSLADT) to reduce the size and cost of microelectronics packages.
Xilinx Inc. (Nasdaq:XLNX) began shipping its Virtex-7 2000T field programmable gate array (FPGA), a programmable logic device with 6.8 billion transistors: 2 million logic cells, a die-stack architecture, low power consumption, and a more flexible design than large ASICS and monolithic FPGAs.
Brewer Science Inc. and EV Group (EVG) will both commercialize ZoneBOND technology for temporary wafer bonding, thin wafer processing, and debonding applications.
Nanotech accelerator SVTC Technologies, wet chem equipment maker Amerimade Technology, and chemicals company Shanghai Sinyang Semiconductor Materials will collaborate on electroplating processes for TSV that are production-ready for advanced packages and MEMS.
NEXX Systems shipped a Stratus electrochemical deposition tool to Nantong Fujitsu Microelectronics Co. Ltd. (NFME), based in Jiangsu province, China. NFME will use the Stratus for copper pillar and RDL advanced packaging applications.
SUSS MicroTec, in partnership with temporary bonding adhesive maker TMAT, will deliver SUSS MicroTec's new-generation high-volume temporary wafer bond tool clusters to a leading IDM.
MVTS Technologies opened new offices in San Jose, CA; Penang, Malaysia; and Hsinchu, Taiwan to support growing demand for test, assembly, and other IC production equipment and services among semiconductor manufacturers.
ERS uncrated the ERS AirCool 3 wafer thermal test system with modular options and easy integration into all major wafer prober systems.
At the IMAPS 44th International Symposium on Microelectronics in Long Beach, CA, Voya Markovich, well-known industry PCB and packaging expert, took over the reins as the organization
Steven J. Adamson, marketing specialist with Nordson ASYMTEK, received the Daniel C. Hughes, Jr., Memorial Award, for the greatest contribution to IMAPS and the microelectronics packaging industry.
EV Group (EVG) will work with Fraunhofer IZM's ASSID research center to develop temporary bonding/debonding technologies for thicker die structures, some as large as 600
Cascade Microtech Inc. debuted InfinityQuad, a multi-contact probe head capable of automatically probing aluminum (Al), copper (cu), or gold (Au) pads as small as 30 x 50
All Silicon System Integration Dresden (ASSID) installed an Altatech 300mm CVD tool for dielectric film deposition on advanced through silicon vias (TSV), with diameters as small as 10
DuPont Microcircuit Materials, part of DuPont Electronics & Communications, uncrated its DuPont GreenTape 9K5 low temperature co-fired ceramic (LTCC) packaging material, offering good dielectric constant properties for higher speed, frequency, and reliability applications.
Test equipment provider Multitest installed a MT9928 XM Gravity Test Handler at a semiconductor production facility after a 1-year+ benchmarking against two major competitors.
Thanks to MEMS, 3D packaging, LEDs, power devices, and other applications, thinned wafers will be the majority of wafers in the market by 2016, according to Yole D
Analog Devices Inc. (ADI) introduced a packaging technology for digital isolators that achieves a minimum of 8mm creepage distance required by global industry standards to ensure safe operation in high-voltage medical and industrial applications.
Tamar Technology shipped its first fully automated WaferScan system to a major semiconductor fab. The system performs TSV etch depth, deep trench depth, wafer thickness, photo-resist thickness, and hole diameter metrology.
IMAPS 2011, the 44th International Symposium on Microelectronics, will take place in less than one week at the Long Beach Convention Center. Ahead of the show, here are some of the highlights for attendees.
Rudolph Technologies Inc. (NASDAQ:RTEC) shipped its Wafer Scanner 3880 3D Inspection System, multiple NSX Macro Defect Inspection Systems and its Discover Yield Management Software Suite to a leading semiconductor manufacturer for use in developing through silicon via (TSV) structures.
Amkor will acquire Toshiba Electronics Malaysia Sdn. Bhd., Toshiba
Samsung Electronics Co. Ltd. developed a high-performance 64GB embedded memory with 64Gb NAND. The package contains an 8 die stack in a low profile for smartphones, tablets and other mobile devices.
Seiko Epson Corporation introduced the IP-2000 inkjet semiconductor marking system to print identification data on the surface of a semiconductor package without the danger of damage from laser cutting
Cascade Microtech (NASDAQ:CSCD) completed the sale of its test socket manufacturing business for $550,000 to R&D Interconnect Solutions. Cascade's board of directors also authorized a stock repurchase program under which up to $2,000,000 of its common stock may be repurchased.
In a podcast interview with ElectroIQ.com, Ziptronix president & CEO, Daniel Donabedian, and company CTO, Paul Enquist, discussed both the Ziptronix wafer bonding technology and their partnership with Sony.
By R. Wayne Johnson, Ph.D., Auburn UniversityWhile $4/gal.gasoline prices have dropped, it is inevitable they will rise again. So what does this have to do with advanced packaging? A lot! While we hear discussions of alternate energy, we will continue to use oil for the foreseeable future. Electronics (and advanced packaging) are important for measurements during well drilling and for production management over the life of the well.
Electroless Plated Thin-film Resistors on Organic SubstratesBy Swapan K. Bhattacharya, Premjeet Chahal, and John Papapolymerou, Georgia TechThin film resistors on organic substrates can be realized by vacuum deposition, direct foil lamination, and electroless and/or electroplating. This article introduces the feasibility of electroless plated thin-film Ni-W-P and Ni-P resistors on LCP substrate using low-cost PCB process technology.
GLOBALFOUNDRIES entered into a strategic partnership with Amkor (NASDAQ:AMKR) to develop integrated semiconductor assembly and test processes for advanced silicon nodes. The aim is integrated fab-bump-probe-assembly-test steps that can be commercialized across multiple customers and end-market applications.
Cabot Corp. (NYSE:CBT) will sell its Supermetals business to Global Advanced Metals (GAM), a supplier of tantalum ore to the Supermetals business.
The SMTA will host conference events with Amkor, Research in Motion, and TechLead Corporation on package-on-package (PoP) 3D stacking at SMTA International (SMTAI), October 16-20 in Fort Worth, TX.
SATS provider STATS ChipPAC Ltd. (SGX-ST:STATSChP) honored its top materials and equipment suppliers in 2010, recognizing "intense focus and commitment to performance, quality, cycle time, and cost."
National Instruments (Nasdaq: NATI) added per-pin parametric measurement unit modules and source measure unit modules to its PXI platform for semiconductor characterization and production test.
Semiconductor packaging and test provider STATS ChipPAC Ltd. (SGX-ST: STATSChP) welcomed Pasquale Pistorio as an advisor to its Board of Directors.
Compugraphics International is widening its line of photomasks to include larger-area products up to 16 in2, responding to customer demand for wafer-level packaging and other semiconductor and optical applications.
An IDM recently performed side-by-side comparisons of a Multitest Mercury test contactor and an "established contactor of an incumbent Asian competitor" during high-volume production package testing.
The annual Known Good Die (KGD) conference, taking place Nov. 10 in Santa Clara, CA, will address semiconductor die testing, assembly, manufacturing, and business challenges, with the tagline "KGD in an Era of Multi-Die Packaging and 3D Integration."
Nemotek Technologie uncrated the Exiguus, with a VGA wafer-level camera integrating wafer-level optics assembled with CMOS image sensors (CIS).
The 2011 iNEMI Roadmap, published by the International Electronics Manufacturing Initiative (iNEMI), includes a new chapter on MEMS and sensors, and an expanded chapter on packaging to include substrates discussions.
Johnstech International Corporation is rereleasing the configurable ROL 200K (Kelvin) Test Contactor as the ROL 200KR Kelvin-Ready Test Contactor for both pad and leaded style devices.
Tessera Technologies appointed Anthony J. Tether, Ph.D., to its board of directors. Tether is CEO of The Sequoia Group, and has held executive positions at DARPA and Ford Aerospace Corp., among others.
SEMI will hold the first-ever SiP Global Summit, September 7-9, co-located with SEMICON Taiwan. Three forums cover system in package (SiP) test, the "3D IC era," and the requirements of mobile electronics.
Doug Dixon from Henkel explains two announcements the company made at SEMICON West: a silver sintering material that requires no pressure, and joint work with STMicroelectronics on conductive die attach films for very small package configurations.
In these 2 video interviews from SEMICON West 2011, ESI technologists John Sabol and Vernon Cooke discuss what LED chips require on the back-end manufacturing line, starting at wafer scribing and moving on through test.
Nordson MARCH and Science College of Donghua University, Shanghai, China launched a joint laboratory for plasma research and education. The college and supplier will share equipment, research projects, personnel resources, and additional resources as needed.
Amkor's Ron Huemoeller shares his thoughts about two panels from SEMICON West, on 2.5D silicon interposer packaging technologies and its supply chain, and 3D packaging technology and its ecosystem.
The University of Waterloo, Ontario, through the Applied Research and Commercialization Initiative, is supporting several companies researching and developing new products. One company receiving aid from the school is Microbonds, maker of semiconductor bonding wire.
Multitest launched a 16-site tri-temp pick-and-place handler, the MT9510 x16. The platform can be kitted to test a range of semiconductor packages.
Amkor has extended its Quad Flat No-Lead (QFN) package design kit to be the first such kit available for Agilent Technologies' Advanced Design System (ADS) electronic design automation software.
Industry efforts to transition from gold to copper wire are accelerating as prices for gold continue to spike to near record levels, notes TechSearch International in a new report.
Nomura Principal Finance Co. Ltd., a wholly owned subsidiary of Nomura Holdings Inc., transferred all the shares it owns in Eastern Co. Ltd. to Eastern.
Apple Inc.'s iPad has thus far thwarted competitive tablets in design efficiency, according to an IHS iSuppli Teardown Analysis of eight tablet models from IHS. Major savings come from Apple's control of chips like SDRAM and applications processors.
Great Lakes Engineering will supply DEK's VectorGuard packaging and surface mount assembly stencil system to customers in 32 states and 3 countries.
Agilent and UC Davis established the Davis Millimeter Wave Research Center to develop advanced mm wave and THz systems for radar, sensors, imaging systems, communications and integrated passive devices (IPDs) found in electromagnetic metamaterials and antennae.
Data I/O Corporation (NASDAQ: DAIO) debuted the RoadRunner3 in-line programming system, a just-prior-to-placement programming tool with modules to automate processes and eliminate operator interventions.
SATS provider Unisem purchased a LTX-Credence PAx RF Test System for its Sunnyvale, CA, test development center, joining other recent test/wafer equipment purchases at the site.
Texas Instruments has shipped more than 30 million units of its PowerStack packaging technology, a combination of chip stacking and clip bonding that is designed to improve performance and chip densities in power management devices.
EV Group (EVG), wafer bonding and lithography equipment supplier, began a manufacturing capacity expansion at its Austrian headquarters, adding floorspace, equipment, worker comforts, and a state-of-the-art visitor area. EVG will hire about 100 new staff members as part of the expansion.
3D semiconductor packaging processes involve various groups, and standards are important in the hand-offs between them, explains Mark Berry, sales director at Metryx. He covers how to use metrology to protect wafer yields in 3D packaging.
Dr. Phil Garrou summarizes the significant commercial strides made over the past 12 months in 3D IC integration -- as defined vs. other "3D" technologies -- thanks to the promised combination of low cost and high performance.
At SEMICON West, 100+ attendees gathered at the Suss MicroTec workshop "3D Integration: Are we there yet?" to hear technical experts from around the globe to present updates on the status of 3D technology.
Nippon Micrometal Corporation (NMC) licensed their single-layer-palladium (Pd) coated copper (Cu) bonding wire for LSI packaging to Tanaka Denshi Kogyo K.K., bonding wire manufacturer and traditionally a competitor.
Optomec Aerosol Jet product manager Mike O’Reilly will give a presentation titled "Aerosol Jet Printing as an Alternative to Wire Bond and TSV Technology for 3D Interconnect Applications" at the IMAPS Device Packaging Conference on March 9.
IMT introduced its hermetic gold-to-gold (Au-Au) thermo compression bonding for wafer-level packaging (WLP). In development for nearly a year, this bond is being actively used in production.
A new global R&D consortium is seeking companies to join its efforts working on embedding thin-film passive components into packages using through-silicon vias (TSV), for use in smart mobile electronics and implantable bio-electronic systems.
The new gold/tin (AuSn) process from Stellar Industries is ideally matched to Stellar’s proprietary CPU copper on AlN submounts with its sharp guillotine edge for precise edge alignments.
Weeks after announcing a 40nm 8GB DDR3 memory with 3D through-silicon vias (TSV), Samsung is showing a wide I/O 1GB DRAM also utilizing 3D TSVs, targeting mobile applications.
Multitest received its fifth full purchase order for its InCarrier device transfer system with InStrip test handling system adapted to metal frame-based carriers.
The Unifire 7900IR provides 3D inspection of wafer-scale packaging features as well as registration for wafer-to-wafer bonding applications for use in advanced wafer scale packaging process control.
As gold becomes more expensive, copper wire bonding becomes more appealing for chip packaging. Reverse bonding, fine-pitch bonding, looping, second bonds, and other technologies are ramping on roadmaps, according to Kulicke & Soffa (K&S).
CEA-Leti, in a multi-partner project with SET, STMicroelectronics, ALES and CNRS-CEMES, will demonstrate high-alignment-accuracy chip-to-wafer structures made by direct metallic bonding. Such structures are required for high-performance 3D ICs, and possibly microelectronics, optoelectronics, or MEMS.
Tessera Technologies Inc. (NASDAQ:TSRA) announced that on February 17, 2011, it sent Amkor Technology, Inc. an official notice of termination of their license agreement with Tessera. The two companies are currently in arbitration regarding multiple issues.
Jamal Izadian, co-founder & president of RFCONNEXT, makes the case for shaped membrane transmission lines (SMTL) for use in high-speed 3D packaging applications. SMTL supports and improves flip-chip, micro-bumping, wafer thinning, system-in-package (SiP), package-on-package (PoP), and other packaging processes by extending the bandwidth and high-speed limits of these technologies.
inTEST Corporation (NASDAQ: INTT) subsidiaries, Temptronic and Sigma Systems, both in Sharon, MA, will begin operating under the umbrella trade name, inTEST Thermal Solutions Corp.
Agilent Technologies Inc. (NYSE:A) expanded its mixed-signal and digital-storage oscilloscope portfolio with 26 new models that comprise its next-generation InfiniiVision 2000 and 3000 X-Series. Entry-level mixed-signal oscilloscopes and an integrated function generator are part of the 2 new product groups.
STATS ChipPAC launched fcCuBE technology, an advanced flip chip packaging technology that features copper (Cu) column bumps, bond-on-lead (BOL) interconnection and enhanced assembly processes. STATS ChipPAC claims the flip chip package is cost-comprable to standard packaging processes, and compatible with shrinking semiconductor device nodes down to 28nm.
Camtek Ltd. (Nasdaq:CAMT; TASE:CAMT) received an order for multiple wafer inspection systems from one of the world's largest manufacturers of CMOS image sensors (CIS).
InVisage Technologies, image sensor technology start-up, received its series C round of venture funding, led by Intel Capital. The undisclosed amount will be used to bring the company's quantum-dot-based QuantumFilm technology and products into mass production.
Palomar Technologies, precision microelectronics and optoelectronic packaging systems provider, will hold meetings at Stategies in Light to discuss its recent upgrades to high-brightness LED (HB-LED) assembly.
Minco Technology Labs, hi-rel semiconductor die processing, packaging and test provider, appointed board member Bill Bradford as president and CEO.
Samsung Electronics began producing embedded multi-chip package (eMCP) memory for use in entry- to mid-level smartphones. The products use low power double-data-rate 2 (LPDDR2) 30nm DRAM and 20nm NAND flash memory.
Hitachi Chemical filed a lawsuit against INNOX in Taiwan, alleging infringement on Hitachi Chemical's Taiwanese patent related to die bonding film used in semiconductor packaging processes.
Optomec opened its new and expanded Advanced Applications Lab and Product Development Facility in St. Paul, MN. The facility will help Optomec grow its Aerosol Jet additive manufacturing technology for advanced printed electronics applications.
The College of Nanoscale Science and Engineering (CNSE) and Applied DNA Sciences (APDN) are partnering to prevent the counterfeiting of computer chips.
Hesse & Knipps Inc., the Americas subsidiary of Hesse & Knipps Semiconductor Equipment GmbH, will discuss "Wedge Bonding for RF and Microwave Devices" at the Advanced Technology Workshop and Tabletop Exhibition on RF and Microwave Packaging
Mitsubishi Heavy Industries launched a fully automated 12" (300mm) wafer bonding tool, Bond Meister MWB-12-ST, capable of producing 3D LSI circuits at room temperature. The 300mm bonder targets production of memory chips and MPUs.
Zymet introduced the CN-1736 reworkable underfill encapsulant for 0.4mm-pitch package-on-package (PoP) assemblies.
Increased I/O density, power/performance reqs, and other factors are increasing use of flip chip, 2.5D and 3D technologies, a boon to packaging subcontractors. But they face a challenge from foundries, and must navigate under-utilization of wire bonding capacity.
The SMTA released its call for presenters for SMTA International (SMTAI) 2012, October 14-18 in Orlando, FL. The association, along with Chip Scale Review magazine, also announced the keynote for the International Wafer-level Packaging Conference (IWLPC), held November 5-8, San Jose, CA.
Teledyne Microelectronic Technologies will expand its optical packaging portfolio in a partnership with Zephyr Photonics, which makes a proprietary high-temp vertical-cavity surface-emitting laser (VCSEL).
Packaging house Inari Berhad signed an MOU to acquire Amertron Global, which operates in the Philippines and China providing microelectronics and optoelectronics manufacturing services.
Multitest qualified its UltraFlat process for high parallel vertical probe card tests. UltraFlat provides permanent overall PCB flatness for better wafer-level test.
Hesse & Knipps Inc. introduced its next-generation BONDJET BJ93X heavy wire bonder for back-end semiconductor assembly, targeting manufacturers of power semiconductors and automotive electronics.
JEDEC Solid State Technology Association released a new standard for wide I/O mobile DRAM: JESD229 Wide I/O Single Data Rate. Wide I/O mobile DRAM increases die integration -- stacking chips with TSV interconnects with a SoC -- and improves bandwidth, latency, power, weight, and form factor.
Haruo Matsuno, president and CEO of Advantest Corporation (TSE:6857, NYSE:ATE) shares the company's major goals, including expansion into new measurement applications, utilization of cloud computing, and more.
STATS ChipPAC held the groundbreaking ceremony for a new factory in Singapore, which will enable STATS ChipPAC to expand its manufacturing capabilities for advanced wafer level technologies.
Tessera Technologies (TSRA) received a letter from Starboard Value and Opportunity Master Fund Ltd, intending to nominate 3 candidates for the TSRA Board of Directors. Tessera issued a response, saying that it has the right Board and management team in place.
NEXX Systems sold a 300mm Stratus electrochemical deposition (ECD) system to Powertech Technology for copper pillar bumps and re-distribution layers (RDL) fab, and possibly to make TSVs.
The benefits of 3D IC integration can be combined with aggressively scaled 22nm semiconductor devices, with More Moore (scaling) and More than Moore (package advances) developing in parallel but relatively independently, says Paul Lindner, EV Group (EVG).
FormFactor Inc. (NASDAQ: FORM) introduced TrueScale Matrix probe cards for 200mm and 300mm Full Wafer Contact system-on-chip (SoC) test applications.
Ron Huemoeller of Amkor presented in the Advanced Packaging session of Solid State Technology
With many advanced packaging processes taking place on the semiconductor wafer, the traditional supply chain of front-end fab at the foundry and back-end fab at the packaging and test house is falling apart. The ConFab session,
As packaging has played a larger and larger role in chip performance, form factor, and capabilities, The ConFab has increased its focus on back-end processes. Cue
Aehr Test Systems (Nasdaq:AEHR) will install an additional FOX-1 full-wafer test system at a leading flash memory manufacturer.
Displaybank published a 2009-2014 analysis of LED packages, the finished LED components used in various applications. While LED package units will grow steadily through the forecast period, revenues will remain mostly flat from 2010 to 2013.
The New York State Center of Excellence in Small Scale Systems Integration and Packaging at Binghamton University (S3IP), and Applied DNA Sciences will develop new ways to embed and authenticate DNA on various substrates. This may involve marking semiconductor packaging, and exploring rapid-reading technologies to screen chips.
Xilinx Inc. (NASDAQ:XLNX) began shipping a 3D heterogeneous all-programmable FPGA, the Virtex-7 H580T FPGA, using its stacked silicon interconnect (SSI) technology to reach up to 16 28Gbps and 72 13.1Gbps transceiver bandwidth.
Mentor Graphics collaborated with Austria Technologie & Systemtechnik (AT&S) to implement AT&S Embedded Component Package (ECP) process in Mentor Graphics
Ziptronix Inc. is helping a 3D memory device maker replace standard die stacking with its DBI wafer-stacking technology, which has been proven in image sensor packaging.
New Japan Radio Co. Ltd. adopted Tanaka Denshi Kogyo KK
Increased demand for product functionality is driving up IC packaging revenue faster -- a 9.8% compound annual growth rate (CAGR) -- than IC unit growth -- 7.3% CAGR 2010-2016, says New Venture Research (NVR).
Rudolph Technologies Inc. will deliver 14 NSX Series 320 inspection systems to a large outsourced semiconductor assembly and test (OSAT) provider.
Advanced Semiconductor Engineering Incorporated (ASE) opened its Phase 3 manufacturing facility in Weihai, Shangdong province, China, boosting discrete packaging and test capacity.
THE BEST rankings from VLSIresearch identify the highest-rated suppliers of wafer processing, assembly, and test equipment. The top 2 test equipment suppliers were just fractions apart in the rankings.
Mitsubishi Electric Corporation developed a prototype forced-air-cooled three-phase 400V output inverter with all-silicon carbide (SiC) power modules and direct lead bonding that has a power density of 50kVA per liter.
Applied Nanotech Holdings Inc. uncrated the THERCOBOND family of highly thermally conductive bonding and printed materials for power electronics and photonics packaging.
Indium Corporation acquired a manufacturing facility in Rome, NY, to expand its production capacities of indium-, gallium-, germanium-, and tin-based materials, as well as other compounds.
Invensas Corporation, Tessera subsidiary, debuted bond via array (BVA) technology, an ultra-high-I/O PoP semiconductor packaging alternative to wide-I/O TSV packaging.
Bhavesh Muni took the helm as global business director for the Advanced Packaging Technologies business of Dow Electronic Materials, covering Dow's semiconductor packaging materials product portfolio and its manufacturing capabilities.
Amkor Technology Inc. (NASDAQ:AMKR) plans to build a state-of-the-art factory and global research and development center in the Incheon Free Economic Zone, which is located in the greater metropolitan area of Seoul, Korea.
In 2012, the global IC substrate market will reach a value of USD8.67 billion, according to Research in China
Mixed-signal IC maker Silicon Laboratories Inc. (NASDAQ: SLAB) introduced a microcontroller (MCU) die sales program with a minimum order quantity of 1 wafer.
The ASM iHawk Xpress Opto Wire Bonder from backend semiconductor assembly equipment supplier ASM Pacific Technology offers new innovations in transport, copper-wire bonding, and automatic rethreading.
Kulicke & Soffa broke ground on its Singapore global headquarters expansion, near the current leased headquarters location. A state-of-the-art facility in Serangoon will bolster the company
Heraeus introduced its high-reliability composite aluminum/copper (CucorAl) semiconductor bonding wire, which offers strong mechanical and electrical bonds to semiconductor pads, with good thermal properties.
Amkor Technology Inc. (NASDAQ: AMKR), semiconductor assembly and test services provider, announced financial results for 2010, with net sales of $2.94 billion, net income of $232 million, and earnings per diluted share of $0.91. Amkor is currently planning capital additions of approximately $500 million for 2011.
Altera closed the gap on Xilinx considerably in 2010, but Xilinx's competitive 28nm product should enable it to stay at the top of the FPGA market. Start-up Achronix could be the first to reach 22nm because of its Intel connection. The Linley Group's FPGA report, "A Guide to FPGAs," covers competitors within the FPGA space, as well as FPGA adoption in the chip industry.
Hitachi Chemical has granted Henkel a worldwide license for the manufacture and sales of certain dicing die attach film.
Dave Rose, Keithley Instruments, addresses specific cabling techniques for DC, multi-frequency capacitance, and ultra-fast I-V and pulse testing, as well as the importance of proper grounding and shielding, choosing the proper interconnect for a specific measurement, and troubleshooting common interconnect problems.
SPP Process Technology Systems (SPTS) received a follow-on purchase order from CEA-Leti for its Sigma fxP PVD system. The 300mm system will be used for advanced TSV development at Leti's new 300mm fab extension in Grenoble.
FleX Silicon-on-Polymer replaces the mechanical substrate of a traditional silicon wafer with a pliable polymer. Compatible with CMOS wafers from varioius foundries, FleX is a wafer-scale process that can be used to produce single die up to full 200mm flexible wafers.
ElectroIQ caught up with Suresh Ramalingam, director of advanced package design and development at Xilinx, at the January MEPTEC luncheon, where he gave a presentation on the company's stacked silicon interconnect technology. In an interview with Debra Vogler, Ramalingam discusses SSIT in relation to die stacking and TSV.
Under a 3-year, $9.3 million contract with the Air Force Research Lab (AFRL), Camgian Microsystems will develop two ASICs with ultra-low-power characteristics: an RF transceiver ASIC will use radar-on-a-chip technology, while a DSP architecture will integrate aggressive power management.
During the past ten years, Clarkson University has received more than $1.4 million of direct and indirect (through Semiconductor Research Corporation) funding from Intel Corporation.
All the major semiconductor players are embracing 3D integration, says Simon Deleonibus. The CEA-Leti scientist and IEEE Fellow wants to see TSV mature and new technologies develop based on wafer bonding. He speaks with Debra Vogler.
Agilent Technologies Inc. (NYSE: A) enhanced the memory depth of its Infiniium oscilloscope lineup. All 30 models now ship with the industry's deepest standard memory and offer the deepest memory options, according to the company.
Creative Materials Inc. announced a new series of pressure-sensitive tapes that suit use in the fabrication of solar cells and modules; to replace solder and/or conductive adhesive connections; or as bus bar materials for a wide variety of printed electronics applications, including touch panels, LCDs, electro-chromatic displays, and electro-luminescent displays.
DelfMEMS and KFM Technology signed a common agreement to combine their expertise in RF micro-electro-mechanical systems (MEMS) and thin film packaging (TFP) technology. DelfMEMS will use the collaboration to provide packaged MEMS switches, fixed capacitors, and high-Q inductors on the same chip.
CEA-Leti signed a multiyear agreement with SHINKO ELECTRIC INDUSTRIES CO. LTD. to develop advanced semiconductor packaging technology. They will focus on volume production of silicon interposers.
Arthur W. Zafiropoulo, Ultratech, sees the 20/22nm node as a competition for gate-first and gate-last proponents to discover which will lead the semiconductor industry. Device makers that master TSV chip stacking will be the winners over the course of this decade, he says. This is an online exclusive essay in SST's Forecast for 2011: Back to Reality series.
Laurent Clavelier, head of solar technologies department at Leti, discusses the significance of Leti's IEDM paper #2.6 "Engineered substrates and 3D integration technology based on direct bonding for future More Moore and More than Moore integrated devices" with Debra Vogler, senior technical editor.
Tessera Technologies (Nasdaq:TSRA) announced that Bruce McWilliams, PhD, has resigned as a member of Tessera’s board of directors effective immediately, to devote his time and attention to the needs of SuVolta's growing business.
Brush Engineered Materials Inc. (NYSE:BW) will change its name to Materion Corporation (NYSE:MTRN) and unify all of its businesses under the new name effective March 8, 2011.
Dr. Phil Garrou looks ahead to a laundry list of changes coming in the next ITRS Update with respect to assembly and advanced packaging, including 3D integration, interposers, and applications from medical to automotive and embedded applications.
STATS ChipPAC Ltd. (SGX-ST:STATSChP), semiconductor test and advanced packaging service provider, expanded its wafer level package (WLP) offering with new 300mm manufacturing capabilities in Taiwan.
CEA-Leti is expanding its technology offering, ramping up one of Europe’s first 300mm lines dedicated to 3D-integration applications. The new line is dedicated to R&D and prototyping and includes 3D-oriented lithography, deep etching, dielectric deposition, metallization, wet etching, and packaging tools.
SEMI named Thomas DiStefano, John W. Smith Jr., and Michael Warner as recipients of the 2010 SEMI Award for North America for contributions to the development and commercialization of Micro Ball Grid Array (μBGA) technology.
JEDEC Solid State Technology Association, standards developer for the microelectronics industry, today announced that its JC-64.8 Subcommittee for Solid State Drives will target the development of standards for SSDs in applications beyond conventional disk drive form factors.
China WLCSP Co. Ltd., provider of wafer level (WLP) miniaturization technologies for the electronics industry, confirmed its commitment to the US market with the opening of a new R&D center in Sunnyvale, CA.
Environmental legislation in combination with device miniaturization will continue to drive packaging development efforts throughout 2011 and beyond, writes Doug Dixon from Henkel. And the paradigm of "smaller, thinner, more powerful" is challenging traditional design and assembly rules.
Dr. Phil Garrou takes a closer look at an IP dispute lobbed by Ziptronix against Omnivision and TSMC over low-temperature oxide bonding, used in making backside-illumination CMOS image sensors.
Fresh off 3D announcements of IBM and Samsung, several industry leaders talked about the imminent use of 3D Interposers at the RTI 3-D Architectures for Semiconductor Integration and Packaging Conference in Burlingame CA, reports Dr. Phil Garrou.
Nautic Partners has partnered with management to acquire Aavid Thermalloy LLC. Aavid designs and manufactures high-performance thermal management products used in a wide range of electronics systems and energy supplies.
Rogers Corporation (NYSE: ROG) has closed on the transaction to acquire Curamik Electronics GmbH, a manufacturer of power electronic substrate products headquartered in Eschenbach, Germany.
CoorsTek Inc., technical ceramics manufacturer, completed its purchase of the advanced ceramics business of Saint-Gobain. CoorsTek adds manufacturing facilities and product lines such as silicon carbide for semiconductors.
Trident Space & Defense, which specializes in semiconductor packaging, data storage solid state drives, high-reliability electronic components, and turnkey full-tracking ground stations, will become part of the TeleCommunication Systems Inc. (TCS) government segment, as part of an acquisition announced in 2010.
The migration to the 22nm node is about more than just scaling down, it's also about scaling up with thinner devices stacked into a single package -- and these require new manufacturing considerations with wafer bonding playing a central role, writes Bioh Kim from EV Group.
SRC and researchers from Stanford University have developed a combination of elements that yields a unique nanostructure material for packaging. This advance should allow longer life for semiconductor devices while costing less than current state-of-the-art materials.
The development effort involves the integration of defect inspection with a debonding tool. Manufacturing efficiencies, along with the ability to handle ultra-thin wafers, necessitates the integration of inspection in de-bonding applications. Rudolph is bringing its inspection technologies to this three-way collaboration to provide this integrated process control solution.
Aries Electronics, an international manufacturer of standard, programmed and custom interconnection products, now offers machined high-frequency center probe test sockets to accommodate IC devices with a lead pitch of 0.30mm.
The trend toward complex semiconductor devices is fueling demand for more advanced wafer probe cards capable of accurately and cost-effectively testing these ICs, says January Kister, Microprobe. Kister examines the variables that impact current carrying capability (CCC) during semiconductor wafer test, and describe an optimal probe design with a composite metal structure.
Dr. Phil Garrou reports on several talks and trends of note from the recent IMAPS meeting and Device Packaging Conference: the readiness of 3D IC toolsets, what's holding back Cu bonding; and rumors of interposers failing thermal tests.
Victor Moroz discusses the strong but doable effects of stress on TSVs. TSV stress ranges are comparable to the size of the TSV, and analog behaves differently than digital. Synopsys recently presented results (part of a collaboration with imec) at a SEMATECH event.
CEA-Leti and IPDiA have formed a common lab to capitalize on their complementary expertise in miniaturization and 3D integration on silicon. The common lab will develop very high-end passive components that will resist harsh environments, functional sub-mounts for LEDs, and assembly technologies.
At the recent CeBIT Fair in Hanover Germany, IBM announced that its 3D technology to appear in its Power8 processor by 2013 will incorporate microchannel cooling.
The System LSI Division of Samsung Electronics Co. Ltd. has licensed the OptiML Zoom image enhancement solution from Tessera Technologies Inc. (NASDAQ:TSRA).
GE's prototype thermal interface material, developed with nanotechnologies, suits high-heat, high-reliability applications in mobile devices, aviation electronics, and other systems.
Amid questions about the impact of the Japan earthquake on electronics and semiconductor production, there's one angle that could directly affect the semiconductor packaging sector: BT resin shortages.
KLA-Tencor Corporation (Nasdaq: KLAC) introduced the ICOS CI-T620, a high-performance component inspector system for tape and reel. The CI-T620 system has dual tapers working sequentially with minimal operator intervention to increase units per hour.
TeraView and HELIOS are partnering to improve semiconductor package failure analysis using terahertz technology. The technology was originally developed with Intel and isolates faults in advanced 3D semiconductor packages.
Accretech’s next generation prober, the UF3000EX, offers high-speed wafer handling, a low-noise XY stage, and high accuracy with its OTS (Optical Target Scope) positioning technology.
Molex Incorporated, interconnect supplier, has joined with other researchers to advance the goals of the Danish SAFE (Smart Antenna Front End) project. Scheduled to span four years, the $8.7 million project is being conducted by a consortium comprising Aalborg University, Intel Mobile Communications, WiSpry and Molex.
SEMATECH experts reported new breakthroughs in wafer bonding at the 7th Annual Device Packaging Conference (DPC), March 7-10 in Scottsdale, AZ. Low-temp die tacking has yielded faster die-to-wafer integration.
Hynix Semiconductor Inc., DRAM and flash memory supplier, joined SEMATECH's 3D Interconnect program at CNSE's Albany NanoTech Complex to address industry infrastructure and technology gaps in materials, equipment, integration and product-related issues for high-volume adoption of through silicon vias (TSV).
Accel-RF Corporation installed two advanced semiconductor reliability test systems for customers in Taiwan and Japan. The systems were delivered in Q4 2010 with installation completed in early January 2011.
Multitest announced that a major fabless semiconductor manufacturer has evaluated and approved its Mercury-based wafer-level contactors for subcontractors in Asia.
The collaboration will result in new applications in multi-chip modules in radar, communication, and electronic warfare systems. The new technology platform would enable miniaturization of wireless applications that are faster, lighter and can withstand higher temperatures.
Docea Power, power and thermal analysis software supplier, released AceThermalModeler for generating compact thermal models of SoCs, 3D ICs, SiP devices, and complete boards.
Nemotek Technologie uncrated a two-element wafer-level camera, Exiguus H12-A2. The two-element lense gives Exiguus H12-A2 high resolution and low (<0.5%) distortion.
With thermal issues accounting for half of all lighting failures, and costs prohibitive to widespread adoption, assembly and packaging are keys to improving LEDs. TechSearch International tracks LED packaging materials and methods, as well as reliability and package efficiency.
Electronics System Integration Technology Conference (ESTC) 2012 seeks original papers describing research in all areas of electronic packaging, including LED packaging, flexible electronics, assembly and interconnect technologies, and more.
The 2012 IMAPS Device Packaging Conference will take place March 6-8 in Fountain Hills, AZ, with Amkor's Dr. Robert Darveaux presenting "Escalating Challenges in Developing Complex Solutions for Next Generation Package and Interconnect Technologies."
iNEMI will hold the industry kick-off for its 2013 Roadmap in an open workshop immediately following IPC APEX EXPO in San Diego, CA, March 1-2.
Finetech will donate a high-accuracy die bonder in a drawing this summer that is open to U.S. and Canadian qualified universities and colleges.
Backend packaging equipment supplier Hesse & Knipps Inc. opened a West Coast Demo and Applications Laboratory at its manufacturer rep Chalman Technologies.
Engineered Material Systems released the DA-5045-2 and DA-5045-4 high-thermal-conductivity die attach adhesives for LEDs and small power semiconductor die packaging.
Amkor (NASDAQ:AMKR) shared that it cut costs through workforce reductions in Q4 2012, and announced a voluntary retirement program in Japan to continue this initiative.
Synova SA formed an OEM agreement with its partner Makino Milling Machine Co. Ltd., wherein Makino will manufacture Laser MicroJet (LMJ) tools based on Synova technology.
BTU International Inc. won multiple orders for PYRAMAX solder reflow ovens from semiconductor assembly and test subcontractors (SATS) in Asia.
Kyocera America, Inc. doubled its flip chip assembly capacity for microelectronic devices with a $3.5 million Class-10,000 cleanroom, offering lead-free processes in San Diego.
Rudolph Technologies (NASDAQ:RTEC) delivered the first MetaPULSE metrology system to measure under bump metallization (UBM) and redistribution layers (RDL) in advanced package manufacturing.
SUSS MicroTec launched the XBC300 Gen2 high-volume 3D wafer processing tool for permanent wafer bonding, or debonding and cleaning of 200mm and 300mm wafers.
X-FAB Silicon Foundries, a More-than-Moore semiconductor foundry, has used SFT's R3D (Resistive 3D) software for its 0.18
3M launched a high-capacitance Embedded Capacitance Material (ECM), targeting improved power integrity and reduced electromagnetic interference (EMI).
Multitest launched its tri-temp 16-site pick-and-place platform, MT9510 x16, with an installation at a high-volume chip test site in Asia.
STATS ChipPAC decided not to resume semiconductor assembly operations in its Thailand plant, owing to extensive equipment and facility damages sustained during the disastrous floods in 2011.
CEA-Leti launched a major new platform, Open 3D, that provides industrial and academic partners with a global offer of mature 3D packaging technologies for their advanced semiconductor products and research projects.
Tanaka Denshi Kogyo K.K., of Tanaka Precious Metals, will establish a production subsidiary for manufacturing copper bonding wire in Taiwan, with manufacturing ramp on February 1.
Keithley Instruments Inc. upgraded the capabilities of its Automated Characterization Suite Test Environment to ACS Version 4.4. The software is used with several Keithley instrument and system configurations for automated device characterization and reliability analysis.
2E mechatronic GmbH & Co. KG designed a 3D molded interconnect device flow sensor that uses Ticona's Vectra E840i LDS laser-activated LCP for electronic circuits. The Vectra E840i forms circuits on 3D injection moldings produced with an LDS process.
Presto Engineering, integrated semiconductor test and product engineering services provider, opened its newest Hub to serve the semiconductor design community, in Israel.
The USPTO is looking to increase the diversity of honorees for its annual National Medal of Technology and Innovation (NMTI), honoring "this nation's creative geniuses."
Sony has developed a backside-illuminated CMOS image sensor that layers the pixel section with back-illuminated structures over the chips containing signal processing circuits, instead of using supporting substrates.
There are a few key attributes in new consumer electronics: a reduced footprint and/or profile, high electrical performance, fine-pitch design, custom features, and a low cost. Multi-row, wafer-level, flip-chip, and multi-chip packaging can meet these needs, say Unisem writers Rico San Antonio and Chris Stai. They compare the value of each packaging type.
Getting thinner appears to be the goal driving the market in both the wafer-level and substrate-level sectors, and innovative tooling and process technology will become paramount in addressing thinned packaging and ramping up to volume reliably, writes Dave Foggie from DEK.
Arthur Chait, president and CEO of EoPlex, describes the company’s high-volume print forming technology -- a lead carrier product called xLC-- and how it enables a cost-effective replacement for conventional quad flat pack no-lead (QFN) leadframes.
A fast-cure, low-shrinkage adhesive for optics and optical assembly, DYMAX OP-67-LS opto-mechanical adhesive cures in seconds for bonding of optical components. The product's low-shrink nature virtually eliminates movement during curing and subsequent thermal cycling.
Are we closer than we think to our needed mass production costs for silicon interposers? Phil Garrou gleans some insights from the year-ending RTI Architectures for Semiconductor Integration and Packaging conference.
Singapore's Institute of Microelectronics (IME) has launched a new multiproject wafer service for 2.5D through-silicon interposers, to provide a cost-effective platform for R&D prototyping and proof-of-concept in the technology.
Tezzaron Semiconductor has licensed patents regarding Ziptronix's direct bonding technologies, "direct bond interconnect" (DBI) and "direct oxide bonding (ZiBond), for use in 3D memory.
Dr. Phil Garrou reports from the 2nd annual Georgia Tech 2.5D Interposer Conference: what's the market projection for silicon and glass interposers, what's preventing high-volume manufacturing, and is there a crossover with flat-panel display glass manufacturing?
Alchimer SA says it is seeking partnerships with various semiconductor equipment and materials companies as it welcomes two top execs: Bruno Morel is the company's CEO since May of this year, and product development director Fr
Deca Technologies has introduced a new chip-scale packaging (CSP) product line for applications where its existing wafer-level CSP option isn't a good fit. Details and analysis to come.
Texas Instruments' MicroSiP module is the first embedded die package in high volume production. Yole D
Altera Corporation will use an exposed-die molded flip chip technology from Amkor on its 28nm Arria V FPGA. Amkor
Imec developed a via-middle approach to through-silicon via (TSV) manufacturing for 3D packaging, using wafer thinning and a silicon etch process to reveal TSV contacts on the wafer.