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Topic Index

A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 0-9


2.5D and 3D Packaging at the Tipping Point

Wed, 5 May 2014
July 1, 2014

Die stacking enables better chip performance in a small form factor, meeting the needs of smartphones, tablets, and other advanced devices. The time of HVM is fast approaching for 2.5D interposer and memory based 3D packages, with commentators expecting significant product announcements to be made over the next 12 - 18 months. This webcast will discuss why now is the right time for these next generation packages. The presenters will also discuss the backside via reveal module in the MEOL, and show how innovative wafer process engineering delivers cost and performance benefits to fuel the growth of 2.5 and first generation 3D devices.


The Rise of MEMS Sensors

Wed, 5 May 2014
June 19, 2014

MEMS have quite different process and material requirements compared to mainstream microprocessor and memory types of devices. This webcast will explore the latest trends in MEMS devices – including sensor fusion, biosensors, energy harvesting – new manufacturing challenges and potential equipment and materials solutions to those challenges.


Trends in Packaging

Wed, 5 May 2014
June 26, 2014

The industry continues to develop new approaches to packaging, including 3D integration, redistribution layers (RDL), through silicon vias (TSV), copper pillars, and wafer-level packaging (WLP). These and other approaches will be discussed in this webcast.


Advances in Wet Processing and Wafer Cleaning

Mon, 5 May 2014
August 14th, 2014

Wet Processing, including wafer cleaning, is one of the most common yet most critical processing step, since it can have a huge impact on the success of the subsequent process step. Not only does it involve the removal of organic and metal contaminants, but it must leave the surface in a desired state (hydrophilic or hydrophobic, for example), with minimal roughness and minimal surface loss – all on a growing list of different types of materials. In this webcast, experts will identify industry challenges and possible solutions, including a new concept of tailoring chemistries to dissolve very small particles rather than physically removing them.


Advanced Packaging

Mon, 5 May 2014
Thursday, October 16, 2014 at 1 p.m. EST

Back-end packaging is increasingly important to semiconductor device form factor, thermal and power performance, and costs. Compounded by the demand for lead-free processing and the soaring cost of gold, the industry is developing new approaches to packaging, including redistribution layers (RDL), through silicon vias (TSV), copper pillars, wafer-level packaging (WLP) and copper wire bonding. Experts will discuss these and other approaches in this webcast.


Metrology and Failure Analysis

Mon, 5 May 2014
Wednesday, November 12, 2014 at 12 p.m. EST

Continued scaling and more complex device structures, including FinFETs and 3D stacking, are creating new challenges in metrology and inspection. Smaller defects must be detected and analyzed on an increasingly diverse set of materials. Chip makers are looking for better wafer edge inspection techniques, higher resolution metrology tools, 450mm-capability and new compositional analysis solutions.


Trends in Semiconductor Materials

Mon, 5 May 2014
Thursday, November 20, 2014 at 1 p.m. EST

The electronics industry is facing a growing crisis in being able to continue providing cost-effective processes and designs to support the continuation of what’s been referred to as ‘Moore’s Law.’ This ‘Law’, or more accurately ‘observation of the economics involved in scaling integrated circuits,' has been a very useful guideline for several decades, but as with any similar types of projections, has been expected to some day run its course. While the exact timeframe is still uncertain, that ‘day’ is now within sight, and yet there are still no clear paths forward beyond that point. This presentation will provide a brief glimpse of some of the key materials-related challenges that exist within the frontend (devices), lithography, and backend-of-line (chip level interconnects). It will also include just a few of the research concepts that offer some potential paths forward, which the Semiconductor Research Corporation and its member companies are exploring alongside the university researchers they are supporting.