Wed, 4 Apr 2013
Hear from the G450C General Manager, Paul Farrar Jr., on the current status of activities, key milestones and schedules, and imec’s senior business development director, Lode Lauwers, on why 450mm is important for Europe, and the status of 450mm research on processes and devices.
Thu, 3 Mar 2011
The seminar is an ideal fit for anyone interested in characterizing and communicating the light and color properties of LED’s accurately.
Wed, 10 Oct 2011
This webinar will provide an introduction to miniature auto-focus camera technology and voice coil motors.
Mon, 3 Mar 2012
As the industry is incorporating more MEMS devices with integrated magnetic sensors, they are encountering challenges that cannot be overcome with existing toolsets. The deposition and magnetic alignment of these materials are critical for proper device performance and require special hardware configurations and process optimization.
Tue, 3 Mar 2013
As the semiconductor industry moves toward smaller geometries, manufacturing processes are becoming more complex. In particular, they’re more demanding of all the variable parameters on a process tool, including process gas accuracy. Cutting down on variability in the process positively impacts productivity and yield.
Thu, 6 Jun 2012
This webcast will explore the present status of 2.5 and 3D integration, including TSV formation.
Wed, 6 Jun 2010
It will also show some new multi-die DRAM package structures designed to offer improved electrical performance using the existing manufacturing infrastructure.
Tue, 7 Jul 2006
SST On the Scene at SEMICON WestThe Next 10 Years: cost-effective lithography, managing R&D costs, scheduling invention, transitioning to 450mm wafers, and new business models.
With escalating R&D costs, economic challenges associated with lithography past the 32nm half-pitch, and increasing competition between countries and even regions within countries, industry executives have their hands full. Among the questions explored in 14 video interviews conducted at SEMICON West are the following:
- Are finishing fabs the answer to the industry's economic challenges going forward?
- Are ever-larger consortia and alliances feeling growing pains, or does size drive momentum for solutions?
- As the government gets more involved in basic research, will you be happy that someone from the government is there to help you?
- Will high-throughput e-beam direct write lithography be ready in time for 32nm half-pitch?
- Is there a solution to the raw polysilicon availability crunch?
- Are universities competing "too much" with industry?
- Is scheduling invention possible?
Thu, 4 Apr 2006
Looking to improve your bottom line and maximize yield for your next design? This seminar covers the latest causes of yield problems and how the new Calibre DFM tools from Mentor Graphics can help you identify, analyze and modify your designs to increase yield. This seminar also includes a rundown on what Calibre is doing to address random, systematic and parametric yield problems.
Tue, 2 Feb 2006
Hear (and see!) what industry experts at the SPIE Microlithography Conference have to say about extending immersion, the readiness of EUV, and other topics.
Lithographers, maskmakers, and chemists have made great strides in identifying challenges and pursuing solutions that are expected to extend immersion lithography - perhaps to the 32nm half-pitch. Some of the topics our guests tackled include double patterning, CD overlay, using polarized light for specific orientations of features, and its impact on layout design. Guests' impressions of industry's progress in moving EUV along as a viable and cost-effective chip production technology are also shared with viewers, along with opinions about the important developments and papers at the show.
Thu, 5 May 2013
This introduction requires the development of new critical and selective cleans tackling galvanic corrosion, pattern collapse both in FEOL and BEOL process steps. An additional challenge is that the reduction in device size and an increase in device topography makes the removal of small particles even more challenging.
Thu, 3 Mar 2014
March 27, 2014
2.5/3D integration and advanced packaging enable better chip performance in a smaller form factor, meeting the needs of smartphones, tablets, and other advanced devices. However, 2.5/3D packaging creates a new set of manufacturing challenges, such as the need to fabricate copper pillars, TSVs, wafer bumping and redistribution layers – which may involve thicker photoresists, spin-on dielectrics and BCB coatings -- and processing may be done on panels instead of round wafers. In this webcast, experts will detail various options, future scenarios and challenges that must still be overcome.