Sat, 2 Feb 2014
March 2016 (Date and time TBD) / Sponsored by Brewer Science
Die stacking enables better chip performance in a small form factor, meeting the needs of smartphones, tablets, and other advanced devices. Through-silicon vias are moving into volume packaging production, but problems with reliability, cost, and scaling remain. The supply chain also must adjust to this “mid” step between front- and back-end chip production. This webcast will explore the wafer thinning, bonding, TSV formation and other critical process steps necessary to enable 3D integration.
Sun, 2 Feb 2014
February 2016 (Date and time TBD) / Sponsored by Boston Semi Equipment
MEMS have quite different process and material requirements compared to mainstream microprocessor and memory types of devices. This webcast will explore the latest trends in MEMS devices – including sensor fusion, biosensors, energy harvesting – new manufacturing challenges and potential equipment and materials solutions to those challenges.
Wed, 1 Jan 2014
March 2016 (Date and time TBD)
Continued scaling and more complex device structures, including FinFETs and 3D stacking, are creating new challenges in metrology and inspection. Smaller defects must be detected and analyzed on an increasingly diverse set of materials. Chip makers are looking for better wafer edge inspection techniques, higher resolution metrology tools, 450mm-capability and new compositional analysis solutions. Experts will describe new approaches for next generation metrology and inspection, including measurements of CDs, stress, film thickness and non-visual defects.
Sun, 12 Dec 2013
April 2016 (Date and time TBD) / Sponsored by Air ProductsTransistor performance has been greatly improved with strained silicon and high-k metal gates. Further performance improvements could be had by implementing III-V materials in the channel of nMOS transistors. Both III-V and Ge-based channels being considered for the pMOS device. High electron-mobility III-V semiconductors have been intensely researched as alternative channel materials for sub-7 nm technology nodes, but one of the main stumbling blocks is how to integrate them monolithically and cost-effectively with traditional CMOS silicon technology. This webcast will discuss the latest efforts in this area, including vertically stacked III-V nanowire.
Fri, 11 Nov 2013
May 2016 (Date and time TBD) / Sponsored by Zeta Instruments
Wafer level packaging (WLP) using fan-out technology is an attractive platform for achieving low-cost low-profile package solutions for smart-phones and tablets, which require cost-effective, high-density interconnects in small form-factor packaging. Assembled directly on a silicon wafer, the approach is unconstrained by die size, providing the design flexibility to accommodate an unlimited number of interconnects between the package and the application board for maximum connection density, finer line/spacing, improved electrical and thermal performance and small package dimensions to meet the relentless form factor requirements and performance demands of the mobile market. In this webcast, industry experts will explain the FOWLP process, discuss recent advances and forecast future trends.