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Topic Index

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The Path to Future Interconnects

Sun, 5 May 2014
August 6, 2015 at 1:00 p.m. ET

Jon Candelaria, Semiconductor Research Corp.’s director of interconnect and packaging sciences, will summarize a SEMICON West Semiconductor Technology Symposium Session focused on interconnects. He’ll describe the challenges for interconnect technology up to the end of the CMOS roadmap, and a few of the alternatives to address them. Next, he’ll discuss possible directions beyond the roadmap, as well as interconnectivity requirements and solution paths for emerging applications.


Lock-in Thermography for Advanced Assembly Qualification

Thu, 4 Apr 2014

August 26, 2015 at 1:00 p.m. ET

Increasing IoT business opportunities drive a need for new packaging techniques such as FOWLP, Embedded Component Packaging, etc. Such new assembly techniques allow more components and functionality to be integrated into an ever decreasing package space. In parallel the faster product cycle drives the need for faster production ramp to stay competitive. All these challenges highlight the need for a better methodology to determine root cause of assembly-related defects during the new package process qualification process. We will demonstrate a totally non-destructive fault localization method based on a lock-in thermography with examples in these areas.

Advanced Packaging

Thu, 4 Apr 2014

August 2015 (Date and time TBD)

Back-end packaging is increasingly important to semiconductor device form factor, thermal and power performance, and costs. Compounded by the demand for lead-free processing and the soaring cost of gold, the industry is developing new approaches to packaging, including redistribution layers (RDL), through silicon vias (TSV), copper pillars, wafer-level packaging (WLP) and copper wire bonding. Experts will discuss these and other approaches in this webcast.

Metrology

Thu, 4 Apr 2014

September 2015 (Date and time TBD)

Continued scaling and more complex device structures, including FinFETs and 3D stacking, are creating new challenges in metrology and inspection. Smaller defects must be detected and analyzed on an increasingly diverse set of materials. Chip makers are looking for better wafer edge inspection techniques, higher resolution metrology tools, 450mm-capability and new compositional analysis solutions. Experts will describe new approaches for next generation metrology and inspection, including measurements of CDs, stress, film thickness and non-visual defects.

Lithography

Thu, 4 Apr 2014

September 2015 (Date and time TBD)

EUV lithography has been under intense development for years and appears to be close to production. Yet its delay has the industry searching for alternatives, including double, triple and even quadruple patterning, directed self-assembly, multi-e-beam and nanoimprint. In this webcast, experts will detail various options, future scenarios and challenges that must still be overcome.