Wafer Level Packaging

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WAFER LEVEL PACKAGING ARTICLES



Fusion bonding for next-generation 3D-ICs

07/24/2014  Recent developments in wafer bonding technology have demonstrated the ability to achieve improved bond alignment accuracy.

Jordan Valley Semiconductors wins more market share in advanced wafer level packaging

07/03/2014  Jordan Valley Semiconductors Ltd., a supplier of X-ray based metrology tools for advanced semiconductor manufacturing lines, today announced that its micro-spot X-ray Fluorescence (µXRF) metrology tool has been qualified for production monitoring of advanced Wafer Level Packaging (WLP) processes, by another memory player.

ConFab panelists discuss optimizing R&D in the changing semi landscape

06/24/2014  Overheard @The ConFab: “I feel the best I’ve felt about semi since 2009.” –Mike Noonen, Silicon Catalyst

Noise cancellation: The new failure and yield analysis superpower

06/22/2014  Root cause deconvolution is a quick and cost effective way to determine the underlying root causes represented in a population of failing devices from test data alone.

Applied Materials enables cost-effective vertical integration of 3D chips

05/28/2014  Applied Materials, Inc. today introduced the Endura Ventura PVD system that helps customers reduce the cost of fabricating smaller, lower power, high-performance integrated 3D chips.

STATS ChipPAC introduces robust encapsulated wafer level packaging technology

05/28/2014  STATS ChipPAC Ltd., a provider of advanced semiconductor packaging and test services, today introduced encapsulated Wafer Level Chip Scale Package, a packaging technology that raises the industry standard of durability for Wafer Level Chip Scale Packaging (WLCSP).

Ziptronix and EV Group demonstrate submicron accuracies for wafer-to-wafer hybrid bonding

05/27/2014  ­ Ziptronix Inc. and EV Group today announced they have successfully achieved submicron post-bond alignment accuracy on customer-provided 300mm DRAM wafers.

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FINANCIALS



TECHNOLOGY PAPERS



Parylene 101: Learn about the best protection for MEMS

This paper explains the basic history, processes, and applications of the ultimate conformal coating, parylene. Parylene has historically been used to protect printed circuit boards, LEDS, and medical devices from rugged environments and the human body, but now the pin-hole free coating is being used increasingly by the leaders in the MEMS market. With no known chemical that can harm the film, it is a perfect application for fuel tanks, water meters, or any product that must function in a hazardous environment. May 22, 2014
Sponsored by Diamond-MT

Conformal Coatings for Reliable Electronic Assemblies

Modern electronics have become part of our daily lives and the sophisticated electronic circuitry at the heart of these devices and systems must be reliable. Conformal coatings act as a barrier between the electronics and the environment, protecting the areas they cover while strengthening delicate components and traces. Find out more about how conformal coatings enhance the reliability and longevity of electronic printed circuit boards.April 24, 2014
Sponsored by Master Bond, Inc.,

The Next Step in Diagnosis Resolution Improvement

Learn more about RCD as the next step in diagnosis solution enhancement. Where layout-aware diagnosis points to a segment, earn more about RCD as the next step in diagnosis solution enhancement. Where layout-aware diagnosis points to a segment, RCD can isolate a particular root cause in that segment. RCD, a statistical enhancement technology in Tessent Diagnosis and YieldInsight products, is the next step in diagnosis resolution enhancement. It works by analyzing multiple layout diagnosis reports together to identify the underlying defect distribution that is more likely to explain this set of diagnosis results. RCD does not require any additional data beyond what is required for layout-aware diagnosis. This means that RCD fits well into existing diagnosis flows. April 24, 2014
Sponsored by Mentor Graphics

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WEBCASTS



Wet Processing

July 2014 (date and time TBD) Wet processing including wafer cleaning, is one of the most common yet most critical processing step, since it can have a huge impact on the success of the subsequent process step. Not only does it involve the removal of organic and metal contaminants, but it must leave the surface in a desired state (hydrophilic or hydrophobic, for example), with minimal roughness and minimal surface loss – all on a growing list of different types of materials. In this webcast, experts will identify industry challenges and possible solutions.

Sponsored By:
450 Update

July 2014 (date and time TBD) The switch to 450mm will likely be the largest, most expensive retooling the semiconductor industry has ever experienced. Will you be ready? 450mm fabs, which will give an unbeatable competitive advantage to the largest semiconductor manufacturers, are likely to cost $10 billion and come on-line in 2017, with production ramp in 2018. Unprecedented technical challenges still need to be overcome, but work is well underway. This webcast will provide an update on the current status of activities, key milestones and schedules, and the status of 450mm research on processes and devices.

Sponsored By:

Metrology

August 2014 (date and time TBD) Continued scaling and more complex device structures, including FinFETs and 3D stacking, are creating new challenges in metrology and inspection. Smaller defects must be detected and analyzed on an increasingly diverse set of materials. Chip makers are looking for better wafer edge inspection techniques, higher resolution metrology tools, 450mm-capability and new compositional analysis solutions.

Sponsored By:
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