Wafer Level Packaging

MAGAZINE



WAFER LEVEL PACKAGING ARTICLES



North American semiconductor equipment industry posts August 2017 billings 

09/22/2017  Equipment billings in August declined relative to July, signaling a pause in this year's extraordinary growth.

Leading-edge paves the way for pure-play foundry growth

09/20/2017  Sales of ICs built using <40nm process technology forecast to rise 18% at pure-play foundries.

Scientists demonstrated 1.3 μm submilliamp threshold quantum dot micro-lasers on Si

09/18/2017  Decades ago, the Moore's law predicted that the number of transistors in a dense integrated circuit doubles approximately every two years. This prediction was proved to be right in the past few decades, and the quest for ever smaller and more efficient semiconductor devices have been a driving force in breakthroughs in the technology.

IMAPS 2017 to showcase advances in microelectronics technology

09/15/2017  Researchers and exhibitors will showcase their work during a comprehensive conference program of technical papers, panels, special sessions, short courses/tutorials, and an exhibition that will spotlight premier work in the fields of microelectronics, semiconductor packaging and circuit design.

Cadence appoints John Wall as next Chief Financial Officer

09/15/2017  Cadence Design Systems, Inc. today announced that John Wall, corporate vice president of finance and corporate controller of Cadence, has been appointed senior vice president and chief financial officer of Cadence, effective October 1, 2017.

Semiconductor industry records best second quarter in three years

09/14/2017  Despite a slightly down first quarter, the semiconductor industry achieved near record growth in the second quarter of 2017, posting a 6.1 percent growth from the previous quarter, according to IHS Markit.

Cadence delivers design and analysis flow enhancements for TSMC InFO and CoWoS 3D packaging tech

09/13/2017  Cadence Design Systems, Inc. today announced new capabilities that complete its holistic, integrated design flow for TSMC's advanced wafer-level Integrated Fan-Out (InFO) packaging technology.

Fab equipment spending breaking industry records

09/12/2017  2017 fab equipment spending (new and refurbished) is expected to increase by 37 percent, reaching a new annual spending record of about US$55 billion.

The ConFab announces mainstream semiconductor and emerging technologies 2018 conference focus

08/28/2017  The ConFab – an exclusive conference and networking event for semiconductor manufacturing and design executives from leading device makers, OEMs, OSATs, fabs, suppliers and fabless/design companies – announces the 2018 event will be held at THE COSMOPOLITAN of LAS VEGAS on May 20-23.

Semiconductor industry capital spending forecast to jump 20% in 2017

08/22/2017  Samsung remains the “wild card” with regard to 2H17 capital expenditures.

TowerJazz and Tacoma announce a partnership for a new 8-inch fabrication facility in Nanjing, China

08/21/2017  TowerJazz to gain up to 50% of the planned fab loading capacity.

Lam Research takes uniformity control to the edge

08/16/2017  Chipmakers want every part of the wafer to yield good die. Advances in process technologies have just about made this a reality, even as feature dimensions continue to shrink and devices grow more complex.

Mid-year global semiconductor sales up 21% compared to 2016

08/04/2017  Q2 sales are highest on record, 5.8 percent more than previous quarter, 23.7 percent higher than Q2 of last year.

MORE WAFER-LEVEL-PACKAGING ARTICLES

TWITTER


WEBCASTS



3D NAND: Trends in Processes, Circuits

October 3, 2017 at 1 p.m. ET

Conventional planar flash memory technology is approaching critical scaling limitations that are driving the transition to 3D solutions. 3D NAND is expected to scale in height, from 16-bit-tall strings to string heights of more than 128 bits. Meanwhile NAND makers will find ways of placing these strings closer to each other through more aggressive lithography.

Sponsored By:

Materials

Date and time TBD

Success in electronics manufacturing increasingly relies on the materials used in production and packaging. More than 50 different elements from the periodic table are now used in semiconductor manufacturing, and the list grows even longer when you consider the requirements of flexible/printed electronics, LEDs, compound semiconductors, power electronics, displays, MEMS and bioelectronics. In this webcast, experts will focus on changing material requirements, the evolving material supply chain, recent advances in process and packaging materials and substrates, and the role new materials such as carbon nanotubes will play in the future.

Sponsored By:

MEMS

Date and time TBD

MEMS have quite different process and material requirements compared to mainstream microprocessor and memory types of devices. We will explore the latest trends in MEMS devices – including sensor fusion, biosensors, energy harvesting – new manufacturing challenges and potential equipment and materials solutions to those challenges.

Sponsored By:

More Webcasts

TECHNOLOGY PAPERS



Testing PAs under Digital Predistortion and Dynamic Power Supply Conditions

The power amplifier (PA) – as either a discrete component or part of an integrated front end module (FEM) – is one of the most integral RF integrated circuits (RFICs) in the modern radio. In Part 2 of this white paper series, you will learn different techniques for testing PAs via an interactive white paper with multiple how-to videos.September 06, 2017
Sponsored by National Instruments

Learn the Basics of Power Amplifier and Front End Module Measurements

The power amplifier (PA) – as either a discrete component or part of an integrated front end module (FEM) – is one of the most integral RF integrated circuits (RFICs) in the modern radio. Download this white paper to learn the basics of testing RF PAs and FEMs via an interactive white paper with multiple how-to videos.May 22, 2017
Sponsored by National Instruments

Wafer Handler Predictive Monitor and Equipment Verification, Excursion Detection, Defect Reduction & Tool Matching

Consistent equipment performance, avoiding unscheduled downtime, reducing defects and preventing excursions is key to reducing cost and improving die and line yield in semiconductor manufacturing. The fully automated InnerSense SmartWafer (SMW2) system addresses these key metrics. The SMW2 system is effectively being used as a predictive monitor for handler PM’s, a leading indicator for mechanical defects and can detect, predict and prevent most mechanical related excursions, including wafer damage that can lead to subsequent wafer breakage. The SMW2 system can further improve tool availability by improving post PM recovery and tool matching.January 24, 2017
Sponsored by InnerSense

More Technology Papers

EVENTS



Advanced Process Control Conference
Austin, Texas
http://www.apcconference.com
October 09, 2017 - October 12, 2017
IEDM 2017
San Francisco, CA
http://ieee-iedm.org
December 02, 2017 - December 06, 2017
SEMI-THERM
San Jose, CA
http://semi-therm.org
March 19, 2018 - March 23, 2018

VIDEOS