Wafer Level Packaging

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WAFER LEVEL PACKAGING ARTICLES



FlipChip International creates 250 multi-product wafer bump designs

10/01/2014  FlipChip International (FCI), the global technology leader in flip chip bumping and advanced wafer level packaging, announced that their engineering team had completed design and production of the 250th Multi-Product Wafer Bump design since January 2013.

NANIUM launches the industry’s largest WLCSP in volume production

09/23/2014  NANIUM today announced it has successfully launched the industry’s largest Wafer-Level Chip Scale Package (WLCSP) in volume.

Fermilab implements Ziptronix's DBI hybrid bonding in high-end 3D image sensors

09/09/2014  Ziptronix Inc. today announced that its Direct Bond Interconnect (DBI) hybrid bonding has been implemented by Fermi National Accelerator Laboratory (Fermilab) to improve the performance of high-end 3D sensor arrays, which are used for particle detection in large-scale particle physics and x-ray imaging experiments.

STATS ChipPAC’s fcCuBE technology surpasses 100 million unit milestone

08/20/2014  STATS ChipPAC Ltd., a provider of advanced semiconductor packaging and test services, announced today that it has shipped over 100 million semiconductor packages with the company’s fcCuBE technology, advanced flip chip packaging with fine pitch copper (Cu) column bumps, Bond-on-Lead (BOL) interconnection and enhanced assembly processes.

MEMSIC introduces the world's first monolithic and wafer level packaged 3D-axis accelerometer

08/15/2014  MEMSIC, Inc., a MEMS sensing solution provider, announced today the availability of its MXC400xXC, the world's first monolithic 3D accelerometer, and also the first 3D accelerometer to utilize WLP technology.

Pfeiffer Vacuum joins the Facilities 450mm Consortium

08/06/2014  The Facilities 450mm Consortium (F450C), a partnership of leading nanoelectronics facility companies guiding the effort to design and build the next-generation 450mm computer chip fabrication facilities, today announced it has again increased in size, naming Pfeiffer Vacuum as the twelfth member company to join the consortium.

Fusion bonding for next-generation 3D-ICs

07/24/2014  Recent developments in wafer bonding technology have demonstrated the ability to achieve improved bond alignment accuracy.

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FINANCIALS



TECHNOLOGY PAPERS



Conformal Coatings for Reliable Electronic Assemblies

Modern electronics have become part of our daily lives and the sophisticated electronic circuitry at the heart of these devices and systems must be reliable. Conformal coatings act as a barrier between the electronics and the environment, protecting the areas they cover while strengthening delicate components and traces. Find out more about how conformal coatings enhance the reliability and longevity of electronic printed circuit boards.April 24, 2014
Sponsored by Master Bond, Inc.,

The Next Step in Diagnosis Resolution Improvement

Root Cause Deconvolution (RCD), a statistical enhancement technology recently made available in Mentor Graphics’ Tessent Diagnosis and YieldInsight products, is the next step in diagnosis resolution enhancement. It works by analyzing multiple layout-aware diagnosis reports together to identify the underlying defect distribution (root cause distribution) that is most likely to explain this set of diagnosis results. The results are then back- annotated to the individual diagnosis suspects.April 24, 2014
Sponsored by Mentor Graphics

UV LED Curing for the Electronics Industry

This paper provides an introduction to UV LED curing and the many benefits UV LED curing provides for bonding and coating applications in the electronics industry. Product manufacturers, machine builders, and chemistry formulators will gain an understanding of the benefits and how to apply UV LED curing in manufacturing processes. Included are specific examples of how manufacturers are using UV LED to make touch screens, mobile phones, micro speakers, and hard disk drives.April 03, 2014
Sponsored by Phoseon Technology

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WEBCASTS



Advanced Packaging

Oct. 2014 (Date and time TBD)

Back-end packaging is increasingly important to semiconductor device form factor, thermal and power performance, and costs. Compounded by the demand for lead-free processing and the soaring cost of gold, the industry is developing new approaches to packaging, including redistribution layers (RDL), through silicon vias (TSV), copper pillars, wafer-level packaging (WLP) and copper wire bonding. Experts will discuss these and other approaches in this webcast.

Sponsored By:
Metrology

Oct. 2014 (date and time TBD)

Continued scaling and more complex device structures, including FinFETs and 3D stacking, are creating new challenges in metrology and inspection. Smaller defects must be detected and analyzed on an increasingly diverse set of materials. Chip makers are looking for better wafer edge inspection techniques, higher resolution metrology tools, 450mm-capability and new compositional analysis solutions.

Sponsored By:

Interconnects

Oct. 2014 (Date and time TBD)

This webcast will examine the state-of-the-art in conductors and dielectrics, -- including contacts and Metal1 through global level -- pre-metal dielectrics, associated planarization, necessary etch, strip and cleans, embedded passives, global and intermediate TSVs for 3D, as well as reliability, system, and performance issues.

Sponsored By:

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